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authorChris Bainbridge <chrb@gentoo.org>2004-07-26 17:53:25 +0000
committerChris Bainbridge <chrb@gentoo.org>2004-07-26 17:53:25 +0000
commita0a6d724af74927c83737f8442e0f9f4fcda3fae (patch)
tree0761d93501158ed2c4bce4bfc220632c08dc3438 /app-sci
parentchange homepage (diff)
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Diffstat (limited to 'app-sci')
-rw-r--r--app-sci/balsa-async/balsa-async-3.4.ebuild4
1 files changed, 2 insertions, 2 deletions
diff --git a/app-sci/balsa-async/balsa-async-3.4.ebuild b/app-sci/balsa-async/balsa-async-3.4.ebuild
index 107ec2c48803..311ab3bcdabf 100644
--- a/app-sci/balsa-async/balsa-async-3.4.ebuild
+++ b/app-sci/balsa-async/balsa-async-3.4.ebuild
@@ -1,6 +1,6 @@
# Copyright 1999-2004 Gentoo Foundation
# Distributed under the terms of the GNU General Public License v2
-# $Header: /var/cvsroot/gentoo-x86/app-sci/balsa-async/balsa-async-3.4.ebuild,v 1.2 2004/07/26 17:51:47 chrb Exp $
+# $Header: /var/cvsroot/gentoo-x86/app-sci/balsa-async/balsa-async-3.4.ebuild,v 1.3 2004/07/26 17:53:25 chrb Exp $
inherit eutils
@@ -64,7 +64,7 @@ src_compile() {
fi
# config generic verilog backend
-# cd ${WORKDIR}/balsa-tech-verilog-20030204
+# cd ${WORKDIR}/balsa-tech-verilog-20030204
# econf || die "econf failed"
# config Xilinx FPGA backend