diff options
| author |   Nick Clifton <nickc@redhat.com> | 2009-09-29 14:17:19 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2009-09-29 14:17:19 +0000 |
| commit | c7927a3c0ef1d97faf24f1df31baf419e2d92fa1 (patch) | |
| tree | 1945b2f761590ba0f6c3930e7b0e7f1a0387dd33 | |
| parent | opcodes/ (diff) | |
| download | binutils-gdb-c7927a3c0ef1d97faf24f1df31baf419e2d92fa1.tar.gz binutils-gdb-c7927a3c0ef1d97faf24f1df31baf419e2d92fa1.tar.bz2 binutils-gdb-c7927a3c0ef1d97faf24f1df31baf419e2d92fa1.zip | |
bfd
* Makefile.am (ALL_MACHINES): Add cpu-rx.lo.
(ALL_MACHINES_CFILES): Add cpu-rx.c.
(BFD32_BACKENDS): Add elf32-rx.lo.
(BFD32_BACKENDS_CFILES): Add elf32-rx.c.
* archures.c (bfd_architecture): Add bfd_arch_rx and bfd_mach_rx.
Export bfd_rx_arch.
(bfd_archures_list): Add bfd_rx_arch.
* config.bfd: Add entry for rx-*-elf.
* configure.in: Add entries for bfd_elf32_rx_le_vec and
bfd_elf32_rx_be_vec.
* reloc.c: Add RX relocations.
* targets.c: Add RX target vectors.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* cpu-rx.c: New file.
* elf32-rx.c: New file.
binutils
* readelf.c: Add support for RX target.
* MAINTAINERS: Add DJ and NickC as maintainers for RX.
gas
* Makefile.am: Add RX target.
* configure.in: Likewise.
* configure.tgt: Likewise.
* read.c (do_repeat_with_expander): New function.
* read.h: Provide a prototype for do_repeat_with_expander.
* doc/Makefile.am: Add RX target documentation.
* doc/all.texi: Likewise.
* doc/as.texinfo: Likewise.
* Makefile.in: Regenerate.
* NEWS: Mention support for RX architecture.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* config/rx-defs.h: New file.
* config/rx-parse.y: New file.
* config/tc-rx.h: New file.
* config/tc-rx.c: New file.
* doc/c-rx.texi: New file.
gas/testsuite
* gas/rx: New directory.
* gas/rx/*: New set of test cases.
* gas/elf/section2.e-rx: New expected output file.
* gas/all/gas.exp: Add support for RX target.
* gas/elf/elf.exp: Likewise.
* gas/lns/lns.exp: Likewise.
* gas/macros/macros.exp: Likewise.
include
* dis-asm.h: Add prototype for print_insn_rx.
include/elf
* rx.h: New file.
include/opcode
* rx.h: New file.
ld
* Makefile.am: Add rules to build RX emulation.
* configure.tgt: Likewise.
* NEWS: Mention support for RX architecture.
* Makefile.in: Regenerate.
* emulparams/elf32rx.sh: New file.
* emultempl/rxelf.em: New file.
opcodes
* Makefile.am: Add RX files.
* configure.in: Add support for RX target.
* disassemble.c: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* opc2c.c: New file.
* rx-decode.c: New file.
* rx-decode.opc: New file.
* rx-dis.c: New file.
266 files changed, 30415 insertions, 7 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 4ee87317424..ba923a5f496 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,24 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * Makefile.am (ALL_MACHINES): Add cpu-rx.lo. + (ALL_MACHINES_CFILES): Add cpu-rx.c. + (BFD32_BACKENDS): Add elf32-rx.lo. + (BFD32_BACKENDS_CFILES): Add elf32-rx.c. + * archures.c (bfd_architecture): Add bfd_arch_rx and bfd_mach_rx. + Export bfd_rx_arch. + (bfd_archures_list): Add bfd_rx_arch. + * config.bfd: Add entry for rx-*-elf. + * configure.in: Add entries for bfd_elf32_rx_le_vec and + bfd_elf32_rx_be_vec. + * reloc.c: Add RX relocations. + * targets.c: Add RX target vectors. + * Makefile.in: Regenerate. + * bfd-in2.h: Regenerate. + * configure: Regenerate. + * libbfd.h: Regenerate. + * cpu-rx.c: New file. + * elf32-rx.c: New file. + 2009-09-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> * elf32-cr16.c (elf32_cr16_relocate_section): Removed diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 13ace292176..b569f84d82b 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -120,6 +120,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-rx.lo \ cpu-s390.lo \ cpu-score.lo \ cpu-sh.lo \ @@ -191,6 +192,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-rx.c \ cpu-s390.c \ cpu-score.c \ cpu-sh.c \ @@ -307,6 +309,7 @@ BFD32_BACKENDS = \ elf32-or32.lo \ elf32-pj.lo \ elf32-ppc.lo \ + elf32-rx.lo \ elf32-s390.lo \ elf32-sh-symbian.lo \ elf32-sh.lo \ @@ -490,6 +493,7 @@ BFD32_BACKENDS_CFILES = \ elf32-or32.c \ elf32-pj.c \ elf32-ppc.c \ + elf32-rx.c \ elf32-s390.c \ elf32-sh-symbian.c \ elf32-sh.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 721069f05e7..5700ed3b17c 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -415,6 +415,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-rx.lo \ cpu-s390.lo \ cpu-score.lo \ cpu-sh.lo \ @@ -486,6 +487,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-rx.c \ cpu-s390.c \ cpu-score.c \ cpu-sh.c \ @@ -603,6 +605,7 @@ BFD32_BACKENDS = \ elf32-or32.lo \ elf32-pj.lo \ elf32-ppc.lo \ + elf32-rx.lo \ elf32-s390.lo \ elf32-sh-symbian.lo \ elf32-sh.lo \ @@ -786,6 +789,7 @@ BFD32_BACKENDS_CFILES = \ elf32-or32.c \ elf32-pj.c \ elf32-ppc.c \ + elf32-rx.c \ elf32-s390.c \ elf32-sh-symbian.c \ elf32-sh.c \ @@ -1271,6 +1275,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-powerpc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rs6000.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-s390.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-score.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-sh.Plo@am__quote@ @@ -1345,6 +1350,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or32.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s390.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-score.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-score7.Plo@am__quote@ diff --git a/bfd/archures.c b/bfd/archures.c index df73b3f959d..8df2ce1c963 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -380,6 +380,8 @@ DESCRIPTION .#define bfd_mach_cris_v0_v10 255 .#define bfd_mach_cris_v32 32 .#define bfd_mach_cris_v10_v32 1032 +. bfd_arch_rx, {* Renesas RX. *} +.#define bfd_mach_rx 0x75 . bfd_arch_s390, {* IBM s390 *} .#define bfd_mach_s390_31 31 .#define bfd_mach_s390_64 64 @@ -513,6 +515,7 @@ extern const bfd_arch_info_type bfd_plugin_arch; extern const bfd_arch_info_type bfd_powerpc_archs[]; #define bfd_powerpc_arch bfd_powerpc_archs[0] extern const bfd_arch_info_type bfd_rs6000_arch; +extern const bfd_arch_info_type bfd_rx_arch; extern const bfd_arch_info_type bfd_s390_arch; extern const bfd_arch_info_type bfd_score_arch; extern const bfd_arch_info_type bfd_sh_arch; @@ -586,6 +589,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_pdp11_arch, &bfd_powerpc_arch, &bfd_rs6000_arch, + &bfd_rx_arch, &bfd_s390_arch, &bfd_score_arch, &bfd_sh_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index b5fceb7210f..263e0f5ac93 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2047,6 +2047,8 @@ enum bfd_architecture #define bfd_mach_cris_v0_v10 255 #define bfd_mach_cris_v32 32 #define bfd_mach_cris_v10_v32 1032 + bfd_arch_rx, /* Renesas RX. */ +#define bfd_mach_rx 0x75 bfd_arch_s390, /* IBM s390 */ #define bfd_mach_s390_31 31 #define bfd_mach_s390_64 64 @@ -3844,6 +3846,32 @@ instructions */ instructions */ BFD_RELOC_AVR_6_ADIW, +/* Renesas RX Relocations. */ + BFD_RELOC_RX_NEG8, + BFD_RELOC_RX_NEG16, + BFD_RELOC_RX_NEG24, + BFD_RELOC_RX_NEG32, + BFD_RELOC_RX_16_OP, + BFD_RELOC_RX_24_OP, + BFD_RELOC_RX_32_OP, + BFD_RELOC_RX_8U, + BFD_RELOC_RX_16U, + BFD_RELOC_RX_24U, + BFD_RELOC_RX_DIR3U_PCREL, + BFD_RELOC_RX_DIFF, + BFD_RELOC_RX_GPRELB, + BFD_RELOC_RX_GPRELW, + BFD_RELOC_RX_GPRELL, + BFD_RELOC_RX_SYM, + BFD_RELOC_RX_OP_SUBTRACT, + BFD_RELOC_RX_ABS8, + BFD_RELOC_RX_ABS16, + BFD_RELOC_RX_ABS32, + BFD_RELOC_RX_ABS16U, + BFD_RELOC_RX_ABS16UW, + BFD_RELOC_RX_ABS16UL, + BFD_RELOC_RX_RELAX, + /* Direct 12 bit. */ BFD_RELOC_390_12, diff --git a/bfd/config.bfd b/bfd/config.bfd index e3402511374..89b664c7561 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -1191,6 +1191,11 @@ case "${targ}" in targ_selvecs="bfd_powerpcle_pei_vec bfd_powerpc_pei_vec bfd_powerpcle_pe_vec bfd_powerpc_pe_vec" ;; + rx-*-elf) + targ_defvec=bfd_elf32_rx_le_vec + targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec" + ;; + s390-*-linux*) targ_defvec=bfd_elf32_s390_vec targ64_selvecs=bfd_elf64_s390_vec diff --git a/bfd/configure b/bfd/configure index 865ef6964bd..d5aec741700 100755 --- a/bfd/configure +++ b/bfd/configure @@ -14868,6 +14868,8 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_rx_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + bfd_elf32_rx_be_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;; bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;; diff --git a/bfd/configure.in b/bfd/configure.in index bf4dc6cfe12..7ca59b028e0 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -756,6 +756,8 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_rx_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + bfd_elf32_rx_be_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;; bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;; diff --git a/bfd/cpu-rx.c b/bfd/cpu-rx.c new file mode 100644 index 00000000000..92eebb0a647 --- /dev/null +++ b/bfd/cpu-rx.c @@ -0,0 +1,57 @@ +/* BFD support for the RX processor. + Copyright (C) 2008, 2009 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +static const bfd_arch_info_type arch_info_struct[] = +{ + { + 32, /* Bits per word. */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_rx, /* Architecture. */ + bfd_mach_rx, /* Machine. */ + "rx", /* Architecture name. */ + "rx", /* Printable name. */ + 3, /* Section align power. */ + FALSE, /* The default ? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ + NULL /* Next in list. */ + }, +}; + +const bfd_arch_info_type bfd_rx_arch = +{ + 32, /* Bits per word. */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_rx, /* Architecture. */ + bfd_mach_rx, /* Machine. */ + "rx", /* Architecture name. */ + "rx", /* Printable name. */ + 4, /* Section align power. */ + TRUE, /* The default ? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ + & arch_info_struct[0], /* Next in list. */ +}; diff --git a/bfd/elf32-rx.c b/bfd/elf32-rx.c new file mode 100644 index 00000000000..dadd4070347 --- /dev/null +++ b/bfd/elf32-rx.c @@ -0,0 +1,3402 @@ +/* Renesas RX specific support for 32-bit ELF. + Copyright (C) 2008, 2009 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/rx.h" +#include "libiberty.h" + +#define RX_OPCODE_BIG_ENDIAN 0 + +#ifdef DEBUG +char * rx_get_reloc (long); +void dump_symtab (bfd *, void *, void *); +#endif + +#define RXREL(n,sz,bit,shift,complain,pcrel) \ + HOWTO (R_RX_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \ + bfd_elf_generic_reloc, "R_RX_" #n, FALSE, 0, ~0, FALSE) + +/* Note that the relocations around 0x7f are internal to this file; + feel free to move them as needed to avoid conflicts with published + relocation numbers. */ + +static reloc_howto_type rx_elf_howto_table [] = +{ + RXREL (NONE, 0, 0, 0, dont, FALSE), + RXREL (DIR32, 2, 32, 0, signed, FALSE), + RXREL (DIR24S, 2, 24, 0, signed, FALSE), + RXREL (DIR16, 1, 16, 0, dont, FALSE), + RXREL (DIR16U, 1, 16, 0, unsigned, FALSE), + RXREL (DIR16S, 1, 16, 0, signed, FALSE), + RXREL (DIR8, 0, 8, 0, dont, FALSE), + RXREL (DIR8U, 0, 8, 0, unsigned, FALSE), + RXREL (DIR8S, 0, 8, 0, signed, FALSE), + RXREL (DIR24S_PCREL, 2, 24, 0, signed, TRUE), + RXREL (DIR16S_PCREL, 1, 16, 0, signed, TRUE), + RXREL (DIR8S_PCREL, 0, 8, 0, signed, TRUE), + RXREL (DIR16UL, 1, 16, 2, unsigned, FALSE), + RXREL (DIR16UW, 1, 16, 1, unsigned, FALSE), + RXREL (DIR8UL, 0, 8, 2, unsigned, FALSE), + RXREL (DIR8UW, 0, 8, 1, unsigned, FALSE), + RXREL (DIR32_REV, 1, 16, 0, dont, FALSE), + RXREL (DIR16_REV, 1, 16, 0, dont, FALSE), + RXREL (DIR3U_PCREL, 0, 3, 0, dont, TRUE), + + EMPTY_HOWTO (0x13), + EMPTY_HOWTO (0x14), + EMPTY_HOWTO (0x15), + EMPTY_HOWTO (0x16), + EMPTY_HOWTO (0x17), + EMPTY_HOWTO (0x18), + EMPTY_HOWTO (0x19), + EMPTY_HOWTO (0x1a), + EMPTY_HOWTO (0x1b), + EMPTY_HOWTO (0x1c), + EMPTY_HOWTO (0x1d), + EMPTY_HOWTO (0x1e), + EMPTY_HOWTO (0x1f), + + RXREL (RH_3_PCREL, 0, 3, 0, signed, TRUE), + RXREL (RH_16_OP, 1, 16, 0, signed, FALSE), + RXREL (RH_24_OP, 2, 24, 0, signed, FALSE), + RXREL (RH_32_OP, 2, 32, 0, signed, FALSE), + RXREL (RH_24_UNS, 2, 24, 0, unsigned, FALSE), + RXREL (RH_8_NEG, 0, 8, 0, signed, FALSE), + RXREL (RH_16_NEG, 1, 16, 0, signed, FALSE), + RXREL (RH_24_NEG, 2, 24, 0, signed, FALSE), + RXREL (RH_32_NEG, 2, 32, 0, signed, FALSE), + RXREL (RH_DIFF, 2, 32, 0, signed, FALSE), + RXREL (RH_GPRELB, 1, 16, 0, unsigned, FALSE), + RXREL (RH_GPRELW, 1, 16, 0, unsigned, FALSE), + RXREL (RH_GPRELL, 1, 16, 0, unsigned, FALSE), + RXREL (RH_RELAX, 0, 0, 0, dont, FALSE), + + EMPTY_HOWTO (0x2e), + EMPTY_HOWTO (0x2f), + EMPTY_HOWTO (0x30), + EMPTY_HOWTO (0x31), + EMPTY_HOWTO (0x32), + EMPTY_HOWTO (0x33), + EMPTY_HOWTO (0x34), + EMPTY_HOWTO (0x35), + EMPTY_HOWTO (0x36), + EMPTY_HOWTO (0x37), + EMPTY_HOWTO (0x38), + EMPTY_HOWTO (0x39), + EMPTY_HOWTO (0x3a), + EMPTY_HOWTO (0x3b), + EMPTY_HOWTO (0x3c), + EMPTY_HOWTO (0x3d), + EMPTY_HOWTO (0x3e), + EMPTY_HOWTO (0x3f), + EMPTY_HOWTO (0x40), + + RXREL (ABS32, 2, 32, 0, dont, FALSE), + RXREL (ABS24S, 2, 24, 0, signed, FALSE), + RXREL (ABS16, 1, 16, 0, dont, FALSE), + RXREL (ABS16U, 1, 16, 0, unsigned, FALSE), + RXREL (ABS16S, 1, 16, 0, signed, FALSE), + RXREL (ABS8, 0, 8, 0, dont, FALSE), + RXREL (ABS8U, 0, 8, 0, unsigned, FALSE), + RXREL (ABS8S, 0, 8, 0, signed, FALSE), + RXREL (ABS24S_PCREL, 2, 24, 0, signed, TRUE), + RXREL (ABS16S_PCREL, 1, 16, 0, signed, TRUE), + RXREL (ABS8S_PCREL, 0, 8, 0, signed, TRUE), + RXREL (ABS16UL, 1, 16, 0, unsigned, FALSE), + RXREL (ABS16UW, 1, 16, 0, unsigned, FALSE), + RXREL (ABS8UL, 0, 8, 0, unsigned, FALSE), + RXREL (ABS8UW, 0, 8, 0, unsigned, FALSE), + RXREL (ABS32_REV, 2, 32, 0, dont, FALSE), + RXREL (ABS16_REV, 1, 16, 0, dont, FALSE), + +#define STACK_REL_P(x) ((x) <= R_RX_ABS16_REV && (x) >= R_RX_ABS32) + + EMPTY_HOWTO (0x52), + EMPTY_HOWTO (0x53), + EMPTY_HOWTO (0x54), + EMPTY_HOWTO (0x55), + EMPTY_HOWTO (0x56), + EMPTY_HOWTO (0x57), + EMPTY_HOWTO (0x58), + EMPTY_HOWTO (0x59), + EMPTY_HOWTO (0x5a), + EMPTY_HOWTO (0x5b), + EMPTY_HOWTO (0x5c), + EMPTY_HOWTO (0x5d), + EMPTY_HOWTO (0x5e), + EMPTY_HOWTO (0x5f), + EMPTY_HOWTO (0x60), + EMPTY_HOWTO (0x61), + EMPTY_HOWTO (0x62), + EMPTY_HOWTO (0x63), + EMPTY_HOWTO (0x64), + EMPTY_HOWTO (0x65), + EMPTY_HOWTO (0x66), + EMPTY_HOWTO (0x67), + EMPTY_HOWTO (0x68), + EMPTY_HOWTO (0x69), + EMPTY_HOWTO (0x6a), + EMPTY_HOWTO (0x6b), + EMPTY_HOWTO (0x6c), + EMPTY_HOWTO (0x6d), + EMPTY_HOWTO (0x6e), + EMPTY_HOWTO (0x6f), + EMPTY_HOWTO (0x70), + EMPTY_HOWTO (0x71), + EMPTY_HOWTO (0x72), + EMPTY_HOWTO (0x73), + EMPTY_HOWTO (0x74), + EMPTY_HOWTO (0x75), + EMPTY_HOWTO (0x76), + EMPTY_HOWTO (0x77), + + /* These are internal. */ + /* A 5-bit unsigned displacement to a B/W/L address, at bit position 8/12. */ + /* ---- ---- 4--- 3210. */ +#define R_RX_RH_ABS5p8B 0x78 + RXREL (RH_ABS5p8B, 0, 0, 0, dont, FALSE), +#define R_RX_RH_ABS5p8W 0x79 + RXREL (RH_ABS5p8W, 0, 0, 0, dont, FALSE), +#define R_RX_RH_ABS5p8L 0x7a + RXREL (RH_ABS5p8L, 0, 0, 0, dont, FALSE), + /* A 5-bit unsigned displacement to a B/W/L address, at bit position 5/12. */ + /* ---- -432 1--- 0---. */ +#define R_RX_RH_ABS5p5B 0x7b + RXREL (RH_ABS5p5B, 0, 0, 0, dont, FALSE), +#define R_RX_RH_ABS5p5W 0x7c + RXREL (RH_ABS5p5W, 0, 0, 0, dont, FALSE), +#define R_RX_RH_ABS5p5L 0x7d + RXREL (RH_ABS5p5L, 0, 0, 0, dont, FALSE), + /* A 4-bit unsigned immediate at bit position 8. */ +#define R_RX_RH_UIMM4p8 0x7e + RXREL (RH_UIMM4p8, 0, 0, 0, dont, FALSE), + /* A 4-bit negative unsigned immediate at bit position 8. */ +#define R_RX_RH_UNEG4p8 0x7f + RXREL (RH_UNEG4p8, 0, 0, 0, dont, FALSE), + /* End of internal relocs. */ + + RXREL (SYM, 2, 32, 0, dont, FALSE), + RXREL (OPneg, 2, 32, 0, dont, FALSE), + RXREL (OPadd, 2, 32, 0, dont, FALSE), + RXREL (OPsub, 2, 32, 0, dont, FALSE), + RXREL (OPmul, 2, 32, 0, dont, FALSE), + RXREL (OPdiv, 2, 32, 0, dont, FALSE), + RXREL (OPshla, 2, 32, 0, dont, FALSE), + RXREL (OPshra, 2, 32, 0, dont, FALSE), + RXREL (OPsctsize, 2, 32, 0, dont, FALSE), + RXREL (OPscttop, 2, 32, 0, dont, FALSE), + RXREL (OPand, 2, 32, 0, dont, FALSE), + RXREL (OPor, 2, 32, 0, dont, FALSE), + RXREL (OPxor, 2, 32, 0, dont, FALSE), + RXREL (OPnot, 2, 32, 0, dont, FALSE), + RXREL (OPmod, 2, 32, 0, dont, FALSE), + RXREL (OPromtop, 2, 32, 0, dont, FALSE), + RXREL (OPramtop, 2, 32, 0, dont, FALSE) +}; + +/* Map BFD reloc types to RX ELF reloc types. */ + +struct rx_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int rx_reloc_val; +}; + +static const struct rx_reloc_map rx_reloc_map [] = +{ + { BFD_RELOC_NONE, R_RX_NONE }, + { BFD_RELOC_8, R_RX_DIR8S }, + { BFD_RELOC_16, R_RX_DIR16S }, + { BFD_RELOC_24, R_RX_DIR24S }, + { BFD_RELOC_32, R_RX_DIR32 }, + { BFD_RELOC_RX_16_OP, R_RX_DIR16 }, + { BFD_RELOC_RX_DIR3U_PCREL, R_RX_DIR3U_PCREL }, + { BFD_RELOC_8_PCREL, R_RX_DIR8S_PCREL }, + { BFD_RELOC_16_PCREL, R_RX_DIR16S_PCREL }, + { BFD_RELOC_24_PCREL, R_RX_DIR24S_PCREL }, + { BFD_RELOC_RX_8U, R_RX_DIR8U }, + { BFD_RELOC_RX_16U, R_RX_DIR16U }, + { BFD_RELOC_RX_24U, R_RX_RH_24_UNS }, + { BFD_RELOC_RX_NEG8, R_RX_RH_8_NEG }, + { BFD_RELOC_RX_NEG16, R_RX_RH_16_NEG }, + { BFD_RELOC_RX_NEG24, R_RX_RH_24_NEG }, + { BFD_RELOC_RX_NEG32, R_RX_RH_32_NEG }, + { BFD_RELOC_RX_DIFF, R_RX_RH_DIFF }, + { BFD_RELOC_RX_GPRELB, R_RX_RH_GPRELB }, + { BFD_RELOC_RX_GPRELW, R_RX_RH_GPRELW }, + { BFD_RELOC_RX_GPRELL, R_RX_RH_GPRELL }, + { BFD_RELOC_RX_RELAX, R_RX_RH_RELAX }, + { BFD_RELOC_RX_SYM, R_RX_SYM }, + { BFD_RELOC_RX_OP_SUBTRACT, R_RX_OPsub }, + { BFD_RELOC_RX_ABS8, R_RX_ABS8 }, + { BFD_RELOC_RX_ABS16, R_RX_ABS16 }, + { BFD_RELOC_RX_ABS32, R_RX_ABS32 }, + { BFD_RELOC_RX_ABS16UL, R_RX_ABS16UL }, + { BFD_RELOC_RX_ABS16UW, R_RX_ABS16UW }, + { BFD_RELOC_RX_ABS16U, R_RX_ABS16U } +}; + +#define BIGE(abfd) ((abfd)->xvec->byteorder == BFD_ENDIAN_BIG) + +static reloc_howto_type * +rx_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + + if (code == BFD_RELOC_RX_32_OP) + return rx_elf_howto_table + R_RX_DIR32; + + for (i = ARRAY_SIZE (rx_reloc_map); --i;) + if (rx_reloc_map [i].bfd_reloc_val == code) + return rx_elf_howto_table + rx_reloc_map[i].rx_reloc_val; + + return NULL; +} + +static reloc_howto_type * +rx_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char * r_name) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (rx_elf_howto_table); i++) + if (rx_elf_howto_table[i].name != NULL + && strcasecmp (rx_elf_howto_table[i].name, r_name) == 0) + return rx_elf_howto_table + i; + + return NULL; +} + +/* Set the howto pointer for an RX ELF reloc. */ + +static void +rx_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_RX_max); + cache_ptr->howto = rx_elf_howto_table + r_type; +} + +static bfd_vma +get_symbol_value (const char * name, + bfd_reloc_status_type * stat, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + int offset) +{ + bfd_vma value = 0; + struct bfd_link_hash_entry * h; + + h = bfd_link_hash_lookup (info->hash, name, FALSE, FALSE, TRUE); + + if (h == NULL + || (h->type != bfd_link_hash_defined + && h->type != bfd_link_hash_defweak)) + * stat = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, offset, TRUE); + else + value = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + return value; +} + +static bfd_vma +get_gp (bfd_reloc_status_type * stat, + struct bfd_link_info * info, + bfd * abfd, + asection * sec, + int offset) +{ + static bfd_boolean cached = FALSE; + static bfd_vma cached_value = 0; + + if (!cached) + { + cached_value = get_symbol_value ("__gp", stat, info, abfd, sec, offset); + cached = TRUE; + } + return cached_value; +} + +static bfd_vma +get_romstart (bfd_reloc_status_type * stat, + struct bfd_link_info * info, + bfd * abfd, + asection * sec, + int offset) +{ + static bfd_boolean cached = FALSE; + static bfd_vma cached_value = 0; + + if (!cached) + { + cached_value = get_symbol_value ("_start", stat, info, abfd, sec, offset); + cached = TRUE; + } + return cached_value; +} + +static bfd_vma +get_ramstart (bfd_reloc_status_type * stat, + struct bfd_link_info * info, + bfd * abfd, + asection * sec, + int offset) +{ + static bfd_boolean cached = FALSE; + static bfd_vma cached_value = 0; + + if (!cached) + { + cached_value = get_symbol_value ("__datastart", stat, info, abfd, sec, offset); + cached = TRUE; + } + return cached_value; +} + +#define NUM_STACK_ENTRIES 16 +static int32_t rx_stack [ NUM_STACK_ENTRIES ]; +static unsigned int rx_stack_top; + +#define RX_STACK_PUSH(val) \ + do \ + { \ + if (rx_stack_top < NUM_STACK_ENTRIES) \ + rx_stack [rx_stack_top ++] = (val); \ + else \ + r = bfd_reloc_dangerous; \ + } \ + while (0) + +#define RX_STACK_POP(dest) \ + do \ + { \ + if (rx_stack_top > 0) \ + (dest) = rx_stack [-- rx_stack_top]; \ + else \ + (dest) = 0, r = bfd_reloc_dangerous; \ + } \ + while (0) + +/* Relocate an RX ELF section. + There is some attempt to make this function usable for many architectures, + both USE_REL and USE_RELA ['twould be nice if such a critter existed], + if only to serve as a learning tool. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjusting the section contents as + necessary, and (if using Rela relocs and generating a relocatable + output file) adjusting the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocatable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static bfd_boolean +rx_elf_relocate_section + (bfd * output_bfd, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + Elf_Internal_Rela * rel; + Elf_Internal_Rela * relend; + bfd * dynobj; + asection * splt; + + symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + dynobj = elf_hash_table (info)->dynobj; + splt = NULL; + if (dynobj != NULL) + splt = bfd_get_section_by_name (dynobj, ".plt"); + + for (rel = relocs; rel < relend; rel ++) + { + reloc_howto_type * howto; + unsigned long r_symndx; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + bfd_boolean unresolved_reloc = TRUE; + int r_type; + + r_type = ELF32_R_TYPE (rel->r_info); + r_symndx = ELF32_R_SYM (rel->r_info); + + howto = rx_elf_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + relocation = 0; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections [r_symndx]; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (sym->st_name == 0) ? bfd_section_name (input_bfd, sec) : name; + } + else + { + bfd_boolean warned; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, h, + sec, relocation, unresolved_reloc, + warned); + + name = h->root.root.string; + } + + if (sec != NULL && elf_discarded_section (sec)) + { + /* For relocs against symbols from removed linkonce sections, + or sections discarded by a linker script, we just want the + section contents zeroed. Avoid any special processing. */ + _bfd_clear_contents (howto, input_bfd, contents + rel->r_offset); + rel->r_info = 0; + rel->r_addend = 0; + continue; + } + + if (info->relocatable) + { + /* This is a relocatable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION) + rel->r_addend += sec->output_offset; + continue; + } + + if (h != NULL && h->root.type == bfd_link_hash_undefweak) + /* If the symbol is undefined and weak + then the relocation resolves to zero. */ + relocation = 0; + else + { + if (howto->pc_relative) + { + relocation -= (input_section->output_section->vma + + input_section->output_offset + + rel->r_offset); + if (r_type != R_RX_RH_3_PCREL + && r_type != R_RX_DIR3U_PCREL) + relocation ++; + } + + relocation += rel->r_addend; + } + + r = bfd_reloc_ok; + +#define RANGE(a,b) if (a > (long) relocation || (long) relocation > b) r = bfd_reloc_overflow +#define ALIGN(m) if (relocation & m) r = bfd_reloc_other; +#define OP(i) (contents[rel->r_offset + (i)]) +#define WARN_REDHAT(type) \ + _bfd_error_handler (_("%B:%A: Warning: deprecated Red Hat reloc " type " detected against: %s."), \ + input_bfd, input_section, name) + + /* Opcode relocs are always big endian. Data relocs are bi-endian. */ + switch (r_type) + { + case R_RX_NONE: + break; + + case R_RX_RH_RELAX: + break; + + case R_RX_RH_3_PCREL: + WARN_REDHAT ("RX_RH_3_PCREL"); + RANGE (3, 10); + OP (0) &= 0xf8; + OP (0) |= relocation & 0x07; + break; + + case R_RX_RH_8_NEG: + WARN_REDHAT ("RX_RH_8_NEG"); + relocation = - relocation; + case R_RX_DIR8S_PCREL: + RANGE (-128, 127); + OP (0) = relocation; + break; + + case R_RX_DIR8S: + RANGE (-128, 255); + OP (0) = relocation; + break; + + case R_RX_DIR8U: + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RX_RH_16_NEG: + WARN_REDHAT ("RX_RH_16_NEG"); + relocation = - relocation; + case R_RX_DIR16S_PCREL: + RANGE (-32768, 32767); +#if RX_OPCODE_BIG_ENDIAN +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_RH_16_OP: + WARN_REDHAT ("RX_RH_16_OP"); + RANGE (-32768, 32767); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_DIR16S: + RANGE (-32768, 65535); + if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE)) + { + OP (1) = relocation; + OP (0) = relocation >> 8; + } + else + { + OP (0) = relocation; + OP (1) = relocation >> 8; + } + break; + + case R_RX_DIR16U: + RANGE (0, 65536); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_DIR16: + RANGE (-32768, 65536); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_DIR16_REV: + RANGE (-32768, 65536); +#if RX_OPCODE_BIG_ENDIAN + OP (0) = relocation; + OP (1) = relocation >> 8; +#else + OP (1) = relocation; + OP (0) = relocation >> 8; +#endif + break; + + case R_RX_DIR3U_PCREL: + RANGE (3, 10); + OP (0) &= 0xf8; + OP (0) |= relocation & 0x07; + break; + + case R_RX_RH_24_NEG: + WARN_REDHAT ("RX_RH_24_NEG"); + relocation = - relocation; + case R_RX_DIR24S_PCREL: + RANGE (-0x800000, 0x7fffff); +#if RX_OPCODE_BIG_ENDIAN + OP (2) = relocation; + OP (1) = relocation >> 8; + OP (0) = relocation >> 16; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; +#endif + break; + + case R_RX_RH_24_OP: + WARN_REDHAT ("RX_RH_24_OP"); + RANGE (-0x800000, 0x7fffff); +#if RX_OPCODE_BIG_ENDIAN + OP (2) = relocation; + OP (1) = relocation >> 8; + OP (0) = relocation >> 16; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; +#endif + break; + + case R_RX_DIR24S: + RANGE (-0x800000, 0x7fffff); + if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE)) + { + OP (2) = relocation; + OP (1) = relocation >> 8; + OP (0) = relocation >> 16; + } + else + { + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + } + break; + + case R_RX_RH_24_UNS: + WARN_REDHAT ("RX_RH_24_UNS"); + RANGE (0, 0xffffff); +#if RX_OPCODE_BIG_ENDIAN + OP (2) = relocation; + OP (1) = relocation >> 8; + OP (0) = relocation >> 16; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; +#endif + break; + + case R_RX_RH_32_NEG: + WARN_REDHAT ("RX_RH_32_NEG"); + relocation = - relocation; +#if RX_OPCODE_BIG_ENDIAN + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; +#endif + break; + + case R_RX_RH_32_OP: + WARN_REDHAT ("RX_RH_32_OP"); +#if RX_OPCODE_BIG_ENDIAN + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; +#endif + break; + + case R_RX_DIR32: + if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE)) + { + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; + } + else + { + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; + } + break; + + case R_RX_DIR32_REV: + if (BIGE (output_bfd)) + { + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; + } + else + { + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; + } + break; + + case R_RX_RH_DIFF: + { + bfd_vma val; + WARN_REDHAT ("RX_RH_DIFF"); + val = bfd_get_32 (output_bfd, & OP (0)); + val -= relocation; + bfd_put_32 (output_bfd, val, & OP (0)); + } + break; + + case R_RX_RH_GPRELB: + WARN_REDHAT ("RX_RH_GPRELB"); + relocation -= get_gp (&r, info, input_bfd, input_section, rel->r_offset); + RANGE (0, 65535); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_RH_GPRELW: + WARN_REDHAT ("RX_RH_GPRELW"); + relocation -= get_gp (&r, info, input_bfd, input_section, rel->r_offset); + ALIGN (1); + relocation >>= 1; + RANGE (0, 65535); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_RH_GPRELL: + WARN_REDHAT ("RX_RH_GPRELL"); + relocation -= get_gp (&r, info, input_bfd, input_section, rel->r_offset); + ALIGN (3); + relocation >>= 2; + RANGE (0, 65535); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + /* Internal relocations just for relaxation: */ + case R_RX_RH_ABS5p5B: + RX_STACK_POP (relocation); + RANGE (0, 31); + OP (0) &= 0xf8; + OP (0) |= relocation >> 2; + OP (1) &= 0x77; + OP (1) |= (relocation << 6) & 0x80; + OP (1) |= (relocation << 3) & 0x08; + break; + + case R_RX_RH_ABS5p5W: + RX_STACK_POP (relocation); + RANGE (0, 62); + ALIGN (1); + relocation >>= 1; + OP (0) &= 0xf8; + OP (0) |= relocation >> 2; + OP (1) &= 0x77; + OP (1) |= (relocation << 6) & 0x80; + OP (1) |= (relocation << 3) & 0x08; + break; + + case R_RX_RH_ABS5p5L: + RX_STACK_POP (relocation); + RANGE (0, 124); + ALIGN (3); + relocation >>= 2; + OP (0) &= 0xf8; + OP (0) |= relocation >> 2; + OP (1) &= 0x77; + OP (1) |= (relocation << 6) & 0x80; + OP (1) |= (relocation << 3) & 0x08; + break; + + case R_RX_RH_ABS5p8B: + RX_STACK_POP (relocation); + RANGE (0, 31); + OP (0) &= 0x70; + OP (0) |= (relocation << 3) & 0x80; + OP (0) |= relocation & 0x0f; + break; + + case R_RX_RH_ABS5p8W: + RX_STACK_POP (relocation); + RANGE (0, 62); + ALIGN (1); + relocation >>= 1; + OP (0) &= 0x70; + OP (0) |= (relocation << 3) & 0x80; + OP (0) |= relocation & 0x0f; + break; + + case R_RX_RH_ABS5p8L: + RX_STACK_POP (relocation); + RANGE (0, 124); + ALIGN (3); + relocation >>= 2; + OP (0) &= 0x70; + OP (0) |= (relocation << 3) & 0x80; + OP (0) |= relocation & 0x0f; + break; + + case R_RX_RH_UIMM4p8: + RANGE (0, 15); + OP (0) &= 0x0f; + OP (0) |= relocation << 4; + break; + + case R_RX_RH_UNEG4p8: + RANGE (-15, 0); + OP (0) &= 0x0f; + OP (0) |= (-relocation) << 4; + break; + + /* Complex reloc handling: */ + + case R_RX_ABS32: + RX_STACK_POP (relocation); +#if RX_OPCODE_BIG_ENDIAN + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; +#endif + break; + + case R_RX_ABS32_REV: + RX_STACK_POP (relocation); +#if RX_OPCODE_BIG_ENDIAN + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + OP (3) = relocation >> 24; +#else + OP (3) = relocation; + OP (2) = relocation >> 8; + OP (1) = relocation >> 16; + OP (0) = relocation >> 24; +#endif + break; + + case R_RX_ABS24S_PCREL: + case R_RX_ABS24S: + RX_STACK_POP (relocation); + RANGE (-0x800000, 0x7fffff); + if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE)) + { + OP (2) = relocation; + OP (1) = relocation >> 8; + OP (0) = relocation >> 16; + } + else + { + OP (0) = relocation; + OP (1) = relocation >> 8; + OP (2) = relocation >> 16; + } + break; + + case R_RX_ABS16: + RX_STACK_POP (relocation); + RANGE (-32768, 65535); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_ABS16_REV: + RX_STACK_POP (relocation); + RANGE (-32768, 65535); +#if RX_OPCODE_BIG_ENDIAN + OP (0) = relocation; + OP (1) = relocation >> 8; +#else + OP (1) = relocation; + OP (0) = relocation >> 8; +#endif + break; + + case R_RX_ABS16S_PCREL: + case R_RX_ABS16S: + RX_STACK_POP (relocation); + RANGE (-32768, 32767); + if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE)) + { + OP (1) = relocation; + OP (0) = relocation >> 8; + } + else + { + OP (0) = relocation; + OP (1) = relocation >> 8; + } + break; + + case R_RX_ABS16U: + RX_STACK_POP (relocation); + RANGE (0, 65536); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_ABS16UL: + RX_STACK_POP (relocation); + relocation >>= 2; + RANGE (0, 65536); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_ABS16UW: + RX_STACK_POP (relocation); + relocation >>= 1; + RANGE (0, 65536); +#if RX_OPCODE_BIG_ENDIAN + OP (1) = relocation; + OP (0) = relocation >> 8; +#else + OP (0) = relocation; + OP (1) = relocation >> 8; +#endif + break; + + case R_RX_ABS8: + RX_STACK_POP (relocation); + RANGE (-128, 255); + OP (0) = relocation; + break; + + case R_RX_ABS8U: + RX_STACK_POP (relocation); + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RX_ABS8UL: + RX_STACK_POP (relocation); + relocation >>= 2; + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RX_ABS8UW: + RX_STACK_POP (relocation); + relocation >>= 1; + RANGE (0, 255); + OP (0) = relocation; + break; + + case R_RX_ABS8S_PCREL: + case R_RX_ABS8S: + RX_STACK_POP (relocation); + RANGE (-128, 127); + OP (0) = relocation; + break; + + case R_RX_SYM: + if (r_symndx < symtab_hdr->sh_info) + RX_STACK_PUSH (sec->output_section->vma + + sec->output_offset + + sym->st_value); + else + { + if (h != NULL + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)) + RX_STACK_PUSH (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + else + _bfd_error_handler (_("Warning: RX_SYM reloc with an unknown symbol")); + } + break; + + case R_RX_OPneg: + { + int32_t tmp; + + RX_STACK_POP (tmp); + tmp = - tmp; + RX_STACK_PUSH (tmp); + } + break; + + case R_RX_OPadd: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 += tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPsub: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp2 -= tmp1; + RX_STACK_PUSH (tmp2); + } + break; + + case R_RX_OPmul: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 *= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPdiv: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 /= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPshla: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 <<= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPshra: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 >>= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPsctsize: + RX_STACK_PUSH (input_section->size); + break; + + case R_RX_OPscttop: + RX_STACK_PUSH (input_section->output_section->vma); + break; + + case R_RX_OPand: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 &= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPor: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 |= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPxor: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 ^= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPnot: + { + int32_t tmp; + + RX_STACK_POP (tmp); + tmp = ~ tmp; + RX_STACK_PUSH (tmp); + } + break; + + case R_RX_OPmod: + { + int32_t tmp1, tmp2; + + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 %= tmp2; + RX_STACK_PUSH (tmp1); + } + break; + + case R_RX_OPromtop: + RX_STACK_PUSH (get_romstart (&r, info, input_bfd, input_section, rel->r_offset)); + break; + + case R_RX_OPramtop: + RX_STACK_PUSH (get_ramstart (&r, info, input_bfd, input_section, rel->r_offset)); + break; + + default: + r = bfd_reloc_notsupported; + break; + } + + if (r != bfd_reloc_ok) + { + const char * msg = NULL; + + switch (r) + { + case bfd_reloc_overflow: + /* Catch the case of a missing function declaration + and emit a more helpful error message. */ + if (r_type == R_RX_DIR24S_PCREL) + msg = _("%B(%A): error: call to undefined function '%s'"); + else + r = info->callbacks->reloc_overflow + (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, + TRUE); + break; + + case bfd_reloc_other: + msg = _("%B(%A): warning: unaligned access to symbol '%s' in the small data area"); + break; + + case bfd_reloc_outofrange: + msg = _("%B(%A): internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("%B(%A): internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("%B(%A): internal error: dangerous relocation"); + break; + + default: + msg = _("%B(%A): internal error: unknown error"); + break; + } + + if (msg) + _bfd_error_handler (msg, input_bfd, input_section, name); + + if (! r) + return FALSE; + } + } + + return TRUE; +} + +/* Relaxation Support. */ + +/* Progression of relocations from largest operand size to smallest + operand size. */ + +static int +next_smaller_reloc (int r) +{ + switch (r) + { + case R_RX_DIR32: return R_RX_DIR24S; + case R_RX_DIR24S: return R_RX_DIR16S; + case R_RX_DIR16S: return R_RX_DIR8S; + case R_RX_DIR8S: return R_RX_NONE; + + case R_RX_DIR16: return R_RX_DIR8; + case R_RX_DIR8: return R_RX_NONE; + + case R_RX_DIR16U: return R_RX_DIR8U; + case R_RX_DIR8U: return R_RX_NONE; + + case R_RX_DIR24S_PCREL: return R_RX_DIR16S_PCREL; + case R_RX_DIR16S_PCREL: return R_RX_DIR8S_PCREL; + case R_RX_DIR8S_PCREL: return R_RX_DIR3U_PCREL; + + case R_RX_DIR16UL: return R_RX_DIR8UL; + case R_RX_DIR8UL: return R_RX_NONE; + case R_RX_DIR16UW: return R_RX_DIR8UW; + case R_RX_DIR8UW: return R_RX_NONE; + + case R_RX_RH_32_OP: return R_RX_RH_24_OP; + case R_RX_RH_24_OP: return R_RX_RH_16_OP; + case R_RX_RH_16_OP: return R_RX_DIR8; + + case R_RX_ABS32: return R_RX_ABS24S; + case R_RX_ABS24S: return R_RX_ABS16S; + case R_RX_ABS16: return R_RX_ABS8; + case R_RX_ABS16U: return R_RX_ABS8U; + case R_RX_ABS16S: return R_RX_ABS8S; + case R_RX_ABS8: return R_RX_NONE; + case R_RX_ABS8U: return R_RX_NONE; + case R_RX_ABS8S: return R_RX_NONE; + case R_RX_ABS24S_PCREL: return R_RX_ABS16S_PCREL; + case R_RX_ABS16S_PCREL: return R_RX_ABS8S_PCREL; + case R_RX_ABS8S_PCREL: return R_RX_NONE; + case R_RX_ABS16UL: return R_RX_ABS8UL; + case R_RX_ABS16UW: return R_RX_ABS8UW; + case R_RX_ABS8UL: return R_RX_NONE; + case R_RX_ABS8UW: return R_RX_NONE; + } + return r; +}; + +/* Delete some bytes from a section while relaxing. */ + +static bfd_boolean +elf32_rx_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, int count, + Elf_Internal_Rela *alignment_rel, int force_snip) +{ + Elf_Internal_Shdr * symtab_hdr; + unsigned int sec_shndx; + bfd_byte * contents; + Elf_Internal_Rela * irel; + Elf_Internal_Rela * irelend; + Elf_Internal_Rela * irelalign; + Elf_Internal_Sym * isym; + Elf_Internal_Sym * isymend; + bfd_vma toaddr; + unsigned int symcount; + struct elf_link_hash_entry ** sym_hashes; + struct elf_link_hash_entry ** end_hashes; + + if (!alignment_rel) + force_snip = 1; + + sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); + + contents = elf_section_data (sec)->this_hdr.contents; + + /* The deletion must stop at the next alignment boundary, if + ALIGNMENT_REL is non-NULL. */ + irelalign = NULL; + toaddr = sec->size; + if (alignment_rel) + toaddr = alignment_rel->r_offset; + + irel = elf_section_data (sec)->relocs; + irelend = irel + sec->reloc_count; + + /* Actually delete the bytes. */ + memmove (contents + addr, contents + addr + count, + (size_t) (toaddr - addr - count)); + + /* If we don't have an alignment marker to worry about, we can just + shrink the section. Otherwise, we have to fill in the newly + created gap with NOP insns (0x03). */ + if (force_snip) + sec->size -= count; + else + memset (contents + toaddr - count, 0x03, count); + + /* Adjust all the relocs. */ + for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++) + { + /* Get the new reloc address. */ + if (irel->r_offset > addr + && (irel->r_offset < toaddr + || (force_snip && irel->r_offset == toaddr))) + irel->r_offset -= count; + + /* If we see an ALIGN marker at the end of the gap, we move it + to the beginning of the gap, since marking these gaps is what + they're for. */ + if (irel->r_offset == toaddr + && ELF32_R_TYPE (irel->r_info) == R_RX_RH_RELAX + && irel->r_addend & RX_RELAXA_ALIGN) + irel->r_offset -= count; + } + + /* Adjust the local symbols defined in this section. */ + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + isym = (Elf_Internal_Sym *) symtab_hdr->contents; + isymend = isym + symtab_hdr->sh_info; + + for (; isym < isymend; isym++) + { + /* If the symbol is in the range of memory we just moved, we + have to adjust its value. */ + if (isym->st_shndx == sec_shndx + && isym->st_value > addr + && isym->st_value < toaddr) + isym->st_value -= count; + + /* If the symbol *spans* the bytes we just deleted (i.e. it's + *end* is in the moved bytes but it's *start* isn't), then we + must adjust its size. */ + if (isym->st_shndx == sec_shndx + && isym->st_value < addr + && isym->st_value + isym->st_size > addr + && isym->st_value + isym->st_size < toaddr) + isym->st_size -= count; + } + + /* Now adjust the global symbols defined in this section. */ + symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) + - symtab_hdr->sh_info); + sym_hashes = elf_sym_hashes (abfd); + end_hashes = sym_hashes + symcount; + + for (; sym_hashes < end_hashes; sym_hashes++) + { + struct elf_link_hash_entry *sym_hash = *sym_hashes; + + if ((sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec) + { + /* As above, adjust the value if needed. */ + if (sym_hash->root.u.def.value > addr + && sym_hash->root.u.def.value < toaddr) + sym_hash->root.u.def.value -= count; + + /* As above, adjust the size if needed. */ + if (sym_hash->root.u.def.value < addr + && sym_hash->root.u.def.value + sym_hash->size > addr + && sym_hash->root.u.def.value + sym_hash->size < toaddr) + sym_hash->size -= count; + } + } + + return TRUE; +} + +/* Used to sort relocs by address. If relocs have the same address, + we maintain their relative order, except that R_RX_RH_RELAX + alignment relocs must be the first reloc for any given address. */ + +static void +reloc_bubblesort (Elf_Internal_Rela * r, int count) +{ + int i; + bfd_boolean again; + bfd_boolean swappit; + + /* This is almost a classic bubblesort. It's the slowest sort, but + we're taking advantage of the fact that the relocations are + mostly in order already (the assembler emits them that way) and + we need relocs with the same address to remain in the same + relative order. */ + again = TRUE; + while (again) + { + again = FALSE; + for (i = 0; i < count - 1; i ++) + { + if (r[i].r_offset > r[i + 1].r_offset) + swappit = TRUE; + else if (r[i].r_offset < r[i + 1].r_offset) + swappit = FALSE; + else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RX_RH_RELAX + && (r[i + 1].r_addend & RX_RELAXA_ALIGN)) + swappit = TRUE; + else if (ELF32_R_TYPE (r[i + 1].r_info) == R_RX_RH_RELAX + && (r[i + 1].r_addend & RX_RELAXA_ELIGN) + && !(ELF32_R_TYPE (r[i].r_info) == R_RX_RH_RELAX + && (r[i].r_addend & RX_RELAXA_ALIGN))) + swappit = TRUE; + else + swappit = FALSE; + + if (swappit) + { + Elf_Internal_Rela tmp; + + tmp = r[i]; + r[i] = r[i + 1]; + r[i + 1] = tmp; + /* If we do move a reloc back, re-scan to see if it + needs to be moved even further back. This avoids + most of the O(n^2) behavior for our cases. */ + if (i > 0) + i -= 2; + again = TRUE; + } + } + } +} + + +#define OFFSET_FOR_RELOC(rel, lrel, scale) \ + rx_offset_for_reloc (abfd, rel + 1, symtab_hdr, shndx_buf, intsyms, \ + lrel, abfd, sec, link_info, scale) + +static bfd_vma +rx_offset_for_reloc (bfd * abfd, + Elf_Internal_Rela * rel, + Elf_Internal_Shdr * symtab_hdr, + Elf_External_Sym_Shndx * shndx_buf, + Elf_Internal_Sym * intsyms, + Elf_Internal_Rela ** lrel, + bfd * input_bfd, + asection * input_section, + struct bfd_link_info * info, + int * scale) +{ + bfd_vma symval; + bfd_reloc_status_type r; + + *scale = 1; + + /* REL is the first of 1..N relocations. We compute the symbol + value for each relocation, then combine them if needed. LREL + gets a pointer to the last relocation used. */ + while (1) + { + int32_t tmp1, tmp2; + + /* Get the value of the symbol referred to by the reloc. */ + if (ELF32_R_SYM (rel->r_info) < symtab_hdr->sh_info) + { + /* A local symbol. */ + Elf_Internal_Sym *isym; + Elf_External_Sym_Shndx *shndx; + asection *ssec; + + isym = intsyms + ELF32_R_SYM (rel->r_info); + + if (isym->st_shndx == SHN_UNDEF) + ssec = bfd_und_section_ptr; + else if (isym->st_shndx == SHN_ABS) + ssec = bfd_abs_section_ptr; + else if (isym->st_shndx == SHN_COMMON) + ssec = bfd_com_section_ptr; + else + ssec = bfd_section_from_elf_index (abfd, + isym->st_shndx); + + shndx = shndx_buf + (shndx_buf ? ELF32_R_SYM (rel->r_info) : 0); + + /* Initial symbol value. */ + symval = isym->st_value; + + /* GAS may have made this symbol relative to a section, in + which case, we have to add the addend to find the + symbol. */ + if (ELF_ST_TYPE (isym->st_info) == STT_SECTION) + symval += rel->r_addend; + + if (ssec) + { + if ((ssec->flags & SEC_MERGE) + && ssec->sec_info_type == ELF_INFO_TYPE_MERGE) + symval = _bfd_merged_section_offset (abfd, & ssec, + elf_section_data (ssec)->sec_info, + symval); + } + + /* Now make the offset relative to where the linker is putting it. */ + if (ssec) + symval += + ssec->output_section->vma + ssec->output_offset; + + symval += rel->r_addend; + } + else + { + unsigned long indx; + struct elf_link_hash_entry * h; + + /* An external symbol. */ + indx = ELF32_R_SYM (rel->r_info) - symtab_hdr->sh_info; + h = elf_sym_hashes (abfd)[indx]; + BFD_ASSERT (h != NULL); + + if (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak) + { + /* This appears to be a reference to an undefined + symbol. Just ignore it--it will be caught by the + regular reloc processing. */ + if (lrel) + *lrel = rel; + return 0; + } + + symval = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + + symval += rel->r_addend; + } + + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_RX_SYM: + RX_STACK_PUSH (symval); + break; + + case R_RX_OPneg: + RX_STACK_POP (tmp1); + tmp1 = - tmp1; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPadd: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 += tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPsub: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp2 -= tmp1; + RX_STACK_PUSH (tmp2); + break; + + case R_RX_OPmul: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 *= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPdiv: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 /= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPshla: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 <<= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPshra: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 >>= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPsctsize: + RX_STACK_PUSH (input_section->size); + break; + + case R_RX_OPscttop: + RX_STACK_PUSH (input_section->output_section->vma); + break; + + case R_RX_OPand: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 &= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPor: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 |= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPxor: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 ^= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPnot: + RX_STACK_POP (tmp1); + tmp1 = ~ tmp1; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPmod: + RX_STACK_POP (tmp1); + RX_STACK_POP (tmp2); + tmp1 %= tmp2; + RX_STACK_PUSH (tmp1); + break; + + case R_RX_OPromtop: + RX_STACK_PUSH (get_romstart (&r, info, input_bfd, input_section, rel->r_offset)); + break; + + case R_RX_OPramtop: + RX_STACK_PUSH (get_ramstart (&r, info, input_bfd, input_section, rel->r_offset)); + break; + + case R_RX_DIR16UL: + case R_RX_DIR8UL: + case R_RX_ABS16UL: + case R_RX_ABS8UL: + if (rx_stack_top) + RX_STACK_POP (symval); + if (lrel) + *lrel = rel; + *scale = 4; + return symval; + + case R_RX_DIR16UW: + case R_RX_DIR8UW: + case R_RX_ABS16UW: + case R_RX_ABS8UW: + if (rx_stack_top) + RX_STACK_POP (symval); + if (lrel) + *lrel = rel; + *scale = 2; + return symval; + + default: + if (rx_stack_top) + RX_STACK_POP (symval); + if (lrel) + *lrel = rel; + return symval; + } + + rel ++; + } +} + +static void +move_reloc (Elf_Internal_Rela * irel, Elf_Internal_Rela * srel, int delta) +{ + bfd_vma old_offset = srel->r_offset; + + irel ++; + while (irel <= srel) + { + if (irel->r_offset == old_offset) + irel->r_offset += delta; + irel ++; + } +} + +/* Relax one section. */ + +static bfd_boolean +elf32_rx_relax_section (bfd * abfd, + asection * sec, + struct bfd_link_info * link_info, + bfd_boolean * again, + bfd_boolean allow_pcrel3) +{ + Elf_Internal_Shdr * symtab_hdr; + Elf_Internal_Shdr * shndx_hdr; + Elf_Internal_Rela * internal_relocs; + Elf_Internal_Rela * free_relocs = NULL; + Elf_Internal_Rela * irel; + Elf_Internal_Rela * srel; + Elf_Internal_Rela * irelend; + Elf_Internal_Rela * next_alignment; + Elf_Internal_Rela * prev_alignment; + bfd_byte * contents = NULL; + bfd_byte * free_contents = NULL; + Elf_Internal_Sym * intsyms = NULL; + Elf_Internal_Sym * free_intsyms = NULL; + Elf_External_Sym_Shndx * shndx_buf = NULL; + bfd_vma pc; + bfd_vma sec_start; + bfd_vma sec_end; + bfd_vma symval = 0; + int pcrel = 0; + int code = 0; + int section_alignment_glue; + /* how much to scale the relocation by - 1, 2, or 4. */ + int scale; + + /* Assume nothing changes. */ + *again = FALSE; + + /* We don't have to do anything for a relocatable link, if + this section does not have relocs, or if this is not a + code section. */ + if (link_info->relocatable + || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 + || (sec->flags & SEC_CODE) == 0) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr; + + sec_start = sec->output_section->vma + sec->output_offset; + sec_end = sec->output_section->vma + sec->output_offset + sec->size; + + /* Get the section contents. */ + if (elf_section_data (sec)->this_hdr.contents != NULL) + contents = elf_section_data (sec)->this_hdr.contents; + /* Go get them off disk. */ + else + { + if (! bfd_malloc_and_get_section (abfd, sec, &contents)) + goto error_return; + elf_section_data (sec)->this_hdr.contents = contents; + } + + /* Read this BFD's symbols. */ + /* Get cached copy if it exists. */ + if (symtab_hdr->contents != NULL) + intsyms = (Elf_Internal_Sym *) symtab_hdr->contents; + else + { + intsyms = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, 0, NULL, NULL, NULL); + symtab_hdr->contents = (bfd_byte *) intsyms; + } + + if (shndx_hdr->sh_size != 0) + { + bfd_size_type amt; + + amt = symtab_hdr->sh_info; + amt *= sizeof (Elf_External_Sym_Shndx); + shndx_buf = (Elf_External_Sym_Shndx *) bfd_malloc (amt); + if (shndx_buf == NULL) + goto error_return; + if (bfd_seek (abfd, shndx_hdr->sh_offset, SEEK_SET) != 0 + || bfd_bread ((PTR) shndx_buf, amt, abfd) != amt) + goto error_return; + shndx_hdr->contents = (bfd_byte *) shndx_buf; + } + + /* Get a copy of the native relocations. */ + internal_relocs = (_bfd_elf_link_read_relocs + (abfd, sec, (PTR) NULL, (Elf_Internal_Rela *) NULL, + link_info->keep_memory)); + if (internal_relocs == NULL) + goto error_return; + if (! link_info->keep_memory) + free_relocs = internal_relocs; + + /* The RL_ relocs must be just before the operand relocs they go + with, so we must sort them to guarantee this. We use bubblesort + instead of qsort so we can guarantee that relocs with the same + address remain in the same relative order. */ + reloc_bubblesort (internal_relocs, sec->reloc_count); + + /* Walk through them looking for relaxing opportunities. */ + irelend = internal_relocs + sec->reloc_count; + + /* This will either be NULL or a pointer to the next alignment + relocation. */ + next_alignment = internal_relocs; + /* This will be the previous alignment, although at first it points + to the first real relocation. */ + prev_alignment = internal_relocs; + + /* We calculate worst case shrinkage caused by alignment directives. + No fool-proof, but better than either ignoring the problem or + doing heavy duty analysis of all the alignment markers in all + input sections. */ + section_alignment_glue = 0; + for (irel = internal_relocs; irel < irelend; irel++) + if (ELF32_R_TYPE (irel->r_info) == R_RX_RH_RELAX + && irel->r_addend & RX_RELAXA_ALIGN) + { + int this_glue = 1 << (irel->r_addend & RX_RELAXA_ANUM); + + if (section_alignment_glue < this_glue) + section_alignment_glue = this_glue; + } + /* Worst case is all 0..N alignments, in order, causing 2*N-1 byte + shrinkage. */ + section_alignment_glue *= 2; + + for (irel = internal_relocs; irel < irelend; irel++) + { + unsigned char *insn; + int nrelocs; + + /* The insns we care about are all marked with one of these. */ + if (ELF32_R_TYPE (irel->r_info) != R_RX_RH_RELAX) + continue; + + if (irel->r_addend & RX_RELAXA_ALIGN + || next_alignment == internal_relocs) + { + /* When we delete bytes, we need to maintain all the alignments + indicated. In addition, we need to be careful about relaxing + jumps across alignment boundaries - these displacements + *grow* when we delete bytes. For now, don't shrink + displacements across an alignment boundary, just in case. + Note that this only affects relocations to the same + section. */ + prev_alignment = next_alignment; + next_alignment += 2; + while (next_alignment < irelend + && (ELF32_R_TYPE (next_alignment->r_info) != R_RX_RH_RELAX + || !(next_alignment->r_addend & RX_RELAXA_ELIGN))) + next_alignment ++; + if (next_alignment >= irelend || next_alignment->r_offset == 0) + next_alignment = NULL; + } + + /* When we hit alignment markers, see if we've shrunk enough + before them to reduce the gap without violating the alignment + requirements. */ + if (irel->r_addend & RX_RELAXA_ALIGN) + { + /* At this point, the next relocation *should* be the ELIGN + end marker. */ + Elf_Internal_Rela *erel = irel + 1; + unsigned int alignment, nbytes; + + if (ELF32_R_TYPE (erel->r_info) != R_RX_RH_RELAX) + continue; + if (!(erel->r_addend & RX_RELAXA_ELIGN)) + continue; + + alignment = 1 << (irel->r_addend & RX_RELAXA_ANUM); + + if (erel->r_offset - irel->r_offset < alignment) + continue; + + nbytes = erel->r_offset - irel->r_offset; + nbytes /= alignment; + nbytes *= alignment; + + elf32_rx_relax_delete_bytes (abfd, sec, erel->r_offset-nbytes, nbytes, next_alignment, + erel->r_offset == sec->size); + *again = TRUE; + + continue; + } + + if (irel->r_addend & RX_RELAXA_ELIGN) + continue; + + insn = contents + irel->r_offset; + + nrelocs = irel->r_addend & RX_RELAXA_RNUM; + + /* At this point, we have an insn that is a candidate for linker + relaxation. There are NRELOCS relocs following that may be + relaxed, although each reloc may be made of more than one + reloc entry (such as gp-rel symbols). */ + + /* Get the value of the symbol referred to by the reloc. Just + in case this is the last reloc in the list, use the RL's + addend to choose between this reloc (no addend) or the next + (yes addend, which means at least one following reloc). */ + + /* srel points to the "current" reloction for this insn - + actually the last reloc for a given operand, which is the one + we need to update. We check the relaxations in the same + order that the relocations happen, so we'll just push it + along as we go. */ + srel = irel; + + pc = sec->output_section->vma + sec->output_offset + + srel->r_offset; + +#define GET_RELOC \ + symval = OFFSET_FOR_RELOC (srel, &srel, &scale); \ + pcrel = symval - pc + srel->r_addend; \ + nrelocs --; + +#define SNIPNR(offset, nbytes) \ + elf32_rx_relax_delete_bytes (abfd, sec, (insn - contents) + offset, nbytes, next_alignment, 0); +#define SNIP(offset, nbytes, newtype) \ + SNIPNR (offset, nbytes); \ + srel->r_info = ELF32_R_INFO (ELF32_R_SYM (srel->r_info), newtype) + + /* The order of these bit tests must match the order that the + relocs appear in. Since we sorted those by offset, we can + predict them. */ + + /* Note that the numbers in, say, DSP6 are the bit offsets of + the code fields that describe the operand. Bits number 0 for + the MSB of insn[0]. */ + + /* DSP* codes: + 0 00 [reg] + 1 01 dsp:8[reg] + 2 10 dsp:16[reg] + 3 11 reg */ + if (irel->r_addend & RX_RELAXA_DSP6) + { + GET_RELOC; + + code = insn[0] & 3; + if (code == 2 && symval/scale <= 255) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + insn[0] &= 0xfc; + insn[0] |= 0x01; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (3, 1, newrel); + *again = TRUE; + } + } + + else if (code == 1 && symval == 0) + { + insn[0] &= 0xfc; + SNIP (2, 1, R_RX_NONE); + *again = TRUE; + } + + /* Special case DSP:5 format: MOV.bwl dsp:5[Rsrc],Rdst. */ + else if (code == 1 && symval/scale <= 31 + /* Decodable bits. */ + && (insn[0] & 0xcc) == 0xcc + /* width */ + && (insn[0] & 0x30) != 3 + /* register MSBs */ + && (insn[1] & 0x88) == 0x00) + { + int newrel = 0; + + insn[0] = 0x88 | (insn[0] & 0x30); + /* The register fields are in the right place already. */ + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + switch ((insn[0] & 0x30) >> 4) + { + case 0: + newrel = R_RX_RH_ABS5p5B; + break; + case 1: + newrel = R_RX_RH_ABS5p5W; + break; + case 2: + newrel = R_RX_RH_ABS5p5L; + break; + } + + move_reloc (irel, srel, -2); + SNIP (2, 1, newrel); + } + + /* Special case DSP:5 format: MOVU.bw dsp:5[Rsrc],Rdst. */ + else if (code == 1 && symval/scale <= 31 + /* Decodable bits. */ + && (insn[0] & 0xf8) == 0x58 + /* Register MSBs. */ + && (insn[1] & 0x88) == 0x00) + { + int newrel = 0; + + insn[0] = 0xb0 | ((insn[0] & 0x04) << 1); + /* The register fields are in the right place already. */ + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + switch ((insn[0] & 0x08) >> 3) + { + case 0: + newrel = R_RX_RH_ABS5p5B; + break; + case 1: + newrel = R_RX_RH_ABS5p5W; + break; + } + + move_reloc (irel, srel, -2); + SNIP (2, 1, newrel); + } + } + + /* A DSP4 operand always follows a DSP6 operand, even if there's + no relocation for it. We have to read the code out of the + opcode to calculate the offset of the operand. */ + if (irel->r_addend & RX_RELAXA_DSP4) + { + int code6, offset = 0; + + GET_RELOC; + + code6 = insn[0] & 0x03; + switch (code6) + { + case 0: offset = 2; break; + case 1: offset = 3; break; + case 2: offset = 4; break; + case 3: offset = 2; break; + } + + code = (insn[0] & 0x0c) >> 2; + + if (code == 2 && symval / scale <= 255) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + + insn[0] &= 0xf3; + insn[0] |= 0x04; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (offset+1, 1, newrel); + *again = TRUE; + } + } + + else if (code == 1 && symval == 0) + { + insn[0] &= 0xf3; + SNIP (offset, 1, R_RX_NONE); + *again = TRUE; + } + /* Special case DSP:5 format: MOV.bwl Rsrc,dsp:5[Rdst] */ + else if (code == 1 && symval/scale <= 31 + /* Decodable bits. */ + && (insn[0] & 0xc3) == 0xc3 + /* Width. */ + && (insn[0] & 0x30) != 3 + /* Register MSBs. */ + && (insn[1] & 0x88) == 0x00) + { + int newrel = 0; + + insn[0] = 0x80 | (insn[0] & 0x30); + /* The register fields are in the right place already. */ + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + switch ((insn[0] & 0x30) >> 4) + { + case 0: + newrel = R_RX_RH_ABS5p5B; + break; + case 1: + newrel = R_RX_RH_ABS5p5W; + break; + case 2: + newrel = R_RX_RH_ABS5p5L; + break; + } + + move_reloc (irel, srel, -2); + SNIP (2, 1, newrel); + } + } + + /* These always occur alone, but the offset depends on whether + it's a MEMEX opcode (0x06) or not. */ + if (irel->r_addend & RX_RELAXA_DSP14) + { + int offset; + GET_RELOC; + + if (insn[0] == 0x06) + offset = 3; + else + offset = 4; + + code = insn[1] & 3; + + if (code == 2 && symval / scale <= 255) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + + insn[1] &= 0xfc; + insn[1] |= 0x01; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (offset, 1, newrel); + *again = TRUE; + } + } + else if (code == 1 && symval == 0) + { + insn[1] &= 0xfc; + SNIP (offset, 1, R_RX_NONE); + *again = TRUE; + } + } + + /* IMM* codes: + 0 00 imm:32 + 1 01 simm:8 + 2 10 simm:16 + 3 11 simm:24. */ + + /* These always occur alone. */ + if (irel->r_addend & RX_RELAXA_IMM6) + { + long ssymval; + + GET_RELOC; + + /* These relocations sign-extend, so we must do signed compares. */ + ssymval = (long) symval; + + code = insn[0] & 0x03; + + if (code == 0 && ssymval <= 8388607 && ssymval >= -8388608) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + + insn[0] &= 0xfc; + insn[0] |= 0x03; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (2, 1, newrel); + *again = TRUE; + } + } + + else if (code == 3 && ssymval <= 32767 && ssymval >= -32768) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + + insn[0] &= 0xfc; + insn[0] |= 0x02; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (2, 1, newrel); + *again = TRUE; + } + } + + /* Special case UIMM8 format: CMP #uimm8,Rdst. */ + else if (code == 2 && ssymval <= 255 && ssymval >= 16 + /* Decodable bits. */ + && (insn[0] & 0xfc) == 0x74 + /* Decodable bits. */ + && ((insn[1] & 0xf0) == 0x00)) + { + int newrel; + + insn[0] = 0x75; + insn[1] = 0x50 | (insn[1] & 0x0f); + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + if (STACK_REL_P (ELF32_R_TYPE (srel->r_info))) + newrel = R_RX_ABS8U; + else + newrel = R_RX_DIR8U; + + SNIP (2, 1, newrel); + *again = TRUE; + } + + else if (code == 2 && ssymval <= 127 && ssymval >= -128) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + + insn[0] &= 0xfc; + insn[0] |= 0x01; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (2, 1, newrel); + *again = TRUE; + } + } + + /* Special case UIMM4 format: CMP, MUL, AND, OR. */ + else if (code == 1 && ssymval <= 15 && ssymval >= 0 + /* Decodable bits and immediate type. */ + && insn[0] == 0x75 + /* Decodable bits. */ + && (insn[1] & 0xc0) == 0x00) + { + static const int newop[4] = { 1, 3, 4, 5 }; + + insn[0] = 0x60 | newop[insn[1] >> 4]; + /* The register number doesn't move. */ + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + move_reloc (irel, srel, -1); + + SNIP (2, 1, R_RX_RH_UIMM4p8); + *again = TRUE; + } + + /* Special case UIMM4 format: ADD -> ADD/SUB. */ + else if (code == 1 && ssymval <= 15 && ssymval >= -15 + /* Decodable bits and immediate type. */ + && insn[0] == 0x71 + /* Same register for source and destination. */ + && ((insn[1] >> 4) == (insn[1] & 0x0f))) + { + int newrel; + + /* Note that we can't turn "add $0,Rs" into a NOP + because the flags need to be set right. */ + + if (ssymval < 0) + { + insn[0] = 0x60; /* Subtract. */ + newrel = R_RX_RH_UNEG4p8; + } + else + { + insn[0] = 0x62; /* Add. */ + newrel = R_RX_RH_UIMM4p8; + } + + /* The register number is in the right place. */ + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + move_reloc (irel, srel, -1); + + SNIP (2, 1, newrel); + *again = TRUE; + } + } + + /* These are either matched with a DSP6 (2-byte base) or an id24 + (3-byte base). */ + if (irel->r_addend & RX_RELAXA_IMM12) + { + int dspcode, offset = 0; + long ssymval; + + GET_RELOC; + + if ((insn[0] & 0xfc) == 0xfc) + dspcode = 1; /* Just something with one byte operand. */ + else + dspcode = insn[0] & 3; + switch (dspcode) + { + case 0: offset = 2; break; + case 1: offset = 3; break; + case 2: offset = 4; break; + case 3: offset = 2; break; + } + + /* These relocations sign-extend, so we must do signed compares. */ + ssymval = (long) symval; + + code = (insn[1] >> 2) & 3; + if (code == 0 && ssymval <= 8388607 && ssymval >= -8388608) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + + insn[1] &= 0xf3; + insn[1] |= 0x0c; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (offset, 1, newrel); + *again = TRUE; + } + } + + else if (code == 3 && ssymval <= 32767 && ssymval >= -32768) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + + insn[1] &= 0xf3; + insn[1] |= 0x08; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE (srel->r_info)) + { + SNIP (offset, 1, newrel); + *again = TRUE; + } + } + + /* Special case UIMM8 format: MOV #uimm8,Rdst. */ + else if (code == 2 && ssymval <= 255 && ssymval >= 16 + /* Decodable bits. */ + && insn[0] == 0xfb + /* Decodable bits. */ + && ((insn[1] & 0x03) == 0x02)) + { + int newrel; + + insn[0] = 0x75; + insn[1] = 0x40 | (insn[1] >> 4); + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + if (STACK_REL_P (ELF32_R_TYPE (srel->r_info))) + newrel = R_RX_ABS8U; + else + newrel = R_RX_DIR8U; + + SNIP (2, 1, newrel); + *again = TRUE; + } + + else if (code == 2 && ssymval <= 127 && ssymval >= -128) + { + unsigned int newrel = ELF32_R_TYPE(srel->r_info); + + insn[1] &= 0xf3; + insn[1] |= 0x04; + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + if (newrel != ELF32_R_TYPE(srel->r_info)) + { + SNIP (offset, 1, newrel); + *again = TRUE; + } + } + + /* Special case UIMM4 format: MOV #uimm4,Rdst. */ + else if (code == 1 && ssymval <= 15 && ssymval >= 0 + /* Decodable bits. */ + && insn[0] == 0xfb + /* Decodable bits. */ + && ((insn[1] & 0x03) == 0x02)) + { + insn[0] = 0x66; + insn[1] = insn[1] >> 4; + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + + move_reloc (irel, srel, -1); + + SNIP (2, 1, R_RX_RH_UIMM4p8); + *again = TRUE; + } + } + + if (irel->r_addend & RX_RELAXA_BRA) + { + unsigned int newrel = ELF32_R_TYPE (srel->r_info); + int max_pcrel3 = 4; + int alignment_glue = 0; + + GET_RELOC; + + /* Branches over alignment chunks are problematic, as + deleting bytes here makes the branch *further* away. We + can be agressive with branches within this alignment + block, but not branches outside it. */ + if ((prev_alignment == NULL + || symval < (bfd_vma)(sec_start + prev_alignment->r_offset)) + && (next_alignment == NULL + || symval > (bfd_vma)(sec_start + next_alignment->r_offset))) + alignment_glue = section_alignment_glue; + + if (ELF32_R_TYPE(srel[1].r_info) == R_RX_RH_RELAX + && srel[1].r_addend & RX_RELAXA_BRA + && srel[1].r_offset < irel->r_offset + pcrel) + max_pcrel3 ++; + + newrel = next_smaller_reloc (ELF32_R_TYPE (srel->r_info)); + + /* The values we compare PCREL with are not what you'd + expect; they're off by a little to compensate for (1) + where the reloc is relative to the insn, and (2) how much + the insn is going to change when we relax it. */ + + /* These we have to decode. */ + switch (insn[0]) + { + case 0x04: /* BRA pcdsp:24 */ + if (-32768 + alignment_glue <= pcrel + && pcrel <= 32765 - alignment_glue) + { + insn[0] = 0x38; + SNIP (3, 1, newrel); + *again = TRUE; + } + break; + + case 0x38: /* BRA pcdsp:16 */ + if (-128 + alignment_glue <= pcrel + && pcrel <= 127 - alignment_glue) + { + insn[0] = 0x2e; + SNIP (2, 1, newrel); + *again = TRUE; + } + break; + + case 0x2e: /* BRA pcdsp:8 */ + /* Note that there's a risk here of shortening things so + much that we no longer fit this reloc; it *should* + only happen when you branch across a branch, and that + branch also devolves into BRA.S. "Real" code should + be OK. */ + if (max_pcrel3 + alignment_glue <= pcrel + && pcrel <= 10 - alignment_glue + && allow_pcrel3) + { + insn[0] = 0x08; + SNIP (1, 1, newrel); + move_reloc (irel, srel, -1); + *again = TRUE; + } + break; + + case 0x05: /* BSR pcdsp:24 */ + if (-32768 + alignment_glue <= pcrel + && pcrel <= 32765 - alignment_glue) + { + insn[0] = 0x39; + SNIP (1, 1, newrel); + *again = TRUE; + } + break; + + case 0x3a: /* BEQ.W pcdsp:16 */ + case 0x3b: /* BNE.W pcdsp:16 */ + if (-128 + alignment_glue <= pcrel + && pcrel <= 127 - alignment_glue) + { + insn[0] = 0x20 | (insn[0] & 1); + SNIP (1, 1, newrel); + *again = TRUE; + } + break; + + case 0x20: /* BEQ.B pcdsp:8 */ + case 0x21: /* BNE.B pcdsp:8 */ + if (max_pcrel3 + alignment_glue <= pcrel + && pcrel - alignment_glue <= 10 + && allow_pcrel3) + { + insn[0] = 0x10 | ((insn[0] & 1) << 3); + SNIP (1, 1, newrel); + move_reloc (irel, srel, -1); + *again = TRUE; + } + break; + + case 0x16: /* synthetic BNE dsp24 */ + case 0x1e: /* synthetic BEQ dsp24 */ + if (-32767 + alignment_glue <= pcrel + && pcrel <= 32766 - alignment_glue + && insn[1] == 0x04) + { + if (insn[0] == 0x16) + insn[0] = 0x3b; + else + insn[0] = 0x3a; + /* We snip out the bytes at the end else the reloc + will get moved too, and too much. */ + SNIP (3, 2, newrel); + move_reloc (irel, srel, -1); + *again = TRUE; + } + break; + } + + /* Special case - synthetic conditional branches, pcrel24. + Note that EQ and NE have been handled above. */ + if ((insn[0] & 0xf0) == 0x20 + && insn[1] == 0x06 + && insn[2] == 0x04 + && srel->r_offset != irel->r_offset + 1 + && -32767 + alignment_glue <= pcrel + && pcrel <= 32766 - alignment_glue) + { + insn[1] = 0x05; + insn[2] = 0x38; + SNIP (5, 1, newrel); + *again = TRUE; + } + + /* Special case - synthetic conditional branches, pcrel16 */ + if ((insn[0] & 0xf0) == 0x20 + && insn[1] == 0x05 + && insn[2] == 0x38 + && srel->r_offset != irel->r_offset + 1 + && -127 + alignment_glue <= pcrel + && pcrel <= 126 - alignment_glue) + { + int cond = (insn[0] & 0x0f) ^ 0x01; + + insn[0] = 0x20 | cond; + /* By moving the reloc first, we avoid having + delete_bytes move it also. */ + move_reloc (irel, srel, -2); + SNIP (2, 3, newrel); + *again = TRUE; + } + } + + BFD_ASSERT (nrelocs == 0); + + /* Special case - check MOV.bwl #IMM, dsp[reg] and see if we can + use MOV.bwl #uimm:8, dsp:5[r7] format. This is tricky + because it may have one or two relocations. */ + if ((insn[0] & 0xfc) == 0xf8 + && (insn[1] & 0x80) == 0x00 + && (insn[0] & 0x03) != 0x03) + { + int dcode, icode, reg, ioff, dscale, ilen; + bfd_vma disp_val = 0; + long imm_val = 0; + Elf_Internal_Rela * disp_rel = 0; + Elf_Internal_Rela * imm_rel = 0; + + /* Reset this. */ + srel = irel; + + dcode = insn[0] & 0x03; + icode = (insn[1] >> 2) & 0x03; + reg = (insn[1] >> 4) & 0x0f; + + ioff = dcode == 1 ? 3 : dcode == 2 ? 4 : 2; + + /* Figure out what the dispacement is. */ + if (dcode == 1 || dcode == 2) + { + /* There's a displacement. See if there's a reloc for it. */ + if (srel[1].r_offset == irel->r_offset + 2) + { + GET_RELOC; + disp_val = symval; + disp_rel = srel; + } + else + { + if (dcode == 1) + disp_val = insn[2]; + else + { +#if RX_OPCODE_BIG_ENDIAN + disp_val = insn[2] * 256 + insn[3]; +#else + disp_val = insn[2] + insn[3] * 256; +#endif + } + switch (insn[1] & 3) + { + case 1: + disp_val *= 2; + scale = 2; + break; + case 2: + disp_val *= 4; + scale = 4; + break; + } + } + } + + dscale = scale; + + /* Figure out what the immediate is. */ + if (srel[1].r_offset == irel->r_offset + ioff) + { + GET_RELOC; + imm_val = (long) symval; + imm_rel = srel; + } + else + { + unsigned char * ip = insn + ioff; + + switch (icode) + { + case 1: + /* For byte writes, we don't sign extend. Makes the math easier later. */ + if (scale == 1) + imm_val = ip[0]; + else + imm_val = (char) ip[0]; + break; + case 2: +#if RX_OPCODE_BIG_ENDIAN + imm_val = ((char) ip[0] << 8) | ip[1]; +#else + imm_val = ((char) ip[1] << 8) | ip[0]; +#endif + break; + case 3: +#if RX_OPCODE_BIG_ENDIAN + imm_val = ((char) ip[0] << 16) | (ip[1] << 8) | ip[2]; +#else + imm_val = ((char) ip[2] << 16) | (ip[1] << 8) | ip[0]; +#endif + break; + case 0: +#if RX_OPCODE_BIG_ENDIAN + imm_val = (ip[0] << 24) | (ip[1] << 16) | (ip[2] << 8) | ip[3]; +#else + imm_val = (ip[3] << 24) | (ip[2] << 16) | (ip[1] << 8) | ip[0]; +#endif + break; + } + } + + ilen = 2; + + switch (dcode) + { + case 1: + ilen += 1; + break; + case 2: + ilen += 2; + break; + } + + switch (icode) + { + case 1: + ilen += 1; + break; + case 2: + ilen += 2; + break; + case 3: + ilen += 3; + break; + case 4: + ilen += 4; + break; + } + + /* The shortcut happens when the immediate is 0..255, + register r0 to r7, and displacement (scaled) 0..31. */ + + if (0 <= imm_val && imm_val <= 255 + && 0 <= reg && reg <= 7 + && disp_val / dscale <= 31) + { + insn[0] = 0x3c | (insn[1] & 0x03); + insn[1] = (((disp_val / dscale) << 3) & 0x80) | (reg << 4) | ((disp_val/dscale) & 0x0f); + insn[2] = imm_val; + + if (disp_rel) + { + int newrel = R_RX_NONE; + + switch (dscale) + { + case 1: + newrel = R_RX_RH_ABS5p8B; + break; + case 2: + newrel = R_RX_RH_ABS5p8W; + break; + case 4: + newrel = R_RX_RH_ABS5p8L; + break; + } + disp_rel->r_info = ELF32_R_INFO (ELF32_R_SYM (disp_rel->r_info), newrel); + move_reloc (irel, disp_rel, -1); + } + if (imm_rel) + { + imm_rel->r_info = ELF32_R_INFO (ELF32_R_SYM (imm_rel->r_info), R_RX_DIR8U); + move_reloc (disp_rel ? disp_rel : irel, + imm_rel, + irel->r_offset - imm_rel->r_offset + 2); + } + + SNIPNR (3, ilen - 3); + *again = TRUE; + + /* We can't relax this new opcode. */ + irel->r_addend = 0; + } + } + } + + /* We can't reliably relax branches to DIR3U_PCREL unless we know + whatever they're branching over won't shrink any more. If we're + basically done here, do one more pass just for branches - but + don't request a pass after that one! */ + if (!*again && !allow_pcrel3) + { + bfd_boolean ignored; + + elf32_rx_relax_section (abfd, sec, link_info, &ignored, TRUE); + } + + return TRUE; + + error_return: + if (free_relocs != NULL) + free (free_relocs); + + if (free_contents != NULL) + free (free_contents); + + if (shndx_buf != NULL) + { + shndx_hdr->contents = NULL; + free (shndx_buf); + } + + if (free_intsyms != NULL) + free (free_intsyms); + + return FALSE; +} + +static bfd_boolean +elf32_rx_relax_section_wrapper (bfd * abfd, + asection * sec, + struct bfd_link_info * link_info, + bfd_boolean * again) +{ + return elf32_rx_relax_section (abfd, sec, link_info, again, FALSE); +} + +/* Function to set the ELF flag bits. */ + +static bfd_boolean +rx_elf_set_private_flags (bfd * abfd, flagword flags) +{ + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = TRUE; + return TRUE; +} + +static bfd_boolean no_warn_mismatch = FALSE; + +void bfd_elf32_rx_set_target_flags (bfd_boolean); + +void +bfd_elf32_rx_set_target_flags (bfd_boolean user_no_warn_mismatch) +{ + no_warn_mismatch = user_no_warn_mismatch; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +rx_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) +{ + flagword old_flags; + flagword new_flags; + bfd_boolean error = FALSE; + + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + + if (!elf_flags_init (obfd)) + { + /* First call, no flags set. */ + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + } + else if (old_flags != new_flags) + { + flagword known_flags = E_FLAG_RX_64BIT_DOUBLES | E_FLAG_RX_DSP; + + if ((old_flags ^ new_flags) & known_flags) + { + /* Only complain if flag bits we care about do not match. + Other bits may be set, since older binaries did use some + deprecated flags. */ + if (no_warn_mismatch) + { + elf_elfheader (obfd)->e_flags = (new_flags | old_flags) & known_flags; + } + else + { + (*_bfd_error_handler) + ("ELF header flags mismatch: old_flags = 0x%.8lx, new_flags = 0x%.8lx, filename = %s", + old_flags, new_flags, bfd_get_filename (ibfd)); + error = TRUE; + } + } + else + elf_elfheader (obfd)->e_flags = new_flags & known_flags; + } + + if (error) + bfd_set_error (bfd_error_bad_value); + + return !error; +} + +static bfd_boolean +rx_elf_print_private_bfd_data (bfd * abfd, void * ptr) +{ + FILE * file = (FILE *) ptr; + flagword flags; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + flags = elf_elfheader (abfd)->e_flags; + fprintf (file, _("private flags = 0x%lx:"), (long) flags); + + if (flags & E_FLAG_RX_64BIT_DOUBLES) + fprintf (file, _(" [64-bit doubles]")); + if (flags & E_FLAG_RX_DSP) + fprintf (file, _(" [dsp]")); + + fputc ('\n', file); + return TRUE; +} + +/* Return the MACH for an e_flags value. */ + +static int +elf32_rx_machine (bfd * abfd) +{ + if ((elf_elfheader (abfd)->e_flags & EF_RX_CPU_MASK) == EF_RX_CPU_RX) + return bfd_mach_rx; + + return 0; +} + +static bfd_boolean +rx_elf_object_p (bfd * abfd) +{ + bfd_default_set_arch_mach (abfd, bfd_arch_rx, + elf32_rx_machine (abfd)); + return TRUE; +} + + +#ifdef DEBUG +void +dump_symtab (bfd * abfd, void * internal_syms, void * external_syms) +{ + size_t locsymcount; + Elf_Internal_Sym * isymbuf; + Elf_Internal_Sym * isymend; + Elf_Internal_Sym * isym; + Elf_Internal_Shdr * symtab_hdr; + bfd_boolean free_internal = FALSE, free_external = FALSE; + char * st_info_str; + char * st_info_stb_str; + char * st_other_str; + char * st_shndx_str; + + if (! internal_syms) + { + internal_syms = bfd_malloc (1000); + free_internal = 1; + } + if (! external_syms) + { + external_syms = bfd_malloc (1000); + free_external = 1; + } + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_size / get_elf_backend_data (abfd)->s->sizeof_sym; + if (free_internal) + isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, 0, + internal_syms, external_syms, NULL); + else + isymbuf = internal_syms; + isymend = isymbuf + locsymcount; + + for (isym = isymbuf ; isym < isymend ; isym++) + { + switch (ELF_ST_TYPE (isym->st_info)) + { + case STT_FUNC: st_info_str = "STT_FUNC"; + case STT_SECTION: st_info_str = "STT_SECTION"; + case STT_FILE: st_info_str = "STT_FILE"; + case STT_OBJECT: st_info_str = "STT_OBJECT"; + case STT_TLS: st_info_str = "STT_TLS"; + default: st_info_str = ""; + } + switch (ELF_ST_BIND (isym->st_info)) + { + case STB_LOCAL: st_info_stb_str = "STB_LOCAL"; + case STB_GLOBAL: st_info_stb_str = "STB_GLOBAL"; + default: st_info_stb_str = ""; + } + switch (ELF_ST_VISIBILITY (isym->st_other)) + { + case STV_DEFAULT: st_other_str = "STV_DEFAULT"; + case STV_INTERNAL: st_other_str = "STV_INTERNAL"; + case STV_PROTECTED: st_other_str = "STV_PROTECTED"; + default: st_other_str = ""; + } + switch (isym->st_shndx) + { + case SHN_ABS: st_shndx_str = "SHN_ABS"; + case SHN_COMMON: st_shndx_str = "SHN_COMMON"; + case SHN_UNDEF: st_shndx_str = "SHN_UNDEF"; + default: st_shndx_str = ""; + } + + printf ("isym = %p st_value = %lx st_size = %lx st_name = (%lu) %s " + "st_info = (%d) %s %s st_other = (%d) %s st_shndx = (%d) %s\n", + isym, + (unsigned long) isym->st_value, + (unsigned long) isym->st_size, + isym->st_name, + bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link, + isym->st_name), + isym->st_info, st_info_str, st_info_stb_str, + isym->st_other, st_other_str, + isym->st_shndx, st_shndx_str); + } + if (free_internal) + free (internal_syms); + if (free_external) + free (external_syms); +} + +char * +rx_get_reloc (long reloc) +{ + if (0 <= reloc && reloc < R_RX_max) + return rx_elf_howto_table[reloc].name; + return ""; +} +#endif /* DEBUG */ + + +/* We must take care to keep the on-disk copy of any code sections + that are fully linked swapped if the target is big endian, to match + the Renesas tools. */ + +/* The rule is: big endian object that are final-link executables, + have code sections stored with 32-bit words swapped relative to + what you'd get by default. */ + +static bfd_boolean +rx_get_section_contents (bfd * abfd, + sec_ptr section, + void * location, + file_ptr offset, + bfd_size_type count) +{ + int exec = (abfd->flags & EXEC_P) ? 1 : 0; + int s_code = (section->flags & SEC_CODE) ? 1 : 0; + bfd_boolean rv; + +#ifdef DJDEBUG + fprintf (stderr, "dj: get %ld %ld from %s %s e%d sc%d %08lx:%08lx\n", + (long) offset, (long) count, section->name, + bfd_big_endian(abfd) ? "be" : "le", + exec, s_code, (long unsigned) section->filepos, + (long unsigned) offset); +#endif + + if (exec && s_code && bfd_big_endian (abfd)) + { + char * cloc = (char *) location; + bfd_size_type cnt, end_cnt; + + rv = TRUE; + + /* Fetch and swap unaligned bytes at the beginning. */ + if (offset % 4) + { + char buf[4]; + + rv = _bfd_generic_get_section_contents (abfd, section, buf, + (offset & -4), 4); + if (!rv) + return FALSE; + + bfd_putb32 (bfd_getl32 (buf), buf); + + cnt = 4 - (offset % 4); + if (cnt > count) + cnt = count; + + memcpy (location, buf + (offset % 4), cnt); + + count -= cnt; + offset += cnt; + cloc += count; + } + + end_cnt = count % 4; + + /* Fetch and swap the middle bytes. */ + if (count >= 4) + { + rv = _bfd_generic_get_section_contents (abfd, section, cloc, offset, + count - end_cnt); + if (!rv) + return FALSE; + + for (cnt = count; cnt >= 4; cnt -= 4, cloc += 4) + bfd_putb32 (bfd_getl32 (cloc), cloc); + } + + /* Fetch and swap the end bytes. */ + if (end_cnt > 0) + { + char buf[4]; + + /* Fetch the end bytes. */ + rv = _bfd_generic_get_section_contents (abfd, section, buf, + offset + count - end_cnt, 4); + if (!rv) + return FALSE; + + bfd_putb32 (bfd_getl32 (buf), buf); + memcpy (cloc, buf, end_cnt); + } + } + else + rv = _bfd_generic_get_section_contents (abfd, section, location, offset, count); + + return rv; +} + +#ifdef DJDEBUG +static bfd_boolean +rx2_set_section_contents (bfd * abfd, + sec_ptr section, + const void * location, + file_ptr offset, + bfd_size_type count) +{ + bfd_size_type i; + + fprintf (stderr, " set sec %s %08x loc %p offset %#x count %#x\n", + section->name, (unsigned) section->vma, location, (int) offset, (int) count); + for (i = 0; i < count; i++) + { + if (i % 16 == 0 && i > 0) + fprintf (stderr, "\n"); + + if (i % 16 && i % 4 == 0) + fprintf (stderr, " "); + + if (i % 16 == 0) + fprintf (stderr, " %08x:", (int) (section->vma + offset + i)); + + fprintf (stderr, " %02x", ((unsigned char *) location)[i]); + } + fprintf (stderr, "\n"); + + return _bfd_elf_set_section_contents (abfd, section, location, offset, count); +} +#define _bfd_elf_set_section_contents rx2_set_section_contents +#endif + +static bfd_boolean +rx_set_section_contents (bfd * abfd, + sec_ptr section, + const void * location, + file_ptr offset, + bfd_size_type count) +{ + bfd_boolean exec = (abfd->flags & EXEC_P) ? TRUE : FALSE; + bfd_boolean s_code = (section->flags & SEC_CODE) ? TRUE : FALSE; + bfd_boolean rv; + char * swapped_data = NULL; + bfd_size_type i; + bfd_vma caddr = section->vma + offset; + file_ptr faddr = 0; + bfd_size_type scount; + +#ifdef DJDEBUG + bfd_size_type i; + + fprintf (stderr, "\ndj: set %ld %ld to %s %s e%d sc%d\n", + (long) offset, (long) count, section->name, + bfd_big_endian (abfd) ? "be" : "le", + exec, s_code); + + for (i = 0; i < count; i++) + { + int a = section->vma + offset + i; + + if (a % 16 == 0 && a > 0) + fprintf (stderr, "\n"); + + if (a % 16 && a % 4 == 0) + fprintf (stderr, " "); + + if (a % 16 == 0 || i == 0) + fprintf (stderr, " %08x:", (int) (section->vma + offset + i)); + + fprintf (stderr, " %02x", ((unsigned char *) location)[i]); + } + + fprintf (stderr, "\n"); +#endif + + if (! exec || ! s_code || ! bfd_big_endian (abfd)) + return _bfd_elf_set_section_contents (abfd, section, location, offset, count); + + while (count > 0 && caddr > 0 && caddr % 4) + { + switch (caddr % 4) + { + case 0: faddr = offset + 3; break; + case 1: faddr = offset + 1; break; + case 2: faddr = offset - 1; break; + case 3: faddr = offset - 3; break; + } + + rv = _bfd_elf_set_section_contents (abfd, section, location, faddr, 1); + if (! rv) + return rv; + + location ++; + offset ++; + count --; + caddr ++; + } + + scount = (int)(count / 4) * 4; + if (scount > 0) + { + char * cloc = (char *) location; + + swapped_data = (char *) bfd_alloc (abfd, count); + + for (i = 0; i < count; i += 4) + { + bfd_vma v = bfd_getl32 (cloc + i); + bfd_putb32 (v, swapped_data + i); + } + + rv = _bfd_elf_set_section_contents (abfd, section, swapped_data, offset, scount); + + if (!rv) + return rv; + } + + count -= scount; + location += scount; + offset += scount; + + if (count > 0) + { + caddr = section->vma + offset; + while (count > 0) + { + switch (caddr % 4) + { + case 0: faddr = offset + 3; break; + case 1: faddr = offset + 1; break; + case 2: faddr = offset - 1; break; + case 3: faddr = offset - 3; break; + } + rv = _bfd_elf_set_section_contents (abfd, section, location, faddr, 1); + if (! rv) + return rv; + + location ++; + offset ++; + count --; + caddr ++; + } + } + + return TRUE; +} + +static bfd_boolean +rx_final_link (bfd * abfd, struct bfd_link_info * info) +{ + asection * o; + + for (o = abfd->sections; o != NULL; o = o->next) + { +#ifdef DJDEBUG + fprintf (stderr, "sec %s fl %x vma %lx lma %lx size %lx raw %lx\n", + o->name, o->flags, o->vma, o->lma, o->size, o->rawsize); +#endif + if (o->flags & SEC_CODE + && bfd_big_endian (abfd) + && (o->size % 4 || o->rawsize % 4)) + { +#ifdef DJDEBUG + fprintf (stderr, "adjusting...\n"); +#endif + o->size += 4 - (o->size % 4); + o->rawsize += 4 - (o->rawsize % 4); + } + } + + return bfd_elf_final_link (abfd, info); +} + +static bfd_boolean +elf32_rx_modify_program_headers (bfd * abfd ATTRIBUTE_UNUSED, + struct bfd_link_info * info ATTRIBUTE_UNUSED) +{ + const struct elf_backend_data * bed; + struct elf_obj_tdata * tdata; + Elf_Internal_Phdr * phdr; + unsigned int count; + unsigned int i; + + bed = get_elf_backend_data (abfd); + tdata = elf_tdata (abfd); + phdr = tdata->phdr; + count = tdata->program_header_size / bed->s->sizeof_phdr; + + for (i = count; i-- != 0; ) + if (phdr[i].p_type == PT_LOAD) + { + /* The Renesas tools expect p_paddr to be zero. However, + there is no other way to store the writable data in ROM for + startup initialization. So, we let the linker *think* + we're using paddr and vaddr the "usual" way, but at the + last minute we move the paddr into the vaddr (which is what + the simulator uses) and zero out paddr. Note that this + does not affect the section headers, just the program + headers. We hope. */ + phdr[i].p_vaddr = phdr[i].p_paddr; + /* If we zero out p_paddr, then the LMA in the section table + becomes wrong. */ + /*phdr[i].p_paddr = 0;*/ + } + + return TRUE; +} + +#define ELF_ARCH bfd_arch_rx +#define ELF_MACHINE_CODE EM_RX +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_BIG_SYM bfd_elf32_rx_be_vec +#define TARGET_BIG_NAME "elf32-rx-be" + +#define TARGET_LITTLE_SYM bfd_elf32_rx_le_vec +#define TARGET_LITTLE_NAME "elf32-rx-le" + +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto rx_info_to_howto_rela +#define elf_backend_object_p rx_elf_object_p +#define elf_backend_relocate_section rx_elf_relocate_section +#define elf_symbol_leading_char ('_') +#define elf_backend_can_gc_sections 1 +#define elf_backend_modify_program_headers elf32_rx_modify_program_headers + +#define bfd_elf32_bfd_reloc_type_lookup rx_reloc_type_lookup +#define bfd_elf32_bfd_reloc_name_lookup rx_reloc_name_lookup +#define bfd_elf32_bfd_set_private_flags rx_elf_set_private_flags +#define bfd_elf32_bfd_merge_private_bfd_data rx_elf_merge_private_bfd_data +#define bfd_elf32_bfd_print_private_bfd_data rx_elf_print_private_bfd_data +#define bfd_elf32_get_section_contents rx_get_section_contents +#define bfd_elf32_set_section_contents rx_set_section_contents +#define bfd_elf32_bfd_final_link rx_final_link +#define bfd_elf32_bfd_relax_section elf32_rx_relax_section_wrapper + +#include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 2450b2d80b3..7fe65789bd7 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1646,6 +1646,30 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_AVR_LDI", "BFD_RELOC_AVR_6", "BFD_RELOC_AVR_6_ADIW", + "BFD_RELOC_RX_NEG8", + "BFD_RELOC_RX_NEG16", + "BFD_RELOC_RX_NEG24", + "BFD_RELOC_RX_NEG32", + "BFD_RELOC_RX_16_OP", + "BFD_RELOC_RX_24_OP", + "BFD_RELOC_RX_32_OP", + "BFD_RELOC_RX_8U", + "BFD_RELOC_RX_16U", + "BFD_RELOC_RX_24U", + "BFD_RELOC_RX_DIR3U_PCREL", + "BFD_RELOC_RX_DIFF", + "BFD_RELOC_RX_GPRELB", + "BFD_RELOC_RX_GPRELW", + "BFD_RELOC_RX_GPRELL", + "BFD_RELOC_RX_SYM", + "BFD_RELOC_RX_OP_SUBTRACT", + "BFD_RELOC_RX_ABS8", + "BFD_RELOC_RX_ABS16", + "BFD_RELOC_RX_ABS32", + "BFD_RELOC_RX_ABS16U", + "BFD_RELOC_RX_ABS16UW", + "BFD_RELOC_RX_ABS16UL", + "BFD_RELOC_RX_RELAX", "BFD_RELOC_390_12", "BFD_RELOC_390_GOT12", "BFD_RELOC_390_PLT32", diff --git a/bfd/reloc.c b/bfd/reloc.c index 3be29fea333..0ea7a85c192 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -4052,6 +4052,57 @@ ENUMDOC instructions ENUM + BFD_RELOC_RX_NEG8 +ENUMX + BFD_RELOC_RX_NEG16 +ENUMX + BFD_RELOC_RX_NEG24 +ENUMX + BFD_RELOC_RX_NEG32 +ENUMX + BFD_RELOC_RX_16_OP +ENUMX + BFD_RELOC_RX_24_OP +ENUMX + BFD_RELOC_RX_32_OP +ENUMX + BFD_RELOC_RX_8U +ENUMX + BFD_RELOC_RX_16U +ENUMX + BFD_RELOC_RX_24U +ENUMX + BFD_RELOC_RX_DIR3U_PCREL +ENUMX + BFD_RELOC_RX_DIFF +ENUMX + BFD_RELOC_RX_GPRELB +ENUMX + BFD_RELOC_RX_GPRELW +ENUMX + BFD_RELOC_RX_GPRELL +ENUMX + BFD_RELOC_RX_SYM +ENUMX + BFD_RELOC_RX_OP_SUBTRACT +ENUMX + BFD_RELOC_RX_ABS8 +ENUMX + BFD_RELOC_RX_ABS16 +ENUMX + BFD_RELOC_RX_ABS32 +ENUMX + BFD_RELOC_RX_ABS16U +ENUMX + BFD_RELOC_RX_ABS16UW +ENUMX + BFD_RELOC_RX_ABS16UL +ENUMX + BFD_RELOC_RX_RELAX +ENUMDOC + Renesas RX Relocations. + +ENUM BFD_RELOC_390_12 ENUMDOC Direct 12 bit. diff --git a/bfd/targets.c b/bfd/targets.c index a33790bcbe6..347c6cd76b3 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -641,6 +641,8 @@ extern const bfd_target bfd_elf32_pjl_vec; extern const bfd_target bfd_elf32_powerpc_vec; extern const bfd_target bfd_elf32_powerpcle_vec; extern const bfd_target bfd_elf32_powerpc_vxworks_vec; +extern const bfd_target bfd_elf32_rx_le_vec; +extern const bfd_target bfd_elf32_rx_be_vec; extern const bfd_target bfd_elf32_s390_vec; extern const bfd_target bfd_elf32_bigscore_vec; extern const bfd_target bfd_elf32_littlescore_vec; @@ -978,6 +980,8 @@ static const bfd_target * const _bfd_target_vector[] = &bfd_elf32_powerpc_vec, &bfd_elf32_powerpc_vxworks_vec, &bfd_elf32_powerpcle_vec, + &bfd_elf32_rx_be_vec, + &bfd_elf32_rx_le_vec, &bfd_elf32_s390_vec, #ifdef BFD64 &bfd_elf32_bigscore_vec, diff --git a/binutils/ChangeLog b/binutils/ChangeLog index a6275e1762a..6a4958d73a3 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * readelf.c: Add support for RX target. + * MAINTAINERS: Add DJ and NickC as maintainers for RX. + 2009-09-28 Alan Modra <amodra@bigpond.net.au> * configure.in: Don't invoke configure.tgt on $enable_targets. diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS index 6d316323bfb..97fb5660a8a 100644 --- a/binutils/MAINTAINERS +++ b/binutils/MAINTAINERS @@ -104,6 +104,8 @@ responsibility among the other maintainers. PPC Geoff Keating <geoffk@geoffk.org> PPC Alan Modra <amodra@bigpond.net.au> PPC vector ext Aldy Hernandez <aldyh@redhat.com> + RX DJ Delorie <dj@redhat.com> + RX Nick Clifton <nickc@redhat.com> s390, s390x Martin Schwidefsky <schwidefsky@de.ibm.com> SCORE Mei Ligang <ligang@sunnorth.com.cn> SH Alexandre Oliva <aoliva@redhat.com> diff --git a/binutils/readelf.c b/binutils/readelf.c index a57b5ad63bc..15f4ac04c8b 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -130,6 +130,7 @@ #include "elf/pj.h" #include "elf/ppc.h" #include "elf/ppc64.h" +#include "elf/rx.h" #include "elf/s390.h" #include "elf/score.h" #include "elf/sh.h" @@ -604,6 +605,7 @@ guess_is_rela (unsigned int e_machine) case EM_NIOS32: case EM_PPC64: case EM_PPC: + case EM_RX: case EM_S390: case EM_S390_OLD: case EM_SH: @@ -1215,6 +1217,10 @@ dump_relocations (FILE * file, case EM_MICROBLAZE_OLD: rtype = elf_microblaze_reloc_type (type); break; + + case EM_RX: + rtype = elf_rx_reloc_type (type); + break; } if (rtype == NULL) @@ -1887,6 +1893,7 @@ get_machine_name (unsigned e_machine) case EM_CR16_OLD: return "National Semiconductor's CR16"; case EM_MICROBLAZE: return "Xilinx MicroBlaze"; case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze"; + case EM_RX: return "Renesas RX"; default: snprintf (buff, sizeof (buff), _("<unknown>: 0x%x"), e_machine); return buff; @@ -2431,6 +2438,12 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) if ((e_flags & EF_VAX_GFLOAT)) strcat (buf, ", G-Float"); break; + + case EM_RX: + if (e_flags & E_FLAG_RX_64BIT_DOUBLES) + strcat (buf, ", 64-bit doubles"); + if (e_flags & E_FLAG_RX_DSP) + strcat (buf, ", dsp"); } } @@ -8054,6 +8067,8 @@ is_32bit_abs_reloc (unsigned int reloc_type) return reloc_type == 1; /* R_PPC64_ADDR32. */ case EM_PPC: return reloc_type == 1; /* R_PPC_ADDR32. */ + case EM_RX: + return reloc_type == 1; /* R_RX_DIR32. */ case EM_S370: return reloc_type == 1; /* R_I370_ADDR31. */ case EM_S390_OLD: diff --git a/gas/ChangeLog b/gas/ChangeLog index 4183f5655a8..bf5e63a9509 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,23 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * Makefile.am: Add RX target. + * configure.in: Likewise. + * configure.tgt: Likewise. + * read.c (do_repeat_with_expander): New function. + * read.h: Provide a prototype for do_repeat_with_expander. + * doc/Makefile.am: Add RX target documentation. + * doc/all.texi: Likewise. + * doc/as.texinfo: Likewise. + * Makefile.in: Regenerate. + * NEWS: Mention support for RX architecture. + * configure: Regenerate. + * doc/Makefile.in: Regenerate. + * config/rx-defs.h: New file. + * config/rx-parse.y: New file. + * config/tc-rx.h: New file. + * config/tc-rx.c: New file. + * doc/c-rx.texi: New file. + 2009-09-25 Martin Thuresson <martint@google.com> Update soruces to make alpha, arc and arm targets compile cleanly diff --git a/gas/Makefile.am b/gas/Makefile.am index d3e88366781..87fbe3c51e1 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -81,6 +81,7 @@ CPU_TYPES = \ pdp11 \ pj \ ppc \ + rx \ s390 \ score \ sh \ @@ -284,6 +285,7 @@ TARGET_CPU_CFILES = \ config/tc-pdp11.c \ config/tc-pj.c \ config/tc-ppc.c \ + config/tc-rx.c \ config/tc-s390.c \ config/tc-score.c \ config/tc-sh.c \ @@ -346,6 +348,7 @@ TARGET_CPU_HFILES = \ config/tc-pdp11.h \ config/tc-pj.h \ config/tc-ppc.h \ + config/tc-rx.h \ config/tc-s390.h \ config/tc-score.h \ config/tc-sh.h \ @@ -499,7 +502,8 @@ noinst_SCRIPTS = $(GDBINIT) EXTRA_SCRIPTS = .gdbinit EXTRA_DIST = m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c \ - bfin-parse.c bfin-parse.h bfin-lex.c + bfin-parse.c bfin-parse.h bfin-lex.c \ + rx-parse.c rx-parse.h diststuff: $(EXTRA_DIST) info @@ -628,6 +632,15 @@ endif $(COMPILE) -c `test -f bfin-lex.c || echo $(srcdir)/`bfin-lex.c $(NO_WERROR) endif +rx-parse.c: $(srcdir)/config/rx-parse.y + $(SHELL) $(YLWRAP) $(srcdir)/config/rx-parse.y y.tab.c rx-parse.c y.tab.h rx-parse.h -- $(YACCCOMPILE) -d ; +rx-parse.h: rx-parse.c +rx-parse.o: rx-parse.c rx-parse.h $(srcdir)/config/rx-defs.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/rx.h $(BFDDIR)/libbfd.h + +rx-defs.h: ; @true +$(srcdir)/config/rx-defs.h: ; @true + # The instruction table specification lexical analyzer and parser. # Disable -Werror, if it has been enabled, since old versions of bison/ diff --git a/gas/Makefile.in b/gas/Makefile.in index e31368609ad..5aa485e0b1a 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -347,6 +347,7 @@ CPU_TYPES = \ pdp11 \ pj \ ppc \ + rx \ s390 \ score \ sh \ @@ -548,6 +549,7 @@ TARGET_CPU_CFILES = \ config/tc-pdp11.c \ config/tc-pj.c \ config/tc-ppc.c \ + config/tc-rx.c \ config/tc-s390.c \ config/tc-score.c \ config/tc-sh.c \ @@ -610,6 +612,7 @@ TARGET_CPU_HFILES = \ config/tc-pdp11.h \ config/tc-pj.h \ config/tc-ppc.h \ + config/tc-rx.h \ config/tc-s390.h \ config/tc-score.h \ config/tc-sh.h \ @@ -755,7 +758,8 @@ POTFILES = $(MULTI_CFILES) $(CONFIG_ATOF_CFILES) \ noinst_SCRIPTS = $(GDBINIT) EXTRA_SCRIPTS = .gdbinit EXTRA_DIST = m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c \ - bfin-parse.c bfin-parse.h bfin-lex.c + bfin-parse.c bfin-parse.h bfin-lex.c \ + rx-parse.c rx-parse.h DISTCLEANFILES = targ-cpu.h obj-format.h targ-env.h itbl-cpu.h cgen-desc.h @@ -989,6 +993,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-score.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-sh.Po@am__quote@ @@ -1646,6 +1651,20 @@ tc-ppc.obj: config/tc-ppc.c @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi` +tc-rx.o: config/tc-rx.c +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rx.o -MD -MP -MF $(DEPDIR)/tc-rx.Tpo -c -o tc-rx.o `test -f 'config/tc-rx.c' || echo '$(srcdir)/'`config/tc-rx.c +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-rx.Tpo $(DEPDIR)/tc-rx.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-rx.c' object='tc-rx.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-rx.o `test -f 'config/tc-rx.c' || echo '$(srcdir)/'`config/tc-rx.c + +tc-rx.obj: config/tc-rx.c +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rx.obj -MD -MP -MF $(DEPDIR)/tc-rx.Tpo -c -o tc-rx.obj `if test -f 'config/tc-rx.c'; then $(CYGPATH_W) 'config/tc-rx.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-rx.c'; fi` +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-rx.Tpo $(DEPDIR)/tc-rx.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-rx.c' object='tc-rx.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-rx.obj `if test -f 'config/tc-rx.c'; then $(CYGPATH_W) 'config/tc-rx.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-rx.c'; fi` + tc-s390.o: config/tc-s390.c @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-s390.o -MD -MP -MF $(DEPDIR)/tc-s390.Tpo -c -o tc-s390.o `test -f 'config/tc-s390.c' || echo '$(srcdir)/'`config/tc-s390.c @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-s390.Tpo $(DEPDIR)/tc-s390.Po @@ -2534,6 +2553,15 @@ bfin-lex.o: bfin-lex.c bfin-parse.h $(srcdir)/config/bfin-defs.h @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(COMPILE) -c `test -f bfin-lex.c || echo $(srcdir)/`bfin-lex.c $(NO_WERROR) +rx-parse.c: $(srcdir)/config/rx-parse.y + $(SHELL) $(YLWRAP) $(srcdir)/config/rx-parse.y y.tab.c rx-parse.c y.tab.h rx-parse.h -- $(YACCCOMPILE) -d ; +rx-parse.h: rx-parse.c +rx-parse.o: rx-parse.c rx-parse.h $(srcdir)/config/rx-defs.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/rx.h $(BFDDIR)/libbfd.h + +rx-defs.h: ; @true +$(srcdir)/config/rx-defs.h: ; @true + # The instruction table specification lexical analyzer and parser. # Disable -Werror, if it has been enabled, since old versions of bison/ @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the Renesas RX processor. + Changes in 2.20: * GNU/Linux targets now supports "gnu_unique_object" as a value in the .type diff --git a/gas/config/rx-defs.h b/gas/config/rx-defs.h new file mode 100644 index 00000000000..c4648d2190a --- /dev/null +++ b/gas/config/rx-defs.h @@ -0,0 +1,57 @@ +/* rx-defs.h Renesas RX internal definitions + Copyright 2008, 2009 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef RX_DEFS_H +#define RX_DEFS_H + +/* Third operand to rx_op. */ +#define RXREL_SIGNED 0 +#define RXREL_UNSIGNED 1 +#define RXREL_NEGATIVE 2 +#define RXREL_PCREL 3 +#define RXREL_NEGATIVE_BORROW 4 + +#define RX_RELAX_NONE 0 +#define RX_RELAX_BRANCH 1 +#define RX_RELAX_IMM 2 +#define RX_RELAX_DISP 3 + +extern int rx_error (char *); +extern void rx_lex_init (char *, char *); +extern void rx_base1 (int); +extern void rx_base2 (int, int); +extern void rx_base3 (int, int, int); +extern void rx_base4 (int, int, int, int); +extern void rx_field (int, int, int); +extern void rx_op (expressionS, int, int); +extern void rx_disp3 (expressionS, int); +extern void rx_field5s (expressionS); +extern void rx_field5s2 (expressionS); +extern void rx_relax (int, int); +extern void rx_linkrelax_dsp (int); +extern void rx_linkrelax_imm (int); +extern void rx_linkrelax_branch (void); +extern int rx_parse (void); +extern int rx_wrap (void); + +extern char * rx_lex_start; +extern char * rx_lex_end; +#endif diff --git a/gas/config/rx-parse.y b/gas/config/rx-parse.y new file mode 100644 index 00000000000..0bcafc81afe --- /dev/null +++ b/gas/config/rx-parse.y @@ -0,0 +1,1555 @@ +/* rx-parse.y Renesas RX parser + Copyright 2008, 2009 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ +%{ + +#include "as.h" +#include "safe-ctype.h" +#include "rx-defs.h" + +static int rx_lex (void); + +#define COND_EQ 0 +#define COND_NE 1 + +#define MEMEX 0x06 + +#define BSIZE 0 +#define WSIZE 1 +#define LSIZE 2 + +/* .sb .sw .l .uw */ +static int sizemap[] = { BSIZE, WSIZE, LSIZE, WSIZE }; + +/* Ok, here are the rules for using these macros... + + B*() is used to specify the base opcode bytes. Fields to be filled + in later, leave zero. Call this first. + + F() and FE() are used to fill in fields within the base opcode bytes. You MUST + call B*() before any F() or FE(). + + [UN]*O*(), PC*() appends operands to the end of the opcode. You + must call P() and B*() before any of these, so that the fixups + have the right byte location. + O = signed, UO = unsigned, NO = negated, PC = pcrel + + IMM() adds an immediate and fills in the field for it. + NIMM() same, but negates the immediate. + NBIMM() same, but negates the immediate, for sbb. + DSP() adds a displacement, and fills in the field for it. + + Note that order is significant for the O, IMM, and DSP macros, as + they append their data to the operand buffer in the order that you + call them. + + Use "disp" for displacements whenever possible; this handles the + "0" case properly. */ + +#define B1(b1) rx_base1 (b1) +#define B2(b1, b2) rx_base2 (b1, b2) +#define B3(b1, b2, b3) rx_base3 (b1, b2, b3) +#define B4(b1, b2, b3, b4) rx_base4 (b1, b2, b3, b4) + +/* POS is bits from the MSB of the first byte to the LSB of the last byte. */ +#define F(val,pos,sz) rx_field (val, pos, sz) +#define FE(exp,pos,sz) rx_field (exp_val (exp), pos, sz); + +#define O1(v) rx_op (v, 1, RXREL_SIGNED) +#define O2(v) rx_op (v, 2, RXREL_SIGNED) +#define O3(v) rx_op (v, 3, RXREL_SIGNED) +#define O4(v) rx_op (v, 4, RXREL_SIGNED) + +#define UO1(v) rx_op (v, 1, RXREL_UNSIGNED) +#define UO2(v) rx_op (v, 2, RXREL_UNSIGNED) +#define UO3(v) rx_op (v, 3, RXREL_UNSIGNED) +#define UO4(v) rx_op (v, 4, RXREL_UNSIGNED) + +#define NO1(v) rx_op (v, 1, RXREL_NEGATIVE) +#define NO2(v) rx_op (v, 2, RXREL_NEGATIVE) +#define NO3(v) rx_op (v, 3, RXREL_NEGATIVE) +#define NO4(v) rx_op (v, 4, RXREL_NEGATIVE) + +#define PC1(v) rx_op (v, 1, RXREL_PCREL) +#define PC2(v) rx_op (v, 2, RXREL_PCREL) +#define PC3(v) rx_op (v, 3, RXREL_PCREL) + +#define IMM(v,pos) F (immediate (v, RXREL_SIGNED, pos), pos, 2); \ + if (v.X_op != O_constant && v.X_op != O_big) rx_linkrelax_imm (pos) +#define NIMM(v,pos) F (immediate (v, RXREL_NEGATIVE, pos), pos, 2) +#define NBIMM(v,pos) F (immediate (v, RXREL_NEGATIVE_BORROW, pos), pos, 2) +#define DSP(v,pos,msz) if (!v.X_md) rx_relax (RX_RELAX_DISP, pos); \ + else rx_linkrelax_dsp (pos); \ + F (displacement (v, msz), pos, 2) + +#define id24(a,b2,b3) B3 (0xfb+a, b2, b3) + +static int rx_intop (expressionS, int); +static int rx_uintop (expressionS, int); +static int rx_disp3op (expressionS); +static int rx_disp5op (expressionS *, int); +static int rx_disp5op0 (expressionS *, int); +static int exp_val (expressionS exp); +static expressionS zero_expr (void); +static int immediate (expressionS, int, int); +static int displacement (expressionS, int); +static void rtsd_immediate (expressionS); + +static int need_flag = 0; +static int rx_in_brackets = 0; +static int rx_last_token = 0; +static char * rx_init_start; +static char * rx_last_exp_start = 0; +static int sub_op; +static int sub_op2; + +#define YYDEBUG 1 +#define YYERROR_VERBOSE 1 + +%} + +%name-prefix="rx_" + +%union { + int regno; + expressionS exp; +} + +%type <regno> REG FLAG CREG BCND BMCND SCCND +%type <regno> flag bwl bw memex +%type <exp> EXPR disp + +%token REG FLAG CREG + +%token EXPR UNKNOWN_OPCODE IS_OPCODE + +%token DOT_S DOT_B DOT_W DOT_L DOT_A DOT_UB DOT_UW + +%token ABS ADC ADD AND_ +%token BCLR BCND BMCND BNOT BRA BRK BSET BSR BTST +%token CLRPSW CMP +%token DBT DIV DIVU +%token EDIV EDIVU EMUL EMULU +%token FADD FCMP FDIV FMUL FREIT FSUB FTOI +%token INT ITOF +%token JMP JSR +%token MACHI MACLO MAX MIN MOV MOVU MUL MULHI MULLO MULU MVFACHI MVFACMI MVFACLO +%token MVFC MVTACHI MVTACLO MVTC MVTIPL +%token NEG NOP NOT +%token OR +%token POP POPC POPM PUSH PUSHA PUSHC PUSHM +%token RACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND RTE RTFI RTS RTSD +%token SAT SATR SBB SCCND SCMPU SETPSW SHAR SHLL SHLR SMOVB SMOVF +%token SMOVU SSTR STNZ STOP STZ SUB SUNTIL SWHILE +%token TST +%token WAIT +%token XCHG XOR + +%% +/* ====================================================================== */ + +statement : + + UNKNOWN_OPCODE + { as_bad (_("Unknown opcode: %s"), rx_init_start); } + +/* ---------------------------------------------------------------------- */ + + | BRK + { B1 (0x00); } + + | DBT + { B1 (0x01); } + + | RTS + { B1 (0x02); } + + | NOP + { B1 (0x03); } + +/* ---------------------------------------------------------------------- */ + + | BRA EXPR + { if (rx_disp3op ($2)) + { B1 (0x08); rx_disp3 ($2, 5); } + else if (rx_intop ($2, 8)) + { B1 (0x2e); PC1 ($2); } + else if (rx_intop ($2, 16)) + { B1 (0x38); PC2 ($2); } + else if (rx_intop ($2, 24)) + { B1 (0x04); PC3 ($2); } + else + { rx_relax (RX_RELAX_BRANCH, 0); + rx_linkrelax_branch (); + /* We'll convert this to a longer one later if needed. */ + B1 (0x08); rx_disp3 ($2, 5); } } + + | BRA DOT_A EXPR + { B1 (0x04); PC3 ($3); } + + | BRA DOT_S EXPR + { B1 (0x08); rx_disp3 ($3, 5); } + +/* ---------------------------------------------------------------------- */ + + | BSR EXPR + { if (rx_intop ($2, 16)) + { B1 (0x39); PC2 ($2); } + else if (rx_intop ($2, 24)) + { B1 (0x05); PC3 ($2); } + else + { rx_relax (RX_RELAX_BRANCH, 0); + rx_linkrelax_branch (); + B1 (0x39); PC2 ($2); } } + | BSR DOT_A EXPR + { B1 (0x05), PC3 ($3); } + +/* ---------------------------------------------------------------------- */ + + | BCND DOT_S EXPR + { if ($1 == COND_EQ || $1 == COND_NE) + { B1 ($1 == COND_EQ ? 0x10 : 0x18); rx_disp3 ($3, 5); } + else + as_bad (_("Only BEQ and BNE may have .S")); } + +/* ---------------------------------------------------------------------- */ + + | BCND DOT_B EXPR + { B1 (0x20); F ($1, 4, 4); PC1 ($3); } + + | BRA DOT_B EXPR + { B1 (0x2e), PC1 ($3); } + +/* ---------------------------------------------------------------------- */ + + | BRA DOT_W EXPR + { B1 (0x38), PC2 ($3); } + | BSR DOT_W EXPR + { B1 (0x39), PC2 ($3); } + | BCND DOT_W EXPR + { if ($1 == COND_EQ || $1 == COND_NE) + { B1 ($1 == COND_EQ ? 0x3a : 0x3b); PC2 ($3); } + else + as_bad (_("Only BEQ and BNE may have .W")); } + | BCND EXPR + { if ($1 == COND_EQ || $1 == COND_NE) + { + rx_relax (RX_RELAX_BRANCH, 0); + rx_linkrelax_branch (); + B1 ($1 == COND_EQ ? 0x10 : 0x18); rx_disp3 ($2, 5); + } + else + { + rx_relax (RX_RELAX_BRANCH, 0); + /* This is because we might turn it into a + jump-over-jump long branch. */ + rx_linkrelax_branch (); + B1 (0x20); F ($1, 4, 4); PC1 ($2); + } } + +/* ---------------------------------------------------------------------- */ + + | MOV DOT_B '#' EXPR ',' disp '[' REG ']' + /* rx_disp5op changes the value if it succeeds, so keep it last. */ + { if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, BSIZE)) + { B2 (0x3c, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); } + else + { B2 (0xf8, 0x04); F ($8, 8, 4); DSP ($6, 6, BSIZE); O1 ($4); + if ($4.X_op != O_constant && $4.X_op != O_big) rx_linkrelax_imm (12); } } + + | MOV DOT_W '#' EXPR ',' disp '[' REG ']' + { if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, WSIZE)) + { B2 (0x3d, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); } + else + { B2 (0xf8, 0x01); F ($8, 8, 4); DSP ($6, 6, WSIZE); IMM ($4, 12); } } + + | MOV DOT_L '#' EXPR ',' disp '[' REG ']' + { if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, LSIZE)) + { B2 (0x3e, 0); rx_field5s2 ($6); F ($8, 9, 3); O1 ($4); } + else + { B2 (0xf8, 0x02); F ($8, 8, 4); DSP ($6, 6, LSIZE); IMM ($4, 12); } } + +/* ---------------------------------------------------------------------- */ + + | RTSD '#' EXPR ',' REG '-' REG + { B2 (0x3f, 0); F ($5, 8, 4); F ($7, 12, 4); rtsd_immediate ($3); + if ($5 == 0) + rx_error (_("RTSD cannot pop R0")); + if ($5 > $7) + rx_error (_("RTSD first reg must be <= second reg")); } + +/* ---------------------------------------------------------------------- */ + + | CMP REG ',' REG + { B2 (0x47, 0); F ($2, 8, 4); F ($4, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | CMP disp '[' REG ']' DOT_UB ',' REG + { B2 (0x44, 0); F ($4, 8, 4); F ($8, 12, 4); DSP ($2, 6, BSIZE); } + + | CMP disp '[' REG ']' memex ',' REG + { B3 (MEMEX, 0x04, 0); F ($6, 8, 2); F ($4, 16, 4); F ($8, 20, 4); DSP ($2, 14, sizemap[$6]); } + +/* ---------------------------------------------------------------------- */ + + | MOVU bw REG ',' REG + { B2 (0x5b, 0x00); F ($2, 5, 1); F ($3, 8, 4); F ($5, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | MOVU bw '[' REG ']' ',' REG + { B2 (0x58, 0x00); F ($2, 5, 1); F ($4, 8, 4); F ($7, 12, 4); } + + | MOVU bw EXPR '[' REG ']' ',' REG + { if ($5 <= 7 && $8 <= 7 && rx_disp5op (&$3, $2)) + { B2 (0xb0, 0); F ($2, 4, 1); F ($5, 9, 3); F ($8, 13, 3); rx_field5s ($3); } + else + { B2 (0x58, 0x00); F ($2, 5, 1); F ($5, 8, 4); F ($8, 12, 4); DSP ($3, 6, $2); } } + +/* ---------------------------------------------------------------------- */ + + | SUB '#' EXPR ',' REG + { if (rx_uintop ($3, 4)) + { B2 (0x60, 0); FE ($3, 8, 4); F ($5, 12, 4); } + else + /* This is really an add, but we negate the immediate. */ + { B2 (0x38, 0); F ($5, 8, 4); F ($5, 12, 4); NIMM ($3, 6); } } /* ? */ + + | CMP '#' EXPR ',' REG + { if (rx_uintop ($3, 4)) + { B2 (0x61, 0); FE ($3, 8, 4); F ($5, 12, 4); } + else if (rx_uintop ($3, 8)) + { B2 (0x75, 0x50); F ($5, 12, 4); UO1 ($3); } + else + { B2 (0x74, 0x00); F ($5, 12, 4); IMM ($3, 6); } } + + | ADD '#' EXPR ',' REG + { if (rx_uintop ($3, 4)) + { B2 (0x62, 0); FE ($3, 8, 4); F ($5, 12, 4); } + else + { B2 (0x70, 0); F ($5, 8, 4); F ($5, 12, 4); IMM ($3, 6); } } + + | MUL '#' EXPR ',' REG + { if (rx_uintop ($3, 4)) + { B2 (0x63, 0); FE ($3, 8, 4); F ($5, 12, 4); } + else + { B2 (0x74, 0x10); F ($5, 12, 4); IMM ($3, 6); } } + + | AND_ '#' EXPR ',' REG + { if (rx_uintop ($3, 4)) + { B2 (0x64, 0); FE ($3, 8, 4); F ($5, 12, 4); } + else + { B2 (0x74, 0x20); F ($5, 12, 4); IMM ($3, 6); } } + + | OR '#' EXPR ',' REG + { if (rx_uintop ($3, 4)) + { B2 (0x65, 0); FE ($3, 8, 4); F ($5, 12, 4); } + else + { B2 (0x74, 0x30); F ($5, 12, 4); IMM ($3, 6); } } + + | MOV DOT_L '#' EXPR ',' REG + { if (rx_uintop ($4, 4)) + { B2 (0x66, 0); FE ($4, 8, 4); F ($6, 12, 4); } + else if (rx_uintop ($4, 8)) + { B2 (0x75, 0x40); F ($6, 12, 4); UO1 ($4); } + else + { B2 (0xfb, 0x02); F ($6, 8, 4); IMM ($4, 12); } } + + | MOV '#' EXPR ',' REG + { if (rx_uintop ($3, 4)) + { B2 (0x66, 0); FE ($3, 8, 4); F ($5, 12, 4); } + else if (rx_uintop ($3, 8)) + { B2 (0x75, 0x40); F ($5, 12, 4); UO1 ($3); } + else + { B2 (0xfb, 0x02); F ($5, 8, 4); IMM ($3, 12); } } + +/* ---------------------------------------------------------------------- */ + + | RTSD '#' EXPR + { B1 (0x67); rtsd_immediate ($3); } + +/* ---------------------------------------------------------------------- */ + + | SHLR { sub_op = 0; } op_shift + | SHAR { sub_op = 1; } op_shift + | SHLL { sub_op = 2; } op_shift + +/* ---------------------------------------------------------------------- */ + + | PUSHM REG '-' REG + { + if ($2 == $4) + { B2 (0x7e, 0x80); F (LSIZE, 10, 2); F ($2, 12, 4); } + else + { B2 (0x6e, 0); F ($2, 8, 4); F ($4, 12, 4); } + if ($2 == 0) + rx_error (_("PUSHM cannot push R0")); + if ($2 > $4) + rx_error (_("PUSHM first reg must be <= second reg")); } + +/* ---------------------------------------------------------------------- */ + + | POPM REG '-' REG + { + if ($2 == $4) + { B2 (0x7e, 0xb0); F ($2, 12, 4); } + else + { B2 (0x6f, 0); F ($2, 8, 4); F ($4, 12, 4); } + if ($2 == 0) + rx_error (_("POPM cannot pop R0")); + if ($2 > $4) + rx_error (_("POPM first reg must be <= second reg")); } + +/* ---------------------------------------------------------------------- */ + + | ADD '#' EXPR ',' REG ',' REG + { B2 (0x70, 0x00); F ($5, 8, 4); F ($7, 12, 4); IMM ($3, 6); } + +/* ---------------------------------------------------------------------- */ + + | INT '#' EXPR + { B2(0x75, 0x60), UO1 ($3); } + +/* ---------------------------------------------------------------------- */ + + | BSET '#' EXPR ',' REG + { B2 (0x78, 0); FE ($3, 7, 5); F ($5, 12, 4); } + | BCLR '#' EXPR ',' REG + { B2 (0x7a, 0); FE ($3, 7, 5); F ($5, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | BTST '#' EXPR ',' REG + { B2 (0x7c, 0x00); FE ($3, 7, 5); F ($5, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | SAT REG + { B2 (0x7e, 0x30); F ($2, 12, 4); } + | RORC REG + { B2 (0x7e, 0x40); F ($2, 12, 4); } + | ROLC REG + { B2 (0x7e, 0x50); F ($2, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | PUSH bwl REG + { B2 (0x7e, 0x80); F ($2, 10, 2); F ($3, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | POP REG + { B2 (0x7e, 0xb0); F ($2, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | PUSHC CREG + { if ($2 < 16) + { B2 (0x7e, 0xc0); F ($2, 12, 4); } + else + as_bad (_("PUSHC can only push the first 16 control registers")); } + +/* ---------------------------------------------------------------------- */ + + | POPC CREG + { if ($2 < 16) + { B2 (0x7e, 0xe0); F ($2, 12, 4); } + else + as_bad (_("POPC can only pop the first 16 control registers")); } + +/* ---------------------------------------------------------------------- */ + + | SETPSW flag + { B2 (0x7f, 0xa0); F ($2, 12, 4); } + | CLRPSW flag + { B2 (0x7f, 0xb0); F ($2, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | JMP REG + { B2 (0x7f, 0x00); F ($2, 12, 4); } + | JSR REG + { B2 (0x7f, 0x10); F ($2, 12, 4); } + | BRA opt_l REG + { B2 (0x7f, 0x40); F ($3, 12, 4); } + | BSR opt_l REG + { B2 (0x7f, 0x50); F ($3, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | SCMPU + { B2 (0x7f, 0x83); } + | SMOVU + { B2 (0x7f, 0x87); } + | SMOVB + { B2 (0x7f, 0x8b); } + | SMOVF + { B2 (0x7f, 0x8f); } + +/* ---------------------------------------------------------------------- */ + + | SUNTIL bwl + { B2 (0x7f, 0x80); F ($2, 14, 2); } + | SWHILE bwl + { B2 (0x7f, 0x84); F ($2, 14, 2); } + | SSTR bwl + { B2 (0x7f, 0x88); F ($2, 14, 2); } + +/* ---------------------------------------------------------------------- */ + + | RMPA bwl + { B2 (0x7f, 0x8c); F ($2, 14, 2); } + +/* ---------------------------------------------------------------------- */ + + | RTFI + { B2 (0x7f, 0x94); } + | RTE + { B2 (0x7f, 0x95); } + | WAIT + { B2 (0x7f, 0x96); } + | SATR + { B2 (0x7f, 0x93); } + +/* ---------------------------------------------------------------------- */ + + | MVTIPL '#' EXPR + { B2 (0x7f, 0x98); FE ($3, 13, 3); } + +/* ---------------------------------------------------------------------- */ + + /* rx_disp5op changes the value if it succeeds, so keep it last. */ + | MOV bwl REG ',' EXPR '[' REG ']' + { if ($3 <= 7 && $7 <= 7 && rx_disp5op (&$5, $2)) + { B2 (0x80, 0); F ($2, 2, 2); F ($7, 9, 3); F ($3, 13, 3); rx_field5s ($5); } + else + { B2 (0xc3, 0x00); F ($2, 2, 2); F ($7, 8, 4); F ($3, 12, 4); DSP ($5, 4, $2); }} + +/* ---------------------------------------------------------------------- */ + + | MOV bwl EXPR '[' REG ']' ',' REG + { if ($5 <= 7 && $8 <= 7 && rx_disp5op (&$3, $2)) + { B2 (0x88, 0); F ($2, 2, 2); F ($5, 9, 3); F ($8, 13, 3); rx_field5s ($3); } + else + { B2 (0xcc, 0x00); F ($2, 2, 2); F ($5, 8, 4); F ($8, 12, 4); DSP ($3, 6, $2); } } + +/* ---------------------------------------------------------------------- */ + + /* MOV a,b - if a is a reg and b is mem, src and dest are + swapped. */ + + /* We don't use "disp" here because it causes a shift/reduce + conflict with the other displacement-less patterns. */ + + | MOV bwl REG ',' '[' REG ']' + { B2 (0xc3, 0x00); F ($2, 2, 2); F ($6, 8, 4); F ($3, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | MOV bwl '[' REG ']' ',' disp '[' REG ']' + { B2 (0xc0, 0); F ($2, 2, 2); F ($4, 8, 4); F ($9, 12, 4); DSP ($7, 4, $2); } + +/* ---------------------------------------------------------------------- */ + + | MOV bwl EXPR '[' REG ']' ',' disp '[' REG ']' + { B2 (0xc0, 0x00); F ($2, 2, 2); F ($5, 8, 4); F ($10, 12, 4); DSP ($3, 6, $2); DSP ($8, 4, $2); } + +/* ---------------------------------------------------------------------- */ + + | MOV bwl REG ',' REG + { B2 (0xcf, 0x00); F ($2, 2, 2); F ($3, 8, 4); F ($5, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | MOV bwl '[' REG ']' ',' REG + { B2 (0xcc, 0x00); F ($2, 2, 2); F ($4, 8, 4); F ($7, 12, 4); } + +/* ---------------------------------------------------------------------- */ + + | BSET '#' EXPR ',' disp '[' REG ']' DOT_B + { B2 (0xf0, 0x00); F ($7, 8, 4); FE ($3, 13, 3); DSP ($5, 6, BSIZE); } + | BCLR '#' EXPR ',' disp '[' REG ']' DOT_B + { B2 (0xf0, 0x08); F ($7, 8, 4); FE ($3, 13, 3); DSP ($5, 6, BSIZE); } + | BTST '#' EXPR ',' disp '[' REG ']' DOT_B + { B2 (0xf4, 0x00); F ($7, 8, 4); FE ($3, 13, 3); DSP ($5, 6, BSIZE); } + +/* ---------------------------------------------------------------------- */ + + | PUSH bwl disp '[' REG ']' + { B2 (0xf4, 0x08); F ($2, 14, 2); F ($5, 8, 4); DSP ($3, 6, $2); } + +/* ---------------------------------------------------------------------- */ + + | SBB { sub_op = 0; } op_dp20_rm + | NEG { sub_op = 1; sub_op2 = 1; } op_dp20_rms + | ADC { sub_op = 2; } op_dp20_rim + | ABS { sub_op = 3; sub_op2 = 2; } op_dp20_rms + | MAX { sub_op = 4; } op_dp20_rim + | MIN { sub_op = 5; } op_dp20_rim + | EMUL { sub_op = 6; } op_dp20_i + | EMULU { sub_op = 7; } op_dp20_i + | DIV { sub_op = 8; } op_dp20_rim + | DIVU { sub_op = 9; } op_dp20_rim + | TST { sub_op = 12; } op_dp20_rim + | XOR { sub_op = 13; } op_dp20_rim + | NOT { sub_op = 14; sub_op2 = 0; } op_dp20_rms + | STZ { sub_op = 14; } op_dp20_i + | STNZ { sub_op = 15; } op_dp20_i + +/* ---------------------------------------------------------------------- */ + + | EMUL { sub_op = 6; } op_xchg + | EMULU { sub_op = 7; } op_xchg + | XCHG { sub_op = 16; } op_xchg + | ITOF { sub_op = 17; } op_xchg + +/* ---------------------------------------------------------------------- */ + + | BSET REG ',' REG + { id24 (1, 0x63, 0x00); F ($4, 16, 4); F ($2, 20, 4); } + | BCLR REG ',' REG + { id24 (1, 0x67, 0x00); F ($4, 16, 4); F ($2, 20, 4); } + | BTST REG ',' REG + { id24 (1, 0x6b, 0x00); F ($4, 16, 4); F ($2, 20, 4); } + | BNOT REG ',' REG + { id24 (1, 0x6f, 0x00); F ($4, 16, 4); F ($2, 20, 4); } + + | BSET REG ',' disp '[' REG ']' DOT_B + { id24 (1, 0x60, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); } + | BCLR REG ',' disp '[' REG ']' DOT_B + { id24 (1, 0x64, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); } + | BTST REG ',' disp '[' REG ']' DOT_B + { id24 (1, 0x68, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); } + | BNOT REG ',' disp '[' REG ']' DOT_B + { id24 (1, 0x6c, 0x00); F ($6, 16, 4); F ($2, 20, 4); DSP ($4, 14, BSIZE); } + +/* ---------------------------------------------------------------------- */ + + | FSUB { sub_op = 0; } float2_op + | FCMP { sub_op = 1; } float2_op + | FADD { sub_op = 2; } float2_op + | FMUL { sub_op = 3; } float2_op + | FDIV { sub_op = 4; } float2_op + | FTOI { sub_op = 5; } float2_op_ni + | ROUND { sub_op = 6; } float2_op_ni + +/* ---------------------------------------------------------------------- */ + + | SCCND DOT_L REG + { id24 (1, 0xdb, 0x00); F ($1, 20, 4); F ($3, 16, 4); } + | SCCND bwl disp '[' REG ']' + { id24 (1, 0xd0, 0x00); F ($1, 20, 4); F ($2, 12, 2); F ($5, 16, 4); DSP ($3, 14, $2); } + +/* ---------------------------------------------------------------------- */ + + | BMCND '#' EXPR ',' disp '[' REG ']' DOT_B + { id24 (1, 0xe0, 0x00); F ($1, 20, 4); FE ($3, 11, 3); + F ($7, 16, 4); DSP ($5, 14, BSIZE); } + +/* ---------------------------------------------------------------------- */ + + | BNOT '#' EXPR ',' disp '[' REG ']' DOT_B + { id24 (1, 0xe0, 0x0f); FE ($3, 11, 3); F ($7, 16, 4); + DSP ($5, 14, BSIZE); } + +/* ---------------------------------------------------------------------- */ + + | MULHI REG ',' REG + { id24 (2, 0x00, 0x00); F ($2, 16, 4); F ($4, 20, 4); } + | MULLO REG ',' REG + { id24 (2, 0x01, 0x00); F ($2, 16, 4); F ($4, 20, 4); } + | MACHI REG ',' REG + { id24 (2, 0x04, 0x00); F ($2, 16, 4); F ($4, 20, 4); } + | MACLO REG ',' REG + { id24 (2, 0x05, 0x00); F ($2, 16, 4); F ($4, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + /* We don't have syntax for these yet. */ + | MVTACHI REG + { id24 (2, 0x17, 0x00); F ($2, 20, 4); } + | MVTACLO REG + { id24 (2, 0x17, 0x10); F ($2, 20, 4); } + | MVFACHI REG + { id24 (2, 0x1f, 0x00); F ($2, 20, 4); } + | MVFACMI REG + { id24 (2, 0x1f, 0x20); F ($2, 20, 4); } + | MVFACLO REG + { id24 (2, 0x1f, 0x10); F ($2, 20, 4); } + + | RACW '#' EXPR + { id24 (2, 0x18, 0x00); + if (rx_uintop ($3, 4) && $3.X_add_number == 1) + ; + else if (rx_uintop ($3, 4) && $3.X_add_number == 2) + F (1, 19, 1); + else + as_bad (_("RACW expects #1 or #2"));} + +/* ---------------------------------------------------------------------- */ + + | MOV bwl REG ',' '[' REG '+' ']' + { id24 (2, 0x20, 0); F ($2, 14, 2); F ($6, 16, 4); F ($3, 20, 4); } + | MOV bwl REG ',' '[' '-' REG ']' + { id24 (2, 0x24, 0); F ($2, 14, 2); F ($7, 16, 4); F ($3, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | MOV bwl '[' REG '+' ']' ',' REG + { id24 (2, 0x28, 0); F ($2, 14, 2); F ($4, 16, 4); F ($8, 20, 4); } + | MOV bwl '[' '-' REG ']' ',' REG + { id24 (2, 0x2c, 0); F ($2, 14, 2); F ($5, 16, 4); F ($8, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | MOVU bw '[' REG '+' ']' ',' REG + { id24 (2, 0x38, 0); F ($2, 15, 1); F ($4, 16, 4); F ($8, 20, 4); } + | MOVU bw '[' '-' REG ']' ',' REG + { id24 (2, 0x3c, 0); F ($2, 15, 1); F ($5, 16, 4); F ($8, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | ROTL { sub_op = 6; } op_shift_rot + | ROTR { sub_op = 4; } op_shift_rot + | REVW { sub_op = 5; } op_shift_rot + | REVL { sub_op = 7; } op_shift_rot + +/* ---------------------------------------------------------------------- */ + + | MVTC REG ',' CREG + { id24 (2, 0x68, 0x00); F ($4 % 16, 20, 4); F ($4 / 16, 15, 1); + F ($2, 16, 4); } + +/* ---------------------------------------------------------------------- */ + + | MVFC CREG ',' REG + { id24 (2, 0x6a, 0); F ($2, 15, 5); F ($4, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | ROTL '#' EXPR ',' REG + { id24 (2, 0x6e, 0); FE ($3, 15, 5); F ($5, 20, 4); } + | ROTR '#' EXPR ',' REG + { id24 (2, 0x6c, 0); FE ($3, 15, 5); F ($5, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | MVTC '#' EXPR ',' CREG + { id24 (2, 0x73, 0x00); F ($5, 19, 5); IMM ($3, 12); } + +/* ---------------------------------------------------------------------- */ + + | BMCND '#' EXPR ',' REG + { id24 (2, 0xe0, 0x00); F ($1, 16, 4); FE ($3, 11, 5); + F ($5, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | BNOT '#' EXPR ',' REG + { id24 (2, 0xe0, 0xf0); FE ($3, 11, 5); F ($5, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | MOV bwl REG ',' '[' REG ',' REG ']' + { id24 (3, 0x00, 0); F ($2, 10, 2); F ($6, 12, 4); F ($8, 16, 4); F ($3, 20, 4); } + + | MOV bwl '[' REG ',' REG ']' ',' REG + { id24 (3, 0x40, 0); F ($2, 10, 2); F ($4, 12, 4); F ($6, 16, 4); F ($9, 20, 4); } + + | MOVU bw '[' REG ',' REG ']' ',' REG + { id24 (3, 0xc0, 0); F ($2, 10, 2); F ($4, 12, 4); F ($6, 16, 4); F ($9, 20, 4); } + +/* ---------------------------------------------------------------------- */ + + | SUB { sub_op = 0; } op_subadd + | ADD { sub_op = 2; } op_subadd + | MUL { sub_op = 3; } op_subadd + | AND_ { sub_op = 4; } op_subadd + | OR { sub_op = 5; } op_subadd + +/* ---------------------------------------------------------------------- */ +/* There is no SBB #imm so we fake it with ADC. */ + + | SBB '#' EXPR ',' REG + { id24 (2, 0x70, 0x20); F ($5, 20, 4); NBIMM ($3, 12); } + +/* ---------------------------------------------------------------------- */ + + ; + +/* ====================================================================== */ + +op_subadd + : REG ',' REG + { B2 (0x43 + (sub_op<<2), 0); F ($1, 8, 4); F ($3, 12, 4); } + | disp '[' REG ']' DOT_UB ',' REG + { B2 (0x40 + (sub_op<<2), 0); F ($3, 8, 4); F ($7, 12, 4); DSP ($1, 6, BSIZE); } + | disp '[' REG ']' memex ',' REG + { B3 (MEMEX, sub_op<<2, 0); F ($5, 8, 2); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, sizemap[$5]); } + | REG ',' REG ',' REG + { id24 (4, sub_op<<4, 0), F ($5, 12, 4), F ($1, 16, 4), F ($3, 20, 4); } + ; + +/* sbb, neg, adc, abs, max, min, div, divu, tst, not, xor, stz, stnz, emul, emulu */ + +op_dp20_rm + : REG ',' REG + { id24 (1, 0x03 + (sub_op<<2), 0x00); F ($1, 16, 4); F ($3, 20, 4); } + | disp '[' REG ']' DOT_UB ',' REG + { id24 (1, 0x00 + (sub_op<<2), 0x00); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, BSIZE); } + | disp '[' REG ']' memex ',' REG + { B4 (MEMEX, 0x20 + ($5 << 6), 0x00 + sub_op, 0x00); + F ($3, 24, 4); F ($7, 28, 4); DSP ($1, 14, sizemap[$5]); } + ; + +op_dp20_i + : '#' EXPR ',' REG + { id24 (2, 0x70, sub_op<<4); F ($4, 20, 4); IMM ($2, 12); } + ; + +op_dp20_rim + : op_dp20_rm + | op_dp20_i + ; + +op_dp20_rms + : op_dp20_rm + | REG + { B2 (0x7e, sub_op2 << 4); F ($1, 12, 4); } + ; + +/* xchg, itof, emul, emulu */ +op_xchg + : REG ',' REG + { id24 (1, 0x03 + (sub_op<<2), 0); F ($1, 16, 4); F ($3, 20, 4); } + | disp '[' REG ']' DOT_UB ',' REG + { id24 (1, 0x00 + (sub_op<<2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, BSIZE); } + | disp '[' REG ']' memex ',' REG + { B4 (MEMEX, 0x20, 0x00 + sub_op, 0); F ($5, 8, 2); F ($3, 24, 4); F ($7, 28, 4); + DSP ($1, 14, sizemap[$5]); } + ; + +/* 000:SHLR, 001:SHAR, 010:SHLL, 011:-, 100:ROTR, 101:REVW, 110:ROTL, 111:REVL */ +op_shift_rot + : REG ',' REG + { id24 (2, 0x60 + sub_op, 0); F ($1, 16, 4); F ($3, 20, 4); } + ; +op_shift + : '#' EXPR ',' REG + { B2 (0x68 + (sub_op<<1), 0); FE ($2, 7, 5); F ($4, 12, 4); } + | '#' EXPR ',' REG ',' REG + { id24 (2, 0x80 + (sub_op << 5), 0); FE ($2, 11, 5); F ($4, 16, 4); F ($6, 20, 4); } + | op_shift_rot + ; + + + +float2_op + : '#' EXPR ',' REG + { id24 (2, 0x72, sub_op << 4); F ($4, 20, 4); O4 ($2); } + | float2_op_ni + ; +float2_op_ni + : REG ',' REG + { id24 (1, 0x83 + (sub_op << 2), 0); F ($1, 16, 4); F ($3, 20, 4); } + | disp '[' REG ']' opt_l ',' REG + { id24 (1, 0x80 + (sub_op << 2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, LSIZE); } + ; + +/* ====================================================================== */ + +disp : { $$ = zero_expr (); } + | EXPR { $$ = $1; } + ; + +flag : { need_flag = 1; } FLAG { need_flag = 0; $$ = $2; } + ; + +/* DOT_UB is not listed here, it's handled with a separate pattern. */ +/* Use sizemap[$n] to get LSIZE etc. */ +memex : DOT_B { $$ = 0; } + | DOT_W { $$ = 1; } + | { $$ = 2; } + | DOT_L { $$ = 2; } + | DOT_UW { $$ = 3; } + ; + +bwl : { $$ = LSIZE; } + | DOT_B { $$ = BSIZE; } + | DOT_W { $$ = WSIZE; } + | DOT_L { $$ = LSIZE; } + ; + +bw : { $$ = 1; } + | DOT_B { $$ = 0; } + | DOT_W { $$ = 1; } + ; + +opt_l : {} + | DOT_L {} + ; + +%% +/* ====================================================================== */ + +static struct +{ + const char * string; + int token; + int val; +} +token_table[] = +{ + { "r0", REG, 0 }, + { "r1", REG, 1 }, + { "r2", REG, 2 }, + { "r3", REG, 3 }, + { "r4", REG, 4 }, + { "r5", REG, 5 }, + { "r6", REG, 6 }, + { "r7", REG, 7 }, + { "r8", REG, 8 }, + { "r9", REG, 9 }, + { "r10", REG, 10 }, + { "r11", REG, 11 }, + { "r12", REG, 12 }, + { "r13", REG, 13 }, + { "r14", REG, 14 }, + { "r15", REG, 15 }, + + { "psw", CREG, 0 }, + { "pc", CREG, 1 }, + { "usp", CREG, 2 }, + { "fpsw", CREG, 3 }, + { "cpen", CREG, 4 }, + /* reserved */ + /* reserved */ + { "wr", CREG, 7 }, + + { "bpsw", CREG, 8 }, + { "bpc", CREG, 9 }, + { "isp", CREG, 10 }, + { "fintv", CREG, 11 }, + { "intb", CREG, 12 }, + + { "pbp", CREG, 16 }, + { "pben", CREG, 17 }, + + { "bbpsw", CREG, 24 }, + { "bbpc", CREG, 25 }, + + { ".s", DOT_S, 0 }, + { ".b", DOT_B, 0 }, + { ".w", DOT_W, 0 }, + { ".l", DOT_L, 0 }, + { ".a", DOT_A , 0}, + { ".ub", DOT_UB, 0 }, + { ".uw", DOT_UW , 0}, + + { "c", FLAG, 0 }, + { "z", FLAG, 1 }, + { "s", FLAG, 2 }, + { "o", FLAG, 3 }, + { "i", FLAG, 8 }, + { "u", FLAG, 9 }, + +#define OPC(x) { #x, x, IS_OPCODE } + OPC(ABS), + OPC(ADC), + OPC(ADD), + { "and", AND_, IS_OPCODE }, + OPC(BCLR), + OPC(BCND), + OPC(BMCND), + OPC(BNOT), + OPC(BRA), + OPC(BRK), + OPC(BSET), + OPC(BSR), + OPC(BTST), + OPC(CLRPSW), + OPC(CMP), + OPC(DBT), + OPC(DIV), + OPC(DIVU), + OPC(EDIV), + OPC(EDIVU), + OPC(EMUL), + OPC(EMULU), + OPC(FADD), + OPC(FCMP), + OPC(FDIV), + OPC(FMUL), + OPC(FREIT), + OPC(FSUB), + OPC(FTOI), + OPC(INT), + OPC(ITOF), + OPC(JMP), + OPC(JSR), + OPC(MVFACHI), + OPC(MVFACMI), + OPC(MVFACLO), + OPC(MVFC), + OPC(MVTACHI), + OPC(MVTACLO), + OPC(MVTC), + OPC(MVTIPL), + OPC(MACHI), + OPC(MACLO), + OPC(MAX), + OPC(MIN), + OPC(MOV), + OPC(MOVU), + OPC(MUL), + OPC(MULHI), + OPC(MULLO), + OPC(MULU), + OPC(NEG), + OPC(NOP), + OPC(NOT), + OPC(OR), + OPC(POP), + OPC(POPC), + OPC(POPM), + OPC(PUSH), + OPC(PUSHA), + OPC(PUSHC), + OPC(PUSHM), + OPC(RACW), + OPC(REIT), + OPC(REVL), + OPC(REVW), + OPC(RMPA), + OPC(ROLC), + OPC(RORC), + OPC(ROTL), + OPC(ROTR), + OPC(ROUND), + OPC(RTE), + OPC(RTFI), + OPC(RTS), + OPC(RTSD), + OPC(SAT), + OPC(SATR), + OPC(SBB), + OPC(SCCND), + OPC(SCMPU), + OPC(SETPSW), + OPC(SHAR), + OPC(SHLL), + OPC(SHLR), + OPC(SMOVB), + OPC(SMOVF), + OPC(SMOVU), + OPC(SSTR), + OPC(STNZ), + OPC(STOP), + OPC(STZ), + OPC(SUB), + OPC(SUNTIL), + OPC(SWHILE), + OPC(TST), + OPC(WAIT), + OPC(XCHG), + OPC(XOR), +}; + +#define NUM_TOKENS (sizeof (token_table) / sizeof (token_table[0])) + +static struct +{ + char * string; + int token; +} +condition_opcode_table[] = +{ + { "b", BCND }, + { "bm", BMCND }, + { "sc", SCCND }, +}; + +#define NUM_CONDITION_OPCODES (sizeof (condition_opcode_table) / sizeof (condition_opcode_table[0])) + +static struct +{ + char * string; + int val; +} +condition_table[] = +{ + { "z", 0 }, + { "eq", 0 }, + { "geu", 2 }, + { "c", 2 }, + { "gtu", 4 }, + { "pz", 6 }, + { "ge", 8 }, + { "gt", 10 }, + { "o", 12}, + /* always = 14 */ + { "nz", 1 }, + { "ne", 1 }, + { "ltu", 3 }, + { "nc", 3 }, + { "leu", 5 }, + { "n", 7 }, + { "lt", 9 }, + { "le", 11 }, + { "no", 13 } + /* never = 15 */ +}; + +#define NUM_CONDITIONS (sizeof (condition_table) / sizeof (condition_table[0])) + +void +rx_lex_init (char * beginning, char * ending) +{ + rx_init_start = beginning; + rx_lex_start = beginning; + rx_lex_end = ending; + rx_in_brackets = 0; + rx_last_token = 0; + + setbuf (stdout, 0); +} + +static int +check_condition (char * base) +{ + char * cp; + unsigned int i; + + if ((unsigned) (rx_lex_end - rx_lex_start) < strlen (base) + 1) + return 0; + if (memcmp (rx_lex_start, base, strlen (base))) + return 0; + cp = rx_lex_start + strlen (base); + for (i = 0; i < NUM_CONDITIONS; i ++) + { + if (strcasecmp (cp, condition_table[i].string) == 0) + { + rx_lval.regno = condition_table[i].val; + return 1; + } + } + return 0; +} + +static int +rx_lex (void) +{ + unsigned int ci; + char * save_input_pointer; + + while (ISSPACE (*rx_lex_start) + && rx_lex_start != rx_lex_end) + rx_lex_start ++; + + rx_last_exp_start = rx_lex_start; + + if (rx_lex_start == rx_lex_end) + return 0; + + if (ISALPHA (*rx_lex_start) + || (*rx_lex_start == '.' && ISALPHA (rx_lex_start[1]))) + { + unsigned int i; + char * e; + char save; + + for (e = rx_lex_start + 1; + e < rx_lex_end && ISALNUM (*e); + e ++) + ; + save = *e; + *e = 0; + + if (rx_last_token == 0) + for (ci = 0; ci < NUM_CONDITION_OPCODES; ci ++) + if (check_condition (condition_opcode_table[ci].string)) + { + *e = save; + rx_lex_start = e; + rx_last_token = condition_opcode_table[ci].token; + return condition_opcode_table[ci].token; + } + + for (i = 0; i < NUM_TOKENS; i++) + if (strcasecmp (rx_lex_start, token_table[i].string) == 0 + && !(token_table[i].val == IS_OPCODE && rx_last_token != 0) + && !(token_table[i].token == FLAG && !need_flag)) + { + rx_lval.regno = token_table[i].val; + *e = save; + rx_lex_start = e; + rx_last_token = token_table[i].token; + return token_table[i].token; + } + *e = save; + } + + if (rx_last_token == 0) + { + rx_last_token = UNKNOWN_OPCODE; + return UNKNOWN_OPCODE; + } + + if (rx_last_token == UNKNOWN_OPCODE) + return 0; + + if (*rx_lex_start == '[') + rx_in_brackets = 1; + if (*rx_lex_start == ']') + rx_in_brackets = 0; + + if (rx_in_brackets + || rx_last_token == REG + || strchr ("[],#", *rx_lex_start)) + { + rx_last_token = *rx_lex_start; + return *rx_lex_start ++; + } + + save_input_pointer = input_line_pointer; + input_line_pointer = rx_lex_start; + rx_lval.exp.X_md = 0; + expression (&rx_lval.exp); + + /* We parse but ignore any :<size> modifier on expressions. */ + if (*input_line_pointer == ':') + { + char *cp; + + for (cp = input_line_pointer + 1; *cp && cp < rx_lex_end; cp++) + if (!ISDIGIT (*cp)) + break; + if (cp > input_line_pointer+1) + input_line_pointer = cp; + } + + rx_lex_start = input_line_pointer; + input_line_pointer = save_input_pointer; + rx_last_token = EXPR; + return EXPR; +} + +int +rx_error (char * str) +{ + int len; + + len = rx_last_exp_start - rx_init_start; + + as_bad ("%s", rx_init_start); + as_bad ("%*s^ %s", len, "", str); + return 0; +} + +static int +rx_intop (expressionS exp, int nbits) +{ + long v; + + if (exp.X_op == O_big && nbits == 32) + return 1; + if (exp.X_op != O_constant) + return 0; + v = exp.X_add_number; + + switch (nbits) + { + case 4: + return -0x8 <= v && v <= 0x7; + case 5: + return -0x10 <= v && v <= 0x17; + case 8: + return -0x80 <= v && v <= 0x7f; + case 16: + return -0x8000 <= v && v <= 0x7fff; + case 24: + return -0x800000 <= v && v <= 0x7fffff; + case 32: + return 1; + default: + printf ("rx_intop passed %d\n", nbits); + abort (); + } + return 1; +} + +static int +rx_uintop (expressionS exp, int nbits) +{ + unsigned long v; + + if (exp.X_op != O_constant) + return 0; + v = exp.X_add_number; + + switch (nbits) + { + case 4: + return v <= 0xf; + case 8: + return v <= 0xff; + case 16: + return v <= 0xffff; + case 24: + return v <= 0xffffff; + default: + printf ("rx_uintop passed %d\n", nbits); + abort (); + } + return 1; +} + +static int +rx_disp3op (expressionS exp) +{ + unsigned long v; + + if (exp.X_op != O_constant) + return 0; + v = exp.X_add_number; + if (v < 3 || v > 10) + return 0; + return 1; +} + +static int +rx_disp5op (expressionS * exp, int msize) +{ + long v; + + if (exp->X_op != O_constant) + return 0; + v = exp->X_add_number; + + switch (msize) + { + case BSIZE: + if (0 < v && v <= 31) + return 1; + break; + case WSIZE: + if (v & 1) + return 0; + if (0 < v && v <= 63) + { + exp->X_add_number >>= 1; + return 1; + } + break; + case LSIZE: + if (v & 3) + return 0; + if (0 < v && v <= 127) + { + exp->X_add_number >>= 2; + return 1; + } + break; + } + return 0; +} + +/* Just like the above, but allows a zero displacement. */ + +static int +rx_disp5op0 (expressionS * exp, int msize) +{ + if (exp->X_op != O_constant) + return 0; + if (exp->X_add_number == 0) + return 1; + return rx_disp5op (exp, msize); +} + +static int +exp_val (expressionS exp) +{ + if (exp.X_op != O_constant) + { + rx_error (_("constant expected")); + return 0; + } + return exp.X_add_number; +} + +static expressionS +zero_expr (void) +{ + /* Static, so program load sets it to all zeros, which is what we want. */ + static expressionS zero; + zero.X_op = O_constant; + return zero; +} + +static int +immediate (expressionS exp, int type, int pos) +{ + /* We will emit constants ourself here, so negate them. */ + if (type == RXREL_NEGATIVE && exp.X_op == O_constant) + exp.X_add_number = - exp.X_add_number; + if (type == RXREL_NEGATIVE_BORROW) + { + if (exp.X_op == O_constant) + exp.X_add_number = - exp.X_add_number - 1; + else + rx_error (_("sbb cannot use symbolic immediates")); + } + + if (rx_intop (exp, 8)) + { + rx_op (exp, 1, type); + return 1; + } + else if (rx_intop (exp, 16)) + { + rx_op (exp, 2, type); + return 2; + } + else if (rx_intop (exp, 24)) + { + rx_op (exp, 3, type); + return 3; + } + else if (rx_intop (exp, 32)) + { + rx_op (exp, 4, type); + return 0; + } + else if (type == RXREL_SIGNED) + { + /* This is a symbolic immediate, we will relax it later. */ + rx_relax (RX_RELAX_IMM, pos); + rx_op (exp, linkrelax ? 4 : 1, type); + return 1; + } + else + { + /* Let the linker deal with it. */ + rx_op (exp, 4, type); + return 0; + } +} + +static int +displacement (expressionS exp, int msize) +{ + int val; + int vshift = 0; + + if (exp.X_op == O_symbol + && exp.X_md) + { + switch (exp.X_md) + { + case BFD_RELOC_GPREL16: + switch (msize) + { + case BSIZE: + exp.X_md = BFD_RELOC_RX_GPRELB; + break; + case WSIZE: + exp.X_md = BFD_RELOC_RX_GPRELW; + break; + case LSIZE: + exp.X_md = BFD_RELOC_RX_GPRELL; + break; + } + O2 (exp); + return 2; + } + } + + if (exp.X_op != O_constant) + { + rx_error (_("displacements must be constants")); + return -1; + } + val = exp.X_add_number; + + if (val == 0) + return 0; + + switch (msize) + { + case BSIZE: + break; + case WSIZE: + if (val & 1) + rx_error (_("word displacement not word-aligned")); + vshift = 1; + break; + case LSIZE: + if (val & 3) + rx_error (_("long displacement not long-aligned")); + vshift = 2; + break; + default: + as_bad (_("displacement with unknown size (internal bug?)\n")); + break; + } + + val >>= vshift; + exp.X_add_number = val; + + if (0 <= val && val <= 255 ) + { + O1 (exp); + return 1; + } + + if (0 <= val && val <= 65535) + { + O2 (exp); + return 2; + } + if (val < 0) + rx_error (_("negative displacements not allowed")); + else + rx_error (_("displacement too large")); + return -1; +} + +static void +rtsd_immediate (expressionS exp) +{ + int val; + + if (exp.X_op != O_constant) + { + rx_error (_("rtsd size must be constant")); + return; + } + val = exp.X_add_number; + if (val & 3) + rx_error (_("rtsd size must be multiple of 4")); + + if (val < 0 || val > 1020) + rx_error (_("rtsd size must be 0..1020")); + + val >>= 2; + exp.X_add_number = val; + O1 (exp); +} diff --git a/gas/config/tc-rx.c b/gas/config/tc-rx.c new file mode 100644 index 00000000000..f6353210f18 --- /dev/null +++ b/gas/config/tc-rx.c @@ -0,0 +1,2394 @@ +/* tc-rx.c -- Assembler for the Renesas RX + Copyright 2008, 2009 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "as.h" +#include "struc-symbol.h" +#include "obstack.h" +#include "safe-ctype.h" +#include "dwarf2dbg.h" +#include "libbfd.h" +#include "elf/common.h" +#include "elf/rx.h" +#include "rx-defs.h" +#include "filenames.h" +#include "listing.h" +#include "sb.h" +#include "macro.h" + +#define RX_OPCODE_BIG_ENDIAN 0 + +const char comment_chars[] = ";"; +/* Note that input_file.c hand checks for '#' at the beginning of the + first line of the input file. This is because the compiler outputs + #NO_APP at the beginning of its output. */ +const char line_comment_chars[] = "#"; +const char line_separator_chars[] = "!"; + +const char EXP_CHARS[] = "eE"; +const char FLT_CHARS[] = "dD"; + +/* ELF flags to set in the output file header. */ +static int elf_flags = 0; + +bfd_boolean rx_use_conventional_section_names = FALSE; +static bfd_boolean rx_use_small_data_limit = FALSE; + +enum options +{ + OPTION_BIG = OPTION_MD_BASE, + OPTION_LITTLE, + OPTION_32BIT_DOUBLES, + OPTION_64BIT_DOUBLES, + OPTION_CONVENTIONAL_SECTION_NAMES, + OPTION_RENESAS_SECTION_NAMES, + OPTION_SMALL_DATA_LIMIT, + OPTION_RELAX +}; + +#define RX_SHORTOPTS "" +const char * md_shortopts = RX_SHORTOPTS; + +/* Assembler options. */ +struct option md_longopts[] = +{ + {"mbig-endian-data", no_argument, NULL, OPTION_BIG}, + {"mlittle-endian-data", no_argument, NULL, OPTION_LITTLE}, + /* The next two switches are here because the + generic parts of the linker testsuite uses them. */ + {"EB", no_argument, NULL, OPTION_BIG}, + {"EL", no_argument, NULL, OPTION_LITTLE}, + {"m32bit-doubles", no_argument, NULL, OPTION_32BIT_DOUBLES}, + {"m64bit-doubles", no_argument, NULL, OPTION_64BIT_DOUBLES}, + /* This option is here mainly for the binutils testsuites, + as many of their tests assume conventional section naming. */ + {"muse-conventional-section-names", no_argument, NULL, OPTION_CONVENTIONAL_SECTION_NAMES}, + {"muse-renesas-section-names", no_argument, NULL, OPTION_RENESAS_SECTION_NAMES}, + {"msmall-data-limit", no_argument, NULL, OPTION_SMALL_DATA_LIMIT}, + {"relax", no_argument, NULL, OPTION_RELAX}, + {NULL, no_argument, NULL, 0} +}; +size_t md_longopts_size = sizeof (md_longopts); + +int +md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED) +{ + switch (c) + { + case OPTION_BIG: + target_big_endian = 1; + return 1; + + case OPTION_LITTLE: + target_big_endian = 0; + return 1; + + case OPTION_32BIT_DOUBLES: + elf_flags &= ~ E_FLAG_RX_64BIT_DOUBLES; + return 1; + + case OPTION_64BIT_DOUBLES: + elf_flags |= E_FLAG_RX_64BIT_DOUBLES; + return 1; + + case OPTION_CONVENTIONAL_SECTION_NAMES: + rx_use_conventional_section_names = TRUE; + return 1; + + case OPTION_RENESAS_SECTION_NAMES: + rx_use_conventional_section_names = FALSE; + return 1; + + case OPTION_SMALL_DATA_LIMIT: + rx_use_small_data_limit = TRUE; + return 1; + + case OPTION_RELAX: + linkrelax = 1; + return 1; + } + return 0; +} + +void +md_show_usage (FILE * stream) +{ + fprintf (stream, _(" RX specific command line options:\n")); + fprintf (stream, _(" --mbig-endian-data\n")); + fprintf (stream, _(" --mlittle-endian-data [default]\n")); + fprintf (stream, _(" --m32bit-doubles [default]\n")); + fprintf (stream, _(" --m64bit-doubles\n")); + fprintf (stream, _(" --muse-conventional-section-names\n")); + fprintf (stream, _(" --muse-renesas-section-names [default]\n")); + fprintf (stream, _(" --msmall-data-limit\n")); +} + +static void +s_bss (int ignore ATTRIBUTE_UNUSED) +{ + int temp; + + temp = get_absolute_expression (); + subseg_set (bss_section, (subsegT) temp); + demand_empty_rest_of_line (); +} + +static void +rx_float_cons (int ignore ATTRIBUTE_UNUSED) +{ + if (elf_flags & E_FLAG_RX_64BIT_DOUBLES) + return float_cons ('d'); + return float_cons ('f'); +} + +static char * +rx_strcasestr (const char *string, const char *sub) +{ + int subl; + int strl; + + if (!sub || !sub[0]) + return (char *)string; + + subl = strlen (sub); + strl = strlen (string); + + while (strl >= subl) + { + /* strncasecmp is in libiberty. */ + if (strncasecmp (string, sub, subl) == 0) + return (char *)string; + + string ++; + strl --; + } + return NULL; +} + +static void +rx_include (int ignore) +{ + FILE * try; + char * path; + char * filename; + char * current_filename; + char * eof; + char * p; + char * d; + char * f; + char end_char; + size_t len; + + /* The RX version of the .INCLUDE pseudo-op does not + have to have the filename inside double quotes. */ + SKIP_WHITESPACE (); + if (*input_line_pointer == '"') + { + /* Treat as the normal GAS .include pseudo-op. */ + s_include (ignore); + return; + } + + /* Get the filename. Spaces are allowed, NUL characters are not. */ + filename = input_line_pointer; + eof = find_end_of_line (filename, FALSE); + input_line_pointer = eof; + + while (eof >= filename && (* eof == ' ' || * eof == '\n')) + -- eof; + end_char = *(++ eof); + * eof = 0; + if (eof == filename) + { + as_bad (_("no filename following .INCLUDE pseudo-op")); + * eof = end_char; + return; + } + + as_where (& current_filename, NULL); + f = (char *) xmalloc (strlen (current_filename) + strlen (filename) + 1); + + /* Check the filename. If [@]..FILE[@] is found then replace + this with the current assembler source filename, stripped + of any directory prefixes or extensions. */ + if ((p = rx_strcasestr (filename, "..file")) != NULL) + { + char * c; + + len = 6; /* strlen ("..file"); */ + + if (p > filename && p[-1] == '@') + -- p, ++len; + + if (p[len] == '@') + len ++; + + for (d = c = current_filename; *c; c++) + if (IS_DIR_SEPARATOR (* c)) + d = c + 1; + for (c = d; *c; c++) + if (*c == '.') + break; + + sprintf (f, "%.*s%.*s%.*s", (int) (p - filename), filename, + (int) (c - d), d, + (int) (strlen (filename) - ((p + len) - filename)), + p + len); + } + else + strcpy (f, filename); + + /* RX .INCLUDE semantics say that 'filename' is located by: + + 1. If filename is absolute, just try that. Otherwise... + + 2. If the current source file includes a directory component + then prepend that to the filename and try. Otherwise... + + 3. Try any directories specified by the -I command line + option(s). + + 4 .Try a directory specifed by the INC100 environment variable. */ + + if (IS_ABSOLUTE_PATH (f)) + try = fopen (path = f, FOPEN_RT); + else + { + char * env = getenv ("INC100"); + + try = NULL; + + len = strlen (current_filename); + if ((size_t) include_dir_maxlen > len) + len = include_dir_maxlen; + if (env && strlen (env) > len) + len = strlen (env); + + path = (char *) xmalloc (strlen (f) + len + 5); + + if (current_filename != NULL) + { + for (d = NULL, p = current_filename; *p; p++) + if (IS_DIR_SEPARATOR (* p)) + d = p; + + if (d != NULL) + { + sprintf (path, "%.*s/%s", (int) (d - current_filename), current_filename, + f); + try = fopen (path, FOPEN_RT); + } + } + + if (try == NULL) + { + int i; + + for (i = 0; i < include_dir_count; i++) + { + sprintf (path, "%s/%s", include_dirs[i], f); + if ((try = fopen (path, FOPEN_RT)) != NULL) + break; + } + } + + if (try == NULL && env != NULL) + { + sprintf (path, "%s/%s", env, f); + try = fopen (path, FOPEN_RT); + } + + free (f); + } + + if (try == NULL) + { + as_bad (_("unable to locate include file: %s"), filename); + free (path); + } + else + { + fclose (try); + register_dependency (path); + input_scrub_insert_file (path); + } + + * eof = end_char; +} + +static void +parse_rx_section (char * name) +{ + asection * sec; + int type; + int attr = SHF_ALLOC | SHF_EXECINSTR; + int align = 2; + char end_char; + + do + { + char * p; + + SKIP_WHITESPACE (); + for (p = input_line_pointer; *p && strchr ("\n\t, =", *p) == NULL; p++) + ; + end_char = *p; + *p = 0; + + if (strcasecmp (input_line_pointer, "ALIGN") == 0) + { + *p = end_char; + + if (end_char == ' ') + while (ISSPACE (*p)) + p++; + + if (*p == '=') + { + ++ p; + while (ISSPACE (*p)) + p++; + switch (*p) + { + case '2': align = 2; break; + case '4': align = 4; break; + case '8': align = 8; break; + default: + as_bad (_("unrecognised alignment value in .SECTION directive: %s"), p); + ignore_rest_of_line (); + return; + } + ++ p; + } + + end_char = *p; + } + else if (strcasecmp (input_line_pointer, "CODE") == 0) + attr = SHF_ALLOC | SHF_EXECINSTR; + else if (strcasecmp (input_line_pointer, "DATA") == 0) + attr = SHF_ALLOC | SHF_WRITE; + else if (strcasecmp (input_line_pointer, "ROMDATA") == 0) + attr = SHF_ALLOC; + else + { + as_bad (_("unknown parameter following .SECTION directive: %s"), + input_line_pointer); + + *p = end_char; + input_line_pointer = p + 1; + ignore_rest_of_line (); + return; + } + + *p = end_char; + input_line_pointer = p + 1; + } + while (end_char != '\n' && end_char != 0); + + if ((sec = bfd_get_section_by_name (stdoutput, name)) == NULL) + { + if (strcmp (name, "B") && strcmp (name, "B_1") && strcmp (name, "B_2")) + type = SHT_NULL; + else + type = SHT_NOBITS; + + obj_elf_change_section (name, type, attr, 0, NULL, FALSE, FALSE); + } + else /* Try not to redefine a section, especially B_1. */ + { + int flags = sec->flags; + + type = elf_section_type (sec); + + attr = ((flags & SEC_READONLY) ? 0 : SHF_WRITE) + | ((flags & SEC_ALLOC) ? SHF_ALLOC : 0) + | ((flags & SEC_CODE) ? SHF_EXECINSTR : 0) + | ((flags & SEC_MERGE) ? SHF_MERGE : 0) + | ((flags & SEC_STRINGS) ? SHF_STRINGS : 0) + | ((flags & SEC_THREAD_LOCAL) ? SHF_TLS : 0); + + obj_elf_change_section (name, type, attr, 0, NULL, FALSE, FALSE); + } + + bfd_set_section_alignment (stdoutput, now_seg, align); +} + +static void +rx_section (int ignore) +{ + char * p; + + /* The as100 assembler supports a different syntax for the .section + pseudo-op. So check for it and handle it here if necessary. */ + SKIP_WHITESPACE (); + + /* Peek past the section name to see if arguments follow. */ + for (p = input_line_pointer; *p; p++) + if (*p == ',' || *p == '\n') + break; + + if (*p == ',') + { + int len = p - input_line_pointer; + + while (ISSPACE (*++p)) + ; + + if (*p != '"' && *p != '#') + { + char * name = (char *) xmalloc (len + 1); + + strncpy (name, input_line_pointer, len); + name[len] = 0; + + input_line_pointer = p; + parse_rx_section (name); + return; + } + } + + obj_elf_section (ignore); +} + +static void +rx_list (int ignore ATTRIBUTE_UNUSED) +{ + SKIP_WHITESPACE (); + + if (strncasecmp (input_line_pointer, "OFF", 3)) + listing_list (0); + else if (strncasecmp (input_line_pointer, "ON", 2)) + listing_list (1); + else + as_warn (_("expecting either ON or OFF after .list")); +} + +/* Like the .rept pseudo op, but supports the + use of ..MACREP inside the repeated region. */ + +static void +rx_rept (int ignore ATTRIBUTE_UNUSED) +{ + int count = get_absolute_expression (); + + do_repeat_with_expander (count, "MREPEAT", "ENDR", "..MACREP"); +} + +/* Like cons() accept that strings are allowed. */ + +static void +rx_cons (int size) +{ + SKIP_WHITESPACE (); + + if (* input_line_pointer == '"') + stringer (8+0); + else + cons (size); +} + +static void +rx_nop (int ignore ATTRIBUTE_UNUSED) +{ + ignore_rest_of_line (); +} + +static void +rx_unimp (int idx) +{ + as_warn (_("The \".%s\" pseudo-op is not implemented\n"), + md_pseudo_table[idx].poc_name); + ignore_rest_of_line (); +} + +/* The target specific pseudo-ops which we support. */ +const pseudo_typeS md_pseudo_table[] = +{ + /* These are unimplemented. They're listed first so that we can use + the poc_value as the index into this array, to get the name of + the pseudo. So, keep these (1) first, and (2) in order, with (3) + the poc_value's in sequence. */ + { "btglb", rx_unimp, 0 }, + { "call", rx_unimp, 1 }, + { "einsf", rx_unimp, 2 }, + { "fb", rx_unimp, 3 }, + { "fbsym", rx_unimp, 4 }, + { "id", rx_unimp, 5 }, + { "initsct", rx_unimp, 6 }, + { "insf", rx_unimp, 7 }, + { "instr", rx_unimp, 8 }, + { "lbba", rx_unimp, 9 }, + { "len", rx_unimp, 10 }, + { "optj", rx_unimp, 11 }, + { "rvector", rx_unimp, 12 }, + { "sb", rx_unimp, 13 }, + { "sbbit", rx_unimp, 14 }, + { "sbsym", rx_unimp, 15 }, + { "sbsym16", rx_unimp, 16 }, + + /* These are the do-nothing pseudos. */ + { "stk", rx_nop, 0 }, + /* The manual documents ".stk" but the compiler emits ".stack". */ + { "stack", rx_nop, 0 }, + + /* Theae are Renesas as100 assembler pseudo-ops that we do support. */ + { "addr", rx_cons, 3 }, + { "align", s_align_bytes, 2 }, + { "byte", rx_cons, 1 }, + { "fixed", float_cons, 'f' }, + { "form", listing_psize, 0 }, + { "glb", s_globl, 0 }, + { "include", rx_include, 0 }, + { "list", rx_list, 0 }, + { "lword", rx_cons, 4 }, + { "mrepeat", rx_rept, 0 }, + { "section", rx_section, 0 }, + + /* FIXME: The following pseudo-ops place their values (and associated + label if present) in the data section, regardless of whatever + section we are currently in. At the moment this code does not + implement that part of the semantics. */ + { "blka", s_space, 3 }, + { "blkb", s_space, 1 }, + { "blkd", s_space, 8 }, + { "blkf", s_space, 4 }, + { "blkl", s_space, 4 }, + { "blkw", s_space, 2 }, + + /* Our "standard" pseudos. */ + { "double", rx_float_cons, 0 }, + { "bss", s_bss, 0 }, + { "3byte", cons, 3 }, + { "int", cons, 4 }, + { "word", cons, 4 }, + + /* End of list marker. */ + { NULL, NULL, 0 } +}; + +static asymbol * gp_symbol; + +void +md_begin (void) +{ + if (rx_use_small_data_limit) + /* Make the __gp symbol now rather + than after the symbol table is frozen. We only do this + when supporting small data limits because otherwise we + pollute the symbol table. */ + gp_symbol = symbol_get_bfdsym (symbol_find_or_make ("__gp")); +} + +char * rx_lex_start; +char * rx_lex_end; + +typedef struct rx_bytesT +{ + char base[4]; + int n_base; + char ops[8]; + int n_ops; + struct + { + expressionS exp; + char offset; + char nbits; + char type; /* RXREL_*. */ + int reloc; + fixS * fixP; + } fixups[2]; + int n_fixups; + struct + { + char type; + char field_pos; + char val_ofs; + } relax[2]; + int n_relax; + int link_relax; + fixS *link_relax_fixP; +} rx_bytesT; + +static rx_bytesT rx_bytes; + +void +rx_relax (int type, int pos) +{ + rx_bytes.relax[rx_bytes.n_relax].type = type; + rx_bytes.relax[rx_bytes.n_relax].field_pos = pos; + rx_bytes.relax[rx_bytes.n_relax].val_ofs = rx_bytes.n_base + rx_bytes.n_ops; + rx_bytes.n_relax ++; +} + +void +rx_linkrelax_dsp (int pos) +{ + switch (pos) + { + case 4: + rx_bytes.link_relax |= RX_RELAXA_DSP4; + break; + case 6: + rx_bytes.link_relax |= RX_RELAXA_DSP6; + break; + case 14: + rx_bytes.link_relax |= RX_RELAXA_DSP14; + break; + } +} + +void +rx_linkrelax_imm (int pos) +{ + switch (pos) + { + case 6: + rx_bytes.link_relax |= RX_RELAXA_IMM6; + break; + case 12: + rx_bytes.link_relax |= RX_RELAXA_IMM12; + break; + } +} + +void +rx_linkrelax_branch (void) +{ + rx_bytes.link_relax |= RX_RELAXA_BRA; +} + +static void +rx_fixup (expressionS exp, int offsetbits, int nbits, int type) +{ + rx_bytes.fixups[rx_bytes.n_fixups].exp = exp; + rx_bytes.fixups[rx_bytes.n_fixups].offset = offsetbits; + rx_bytes.fixups[rx_bytes.n_fixups].nbits = nbits; + rx_bytes.fixups[rx_bytes.n_fixups].type = type; + rx_bytes.fixups[rx_bytes.n_fixups].reloc = exp.X_md; + rx_bytes.n_fixups ++; +} + +#define rx_field_fixup(exp, offset, nbits, type) \ + rx_fixup (exp, offset, nbits, type) + +#define rx_op_fixup(exp, offset, nbits, type) \ + rx_fixup (exp, offset + 8 * rx_bytes.n_base, nbits, type) + +void +rx_base1 (int b1) +{ + rx_bytes.base[0] = b1; + rx_bytes.n_base = 1; +} + +void +rx_base2 (int b1, int b2) +{ + rx_bytes.base[0] = b1; + rx_bytes.base[1] = b2; + rx_bytes.n_base = 2; +} + +void +rx_base3 (int b1, int b2, int b3) +{ + rx_bytes.base[0] = b1; + rx_bytes.base[1] = b2; + rx_bytes.base[2] = b3; + rx_bytes.n_base = 3; +} + +void +rx_base4 (int b1, int b2, int b3, int b4) +{ + rx_bytes.base[0] = b1; + rx_bytes.base[1] = b2; + rx_bytes.base[2] = b3; + rx_bytes.base[3] = b4; + rx_bytes.n_base = 4; +} + +/* This gets complicated when the field spans bytes, because fields + are numbered from the MSB of the first byte as zero, and bits are + stored LSB towards the LSB of the byte. Thus, a simple four-bit + insertion of 12 at position 4 of 0x00 yields: 0x0b. A three-bit + insertion of b'MXL at position 7 is like this: + + - - - - - - - - - - - - - - - - + M X L */ + +void +rx_field (int val, int pos, int sz) +{ + int valm; + int bytep, bitp; + + if (sz > 0) + { + if (val < 0 || val >= (1 << sz)) + as_bad (_("Value %d doesn't fit in unsigned %d-bit field"), val, sz); + } + else + { + sz = - sz; + if (val < -(1 << (sz - 1)) || val >= (1 << (sz - 1))) + as_bad (_("Value %d doesn't fit in signed %d-bit field"), val, sz); + } + + /* This code points at 'M' in the above example. */ + bytep = pos / 8; + bitp = pos % 8; + + while (bitp + sz > 8) + { + int ssz = 8 - bitp; + int svalm; + + svalm = val >> (sz - ssz); + svalm = svalm & ((1 << ssz) - 1); + svalm = svalm << (8 - bitp - ssz); + gas_assert (bytep < rx_bytes.n_base); + rx_bytes.base[bytep] |= svalm; + + bitp = 0; + sz -= ssz; + bytep ++; + } + valm = val & ((1 << sz) - 1); + valm = valm << (8 - bitp - sz); + gas_assert (bytep < rx_bytes.n_base); + rx_bytes.base[bytep] |= valm; +} + +/* Special case of the above, for 3-bit displacements of 2..9. */ + +void +rx_disp3 (expressionS exp, int pos) +{ + rx_field_fixup (exp, pos, 3, RXREL_PCREL); +} + +/* Special case of the above, for split 5-bit displacements. Assumes + the displacement has been checked with rx_disp5op. */ +/* ---- -432 1--- 0--- */ + +void +rx_field5s (expressionS exp) +{ + int val; + + val = exp.X_add_number; + rx_bytes.base[0] |= val >> 2; + rx_bytes.base[1] |= (val << 6) & 0x80; + rx_bytes.base[1] |= (val << 3) & 0x08; +} + +/* ---- ---- 4--- 3210 */ + +void +rx_field5s2 (expressionS exp) +{ + int val; + + val = exp.X_add_number; + rx_bytes.base[1] |= (val << 3) & 0x80; + rx_bytes.base[1] |= (val ) & 0x0f; +} + +#define OP(x) rx_bytes.ops[rx_bytes.n_ops++] = (x) + +#define F_PRECISION 2 + +void +rx_op (expressionS exp, int nbytes, int type) +{ + int v = 0; + + if ((exp.X_op == O_constant || exp.X_op == O_big) + && type != RXREL_PCREL) + { + if (exp.X_op == O_big && exp.X_add_number <= 0) + { + LITTLENUM_TYPE w[2]; + char * ip = rx_bytes.ops + rx_bytes.n_ops; + + gen_to_words (w, F_PRECISION, 8); +#if RX_OPCODE_BIG_ENDIAN + ip[0] = w[0] >> 8; + ip[1] = w[0]; + ip[2] = w[1] >> 8; + ip[3] = w[1]; +#else + ip[3] = w[0] >> 8; + ip[2] = w[0]; + ip[1] = w[1] >> 8; + ip[0] = w[1]; +#endif + rx_bytes.n_ops += 4; + } + else + { + v = exp.X_add_number; + while (nbytes) + { +#if RX_OPCODE_BIG_ENDIAN + OP ((v >> (8 * (nbytes - 1))) & 0xff); +#else + OP (v & 0xff); + v >>= 8; +#endif + nbytes --; + } + } + } + else + { + rx_op_fixup (exp, rx_bytes.n_ops * 8, nbytes * 8, type); + memset (rx_bytes.ops + rx_bytes.n_ops, 0, nbytes); + rx_bytes.n_ops += nbytes; + } +} + +int +rx_wrap (void) +{ + return 0; +} + +#define APPEND(B, N_B) \ + if (rx_bytes.N_B) \ + { \ + memcpy (bytes + idx, rx_bytes.B, rx_bytes.N_B); \ + idx += rx_bytes.N_B; \ + } + +void +rx_frag_init (fragS * fragP) +{ + if (rx_bytes.n_relax || rx_bytes.link_relax) + { + fragP->tc_frag_data = malloc (sizeof (rx_bytesT)); + memcpy (fragP->tc_frag_data, & rx_bytes, sizeof (rx_bytesT)); + } + else + fragP->tc_frag_data = 0; +} + +/* Handle the as100's version of the .equ pseudo-op. It has the syntax: + <symbol_name> .equ <expression> */ + +static void +rx_equ (char * name, char * expr) +{ + char saved_name_end_char; + char * name_end; + char * saved_ilp; + + while (ISSPACE (* name)) + name ++; + + for (name_end = name + 1; *name_end; name_end ++) + if (! ISALNUM (* name_end)) + break; + + saved_name_end_char = * name_end; + * name_end = 0; + + saved_ilp = input_line_pointer; + input_line_pointer = expr; + + equals (name, 1); + + input_line_pointer = saved_ilp; + * name_end = saved_name_end_char; +} + +/* Look for Renesas as100 pseudo-ops that occur after a symbol name + rather than at the start of a line. (eg .EQU or .DEFINE). If one + is found, process it and return TRUE otherwise return FALSE. */ + +static bfd_boolean +scan_for_infix_rx_pseudo_ops (char * str) +{ + char * p; + char * pseudo_op; + char * dot = strchr (str, '.'); + + if (dot == NULL || dot == str) + return FALSE; + + /* A real pseudo-op must be preceeded by whitespace. */ + if (dot[-1] != ' ' && dot[-1] != '\t') + return FALSE; + + pseudo_op = dot + 1; + + if (!ISALNUM (* pseudo_op)) + return FALSE; + + for (p = pseudo_op + 1; ISALNUM (* p); p++) + ; + + if (strncasecmp ("EQU", pseudo_op, p - pseudo_op) == 0) + rx_equ (str, p); + else if (strncasecmp ("DEFINE", pseudo_op, p - pseudo_op) == 0) + as_warn (_("The .DEFINE pseudo-op is not implemented")); + else if (strncasecmp ("MACRO", pseudo_op, p - pseudo_op) == 0) + as_warn (_("The .MACRO pseudo-op is not implemented")); + else if (strncasecmp ("BTEQU", pseudo_op, p - pseudo_op) == 0) + as_warn (_("The .BTEQU pseudo-op is not implemented.")); + else + return FALSE; + + return TRUE; +} + +void +md_assemble (char * str) +{ + char * bytes; + int idx = 0; + int i, rel; + fragS * frag_then = frag_now; + expressionS *exp; + + memset (& rx_bytes, 0, sizeof (rx_bytes)); + + rx_lex_init (str, str + strlen (str)); + if (scan_for_infix_rx_pseudo_ops (str)) + return; + rx_parse (); + + /* This simplifies the relaxation code. */ + if (rx_bytes.n_relax || rx_bytes.link_relax) + { + /* We do it this way because we want the frag to have the + rx_bytes in it, which we initialize above. */ + bytes = frag_more (12); + frag_then = frag_now; + frag_variant (rs_machine_dependent, + 0 /* max_chars */, + 0 /* var */, + 0 /* subtype */, + 0 /* symbol */, + 0 /* offset */, + 0 /* opcode */); + frag_then->fr_opcode = bytes; + frag_then->fr_fix += rx_bytes.n_base + rx_bytes.n_ops; + frag_then->fr_subtype = rx_bytes.n_base + rx_bytes.n_ops; + } + else + { + bytes = frag_more (rx_bytes.n_base + rx_bytes.n_ops); + frag_then = frag_now; + } + + APPEND (base, n_base); + APPEND (ops, n_ops); + + if (rx_bytes.link_relax && rx_bytes.n_fixups) + { + fixS * f; + + f = fix_new (frag_then, + (char *) bytes - frag_then->fr_literal, + 0, + abs_section_sym, + rx_bytes.link_relax | rx_bytes.n_fixups, + 0, + BFD_RELOC_RX_RELAX); + frag_then->tc_frag_data->link_relax_fixP = f; + } + + for (i = 0; i < rx_bytes.n_fixups; i ++) + { + /* index: [nbytes][type] */ + static int reloc_map[5][4] = + { + { 0, 0, 0, BFD_RELOC_RX_DIR3U_PCREL }, + { BFD_RELOC_8, BFD_RELOC_RX_8U, BFD_RELOC_RX_NEG8, BFD_RELOC_8_PCREL }, + { BFD_RELOC_RX_16_OP, BFD_RELOC_RX_16U, BFD_RELOC_RX_NEG16, BFD_RELOC_16_PCREL }, + { BFD_RELOC_RX_24_OP, BFD_RELOC_RX_24U, BFD_RELOC_RX_NEG24, BFD_RELOC_24_PCREL }, + { BFD_RELOC_RX_32_OP, BFD_RELOC_32, BFD_RELOC_RX_NEG32, BFD_RELOC_32_PCREL }, + }; + fixS * f; + + idx = rx_bytes.fixups[i].offset / 8; + rel = reloc_map [rx_bytes.fixups[i].nbits / 8][(int) rx_bytes.fixups[i].type]; + + if (rx_bytes.fixups[i].reloc) + rel = rx_bytes.fixups[i].reloc; + + if (frag_then->tc_frag_data) + exp = & frag_then->tc_frag_data->fixups[i].exp; + else + exp = & rx_bytes.fixups[i].exp; + + f = fix_new_exp (frag_then, + (char *) bytes + idx - frag_then->fr_literal, + rx_bytes.fixups[i].nbits / 8, + exp, + rx_bytes.fixups[i].type == RXREL_PCREL ? 1 : 0, + rel); + if (frag_then->tc_frag_data) + frag_then->tc_frag_data->fixups[i].fixP = f; + } + + dwarf2_emit_insn (idx); +} + +void +rx_md_end (void) +{ +} + +/* Write a value out to the object file, using the appropriate endianness. */ + +void +md_number_to_chars (char * buf, valueT val, int n) +{ + if (target_big_endian) + number_to_chars_bigendian (buf, val, n); + else + number_to_chars_littleendian (buf, val, n); +} + +static struct +{ + char * fname; + int reloc; +} +reloc_functions[] = +{ + { "gp", BFD_RELOC_GPREL16 }, + { 0, 0 } +}; + +void +md_operand (expressionS * exp ATTRIBUTE_UNUSED) +{ + int reloc = 0; + int i; + + for (i = 0; reloc_functions[i].fname; i++) + { + int flen = strlen (reloc_functions[i].fname); + + if (input_line_pointer[0] == '%' + && strncasecmp (input_line_pointer + 1, reloc_functions[i].fname, flen) == 0 + && input_line_pointer[flen + 1] == '(') + { + reloc = reloc_functions[i].reloc; + input_line_pointer += flen + 2; + break; + } + } + if (reloc == 0) + return; + + expression (exp); + if (* input_line_pointer == ')') + input_line_pointer ++; + + exp->X_md = reloc; +} + +valueT +md_section_align (segT segment, valueT size) +{ + int align = bfd_get_section_alignment (stdoutput, segment); + return ((size + (1 << align) - 1) & (-1 << align)); +} + +/* When relaxing, we need to output a reloc for any .align directive + so that we can retain this alignment as we adjust opcode sizes. */ +void +rx_handle_align (fragS * frag) +{ + if (linkrelax + && (frag->fr_type == rs_align + || frag->fr_type == rs_align_code) + && frag->fr_address + frag->fr_fix > 0 + && frag->fr_offset > 0 + && now_seg != bss_section) + { + fix_new (frag, frag->fr_fix, 0, + &abs_symbol, RX_RELAXA_ALIGN + frag->fr_offset, + 0, BFD_RELOC_RX_RELAX); + /* For the purposes of relaxation, this relocation is attached + to the byte *after* the alignment - i.e. the byte that must + remain aligned. */ + fix_new (frag->fr_next, 0, 0, + &abs_symbol, RX_RELAXA_ELIGN + frag->fr_offset, + 0, BFD_RELOC_RX_RELAX); + } +} + +char * +md_atof (int type, char * litP, int * sizeP) +{ + return ieee_md_atof (type, litP, sizeP, target_big_endian); +} + +symbolS * +md_undefined_symbol (char * name ATTRIBUTE_UNUSED) +{ + return NULL; +} + +/*----------------------------------------------------------------------*/ +/* To recap: we estimate everything based on md_estimate_size, then + adjust based on rx_relax_frag. When it all settles, we call + md_convert frag to update the bytes. The relaxation types and + relocations are in fragP->tc_frag_data, which is a copy of that + rx_bytes. + + Our scheme is as follows: fr_fix has the size of the smallest + opcode (like BRA.S). We store the number of total bytes we need in + fr_subtype. When we're done relaxing, we use fr_subtype and the + existing opcode bytes to figure out what actual opcode we need to + put in there. If the fixup isn't resolvable now, we use the + maximal size. */ + +#define TRACE_RELAX 0 +#define tprintf if (TRACE_RELAX) printf + +typedef enum +{ + OT_other, + OT_bra, + OT_beq, + OT_bne, + OT_bsr, + OT_bcc +} op_type_T; + +/* We're looking for these types of relaxations: + + BRA.S 00001dsp + BRA.B 00101110 dspppppp + BRA.W 00111000 dspppppp pppppppp + BRA.A 00000100 dspppppp pppppppp pppppppp + + BEQ.S 00010dsp + BEQ.B 00100000 dspppppp + BEQ.W 00111010 dspppppp pppppppp + + BNE.S 00011dsp + BNE.B 00100001 dspppppp + BNE.W 00111011 dspppppp pppppppp + + BSR.W 00111001 dspppppp pppppppp + BSR.A 00000101 dspppppp pppppppp pppppppp + + Bcc.B 0010cond dspppppp + + Additionally, we can synthesize longer conditional branches using + pairs of opcodes, one with an inverted conditional (flip LSB): + + Bcc.W 0010ncnd 00000110 00111000 dspppppp pppppppp + Bcc.A 0010ncnd 00000111 00000100 dspppppp pppppppp pppppppp + BEQ.A 00011100 00000100 dspppppp pppppppp pppppppp + BNE.A 00010100 00000100 dspppppp pppppppp pppppppp */ + +/* Given the opcode bytes at OP, figure out which opcode it is and + return the type of opcode. We use this to re-encode the opcode as + a different size later. */ + +static op_type_T +rx_opcode_type (char * op) +{ + unsigned char b = (unsigned char) op[0]; + + switch (b & 0xf8) + { + case 0x08: return OT_bra; + case 0x10: return OT_beq; + case 0x18: return OT_bne; + } + + switch (b) + { + case 0x2e: return OT_bra; + case 0x38: return OT_bra; + case 0x04: return OT_bra; + + case 0x20: return OT_beq; + case 0x3a: return OT_beq; + + case 0x21: return OT_bne; + case 0x3b: return OT_bne; + + case 0x39: return OT_bsr; + case 0x05: return OT_bsr; + } + + if ((b & 0xf0) == 0x20) + return OT_bcc; + + return OT_other; +} + +/* Returns zero if *addrP has the target address. Else returns nonzero + if we cannot compute the target address yet. */ + +static int +rx_frag_fix_value (fragS * fragP, + segT segment, + int which, + addressT * addrP, + int need_diff, + addressT * sym_addr) +{ + addressT addr = 0; + rx_bytesT * b = fragP->tc_frag_data; + expressionS * exp = & b->fixups[which].exp; + + if (need_diff && exp->X_op != O_subtract) + return 1; + + if (exp->X_add_symbol) + { + if (S_FORCE_RELOC (exp->X_add_symbol, 1)) + return 1; + if (S_GET_SEGMENT (exp->X_add_symbol) != segment) + return 1; + addr += S_GET_VALUE (exp->X_add_symbol); + } + + if (exp->X_op_symbol) + { + if (exp->X_op != O_subtract) + return 1; + if (S_FORCE_RELOC (exp->X_op_symbol, 1)) + return 1; + if (S_GET_SEGMENT (exp->X_op_symbol) != segment) + return 1; + addr -= S_GET_VALUE (exp->X_op_symbol); + } + if (sym_addr) + * sym_addr = addr; + addr += exp->X_add_number; + * addrP = addr; + return 0; +} + +/* Estimate how big the opcode is after this relax pass. The return + value is the difference between fr_fix and the actual size. We + compute the total size in rx_relax_frag and store it in fr_subtype, + sowe only need to subtract fx_fix and return it. */ + +int +md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED) +{ + int opfixsize; + int delta; + + tprintf ("\033[32m est frag: addr %08lx fix %ld var %ld ofs %ld lit %p opc %p type %d sub %d\033[0m\n", + fragP->fr_address + (fragP->fr_opcode - fragP->fr_literal), + fragP->fr_fix, fragP->fr_var, fragP->fr_offset, + fragP->fr_literal, fragP->fr_opcode, fragP->fr_type, fragP->fr_subtype); + + /* This is the size of the opcode that's accounted for in fr_fix. */ + opfixsize = fragP->fr_fix - (fragP->fr_opcode - fragP->fr_literal); + /* This is the size of the opcode that isn't. */ + delta = (fragP->fr_subtype - opfixsize); + + tprintf (" -> opfixsize %d delta %d\n", opfixsize, delta); + return delta; +} + +/* Given the new addresses for this relax pass, figure out how big + each opcode must be. We store the total number of bytes needed in + fr_subtype. The return value is the difference between the size + after the last pass and the size after this pass, so we use the old + fr_subtype to calculate the difference. */ + +int +rx_relax_frag (segT segment ATTRIBUTE_UNUSED, fragS * fragP, long stretch) +{ + addressT addr0, sym_addr; + addressT mypc; + int disp; + int oldsize = fragP->fr_subtype; + int newsize = oldsize; + op_type_T optype; + /* Index of relaxation we care about. */ + int ri; + + tprintf ("\033[36mrelax frag: addr %08lx fix %ld var %ld ofs %ld lit %p opc %p type %d sub %d str %ld\033[0m\n", + fragP->fr_address + (fragP->fr_opcode - fragP->fr_literal), + fragP->fr_fix, fragP->fr_var, fragP->fr_offset, + fragP->fr_literal, fragP->fr_opcode, fragP->fr_type, fragP->fr_subtype, stretch); + + optype = rx_opcode_type (fragP->fr_opcode); + + /* In the one case where we have both a disp and imm relaxation, we want + the imm relaxation here. */ + ri = 0; + if (fragP->tc_frag_data->n_relax > 1 + && fragP->tc_frag_data->relax[0].type == RX_RELAX_DISP) + ri = 1; + + /* Try to get the target address. */ + if (rx_frag_fix_value (fragP, segment, ri, & addr0, + fragP->tc_frag_data->relax[ri].type != RX_RELAX_BRANCH, + & sym_addr)) + { + /* If we don't, we must use the maximum size for the linker. + Note that we don't use synthetically expanded conditionals + for this. */ + switch (fragP->tc_frag_data->relax[ri].type) + { + case RX_RELAX_BRANCH: + switch (optype) + { + case OT_bra: + case OT_bsr: + newsize = 4; + break; + case OT_beq: + case OT_bne: + newsize = 3; + break; + case OT_bcc: + newsize = 2; + break; + case OT_other: + newsize = oldsize; + break; + } + break; + + case RX_RELAX_IMM: + newsize = fragP->tc_frag_data->relax[ri].val_ofs + 4; + break; + } + fragP->fr_subtype = newsize; + tprintf (" -> new %d old %d delta %d (external)\n", newsize, oldsize, newsize-oldsize); + return newsize - oldsize; + } + + mypc = fragP->fr_address + (fragP->fr_opcode - fragP->fr_literal); + if (sym_addr > mypc) + addr0 += stretch; + + switch (fragP->tc_frag_data->relax[ri].type) + { + case RX_RELAX_BRANCH: + tprintf ("branch, addr %08lx pc %08lx disp %ld\n", addr0, mypc, addr0-mypc); + disp = (int) addr0 - (int) mypc; + + switch (optype) + { + case OT_bcc: + if (disp >= -128 && (disp - (oldsize-2)) <= 127) + /* bcc.b */ + newsize = 2; + else if (disp >= -32768 && (disp - (oldsize-5)) <= 32767) + /* bncc.b/bra.w */ + newsize = 5; + else + /* bncc.b/bra.a */ + newsize = 6; + break; + + case OT_beq: + case OT_bne: + if ((disp - (oldsize-1)) >= 3 && (disp - (oldsize-1)) <= 10 && !linkrelax) + /* beq.s */ + newsize = 1; + else if (disp >= -128 && (disp - (oldsize-2)) <= 127) + /* beq.b */ + newsize = 2; + else if (disp >= -32768 && (disp - (oldsize-3)) <= 32767) + /* beq.w */ + newsize = 3; + else + /* bne.s/bra.a */ + newsize = 5; + break; + + case OT_bra: + case OT_bsr: + if ((disp - (oldsize-1)) >= 3 && (disp - (oldsize-1)) <= 10 && !linkrelax) + /* bra.s */ + newsize = 1; + else if (disp >= -128 && (disp - (oldsize-2)) <= 127) + /* bra.b */ + newsize = 2; + else if (disp >= -32768 && (disp - (oldsize-3)) <= 32767) + /* bra.w */ + newsize = 3; + else + /* bra.a */ + newsize = 4; + break; + + case OT_other: + break; + } + tprintf (" - newsize %d\n", newsize); + break; + + case RX_RELAX_IMM: + tprintf ("other, addr %08lx pc %08lx LI %d OF %d\n", addr0, mypc, + fragP->tc_frag_data->relax[ri].field_pos, + fragP->tc_frag_data->relax[ri].val_ofs); + + newsize = fragP->tc_frag_data->relax[ri].val_ofs; + + if ((long) addr0 >= -128 && (long) addr0 <= 127) + newsize += 1; + else if ((long) addr0 >= -32768 && (long) addr0 <= 32767) + newsize += 2; + else if ((long) addr0 >= -8388608 && (long) addr0 <= 8388607) + newsize += 3; + else + newsize += 4; + break; + + default: + break; + } + + if (fragP->tc_frag_data->relax[ri].type == RX_RELAX_BRANCH) + switch (optype) + { + case OT_bra: + case OT_bcc: + case OT_beq: + case OT_bne: + break; + case OT_bsr: + if (newsize < 3) + newsize = 3; + break; + case OT_other: + break; + } + + fragP->fr_subtype = newsize; + tprintf (" -> new %d old %d delta %d\n", newsize, oldsize, newsize-oldsize); + return newsize - oldsize; +} + +/* This lets us test for the opcode type and the desired size in a + switch statement. */ +#define OPCODE(type,size) ((type) * 16 + (size)) + +/* Given the opcode stored in fr_opcode and the number of bytes we + think we need, encode a new opcode. We stored a pointer to the + fixup for this opcode in the tc_frag_data structure. If we can do + the fixup here, we change the relocation type to "none" (we test + for that in tc_gen_reloc) else we change it to the right type for + the new (biggest) opcode. */ + +void +md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED, + fragS * fragP ATTRIBUTE_UNUSED) +{ + rx_bytesT * rxb = fragP->tc_frag_data; + addressT addr0, mypc; + int disp; + int reloc_type, reloc_adjust; + char * op = fragP->fr_opcode; + int keep_reloc = 0; + int ri; + int fi = (rxb->n_fixups > 1) ? 1 : 0; + fixS * fix = rxb->fixups[fi].fixP; + + tprintf ("\033[31mconvrt frag: addr %08lx fix %ld var %ld ofs %ld lit %p opc %p type %d sub %d\033[0m\n", + fragP->fr_address + (fragP->fr_opcode - fragP->fr_literal), + fragP->fr_fix, fragP->fr_var, fragP->fr_offset, + fragP->fr_literal, fragP->fr_opcode, fragP->fr_type, fragP->fr_subtype); + +#if TRACE_RELAX + { + int i; + + printf ("lit %08x opc %08x", (int) fragP->fr_literal, (int) fragP->fr_opcode); + for (i = 0; i < 10; i++) + printf (" %02x", (unsigned char) (fragP->fr_opcode[i])); + printf ("\n"); + } +#endif + + /* In the one case where we have both a disp and imm relaxation, we want + the imm relaxation here. */ + ri = 0; + if (fragP->tc_frag_data->n_relax > 1 + && fragP->tc_frag_data->relax[0].type == RX_RELAX_DISP) + ri = 1; + + /* Try to get the target address. If we fail here, we just use the + largest format. */ + if (rx_frag_fix_value (fragP, segment, 0, & addr0, + fragP->tc_frag_data->relax[ri].type != RX_RELAX_BRANCH, 0)) + keep_reloc = 1; + + if (linkrelax) + keep_reloc = 1; + + /* We used a new frag for this opcode, so the opcode address should + be the frag address. */ + mypc = fragP->fr_address + (fragP->fr_opcode - fragP->fr_literal); + disp = (int) addr0 - (int) mypc; + + reloc_type = BFD_RELOC_NONE; + reloc_adjust = 0; + + tprintf ("convert, op is %d, disp %d (%lx-%lx)\n", rx_opcode_type (fragP->fr_opcode), disp, addr0, mypc); + switch (fragP->tc_frag_data->relax[ri].type) + { + case RX_RELAX_BRANCH: + switch (OPCODE (rx_opcode_type (fragP->fr_opcode), fragP->fr_subtype)) + { + case OPCODE (OT_bra, 1): /* BRA.S - no change. */ + op[0] = 0x08 + (disp & 7); + break; + case OPCODE (OT_bra, 2): /* BRA.B - 8 bit. */ + op[0] = 0x2e; + op[1] = disp; + reloc_type = keep_reloc ? BFD_RELOC_8_PCREL : BFD_RELOC_NONE; + reloc_adjust = 1; + break; + case OPCODE (OT_bra, 3): /* BRA.W - 16 bit. */ + op[0] = 0x38; +#if RX_OPCODE_BIG_ENDIAN + op[1] = (disp >> 8) & 0xff; + op[2] = disp; +#else + op[2] = (disp >> 8) & 0xff; + op[1] = disp; +#endif + reloc_adjust = 1; + reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; + break; + case OPCODE (OT_bra, 4): /* BRA.A - 24 bit. */ + op[0] = 0x04; +#if RX_OPCODE_BIG_ENDIAN + op[1] = (disp >> 16) & 0xff; + op[2] = (disp >> 8) & 0xff; + op[3] = disp; +#else + op[3] = (disp >> 16) & 0xff; + op[2] = (disp >> 8) & 0xff; + op[1] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_24_PCREL : BFD_RELOC_NONE; + reloc_adjust = 1; + break; + + case OPCODE (OT_beq, 1): /* BEQ.S - no change. */ + op[0] = 0x10 + (disp & 7); + break; + case OPCODE (OT_beq, 2): /* BEQ.B - 8 bit. */ + op[0] = 0x20; + op[1] = disp; + reloc_adjust = 1; + reloc_type = keep_reloc ? BFD_RELOC_8_PCREL : BFD_RELOC_NONE; + break; + case OPCODE (OT_beq, 3): /* BEQ.W - 16 bit. */ + op[0] = 0x3a; +#if RX_OPCODE_BIG_ENDIAN + op[1] = (disp >> 8) & 0xff; + op[2] = disp; +#else + op[2] = (disp >> 8) & 0xff; + op[1] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; + reloc_adjust = 1; + break; + case OPCODE (OT_beq, 5): /* BEQ.A - synthetic. */ + op[0] = 0x1e; /* bne.s .+4. */ + op[1] = 0x04; /* bra.a dsp:24. */ + disp -= 1; +#if RX_OPCODE_BIG_ENDIAN + op[2] = (disp >> 16) & 0xff; + op[3] = (disp >> 8) & 0xff; + op[4] = disp; +#else + op[4] = (disp >> 16) & 0xff; + op[3] = (disp >> 8) & 0xff; + op[2] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_24_PCREL : BFD_RELOC_NONE; + reloc_adjust = 2; + break; + + case OPCODE (OT_bne, 1): /* BNE.S - no change. */ + op[0] = 0x18 + (disp & 7); + break; + case OPCODE (OT_bne, 2): /* BNE.B - 8 bit. */ + op[0] = 0x21; + op[1] = disp; + reloc_adjust = 1; + reloc_type = keep_reloc ? BFD_RELOC_8_PCREL : BFD_RELOC_NONE; + break; + case OPCODE (OT_bne, 3): /* BNE.W - 16 bit. */ + op[0] = 0x3b; +#if RX_OPCODE_BIG_ENDIAN + op[1] = (disp >> 8) & 0xff; + op[2] = disp; +#else + op[2] = (disp >> 8) & 0xff; + op[1] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; + reloc_adjust = 1; + break; + case OPCODE (OT_bne, 5): /* BNE.A - synthetic. */ + op[0] = 0x15; /* beq.s .+4. */ + op[1] = 0x04; /* bra.a dsp:24. */ + disp -= 1; +#if RX_OPCODE_BIG_ENDIAN + op[2] = (disp >> 16) & 0xff; + op[3] = (disp >> 8) & 0xff; + op[4] = disp; +#else + op[4] = (disp >> 16) & 0xff; + op[3] = (disp >> 8) & 0xff; + op[2] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_24_PCREL : BFD_RELOC_NONE; + reloc_adjust = 2; + break; + + case OPCODE (OT_bsr, 3): /* BSR.W - 16 bit. */ + op[0] = 0x39; +#if RX_OPCODE_BIG_ENDIAN + op[1] = (disp >> 8) & 0xff; + op[2] = disp; +#else + op[2] = (disp >> 8) & 0xff; + op[1] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; + reloc_adjust = 0; + break; + case OPCODE (OT_bsr, 4): /* BSR.A - 24 bit. */ + op[0] = 0x05; +#if RX_OPCODE_BIG_ENDIAN + op[1] = (disp >> 16) & 0xff; + op[2] = (disp >> 8) & 0xff; + op[3] = disp; +#else + op[3] = (disp >> 16) & 0xff; + op[2] = (disp >> 8) & 0xff; + op[1] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_24_PCREL : BFD_RELOC_NONE; + reloc_adjust = 0; + break; + + case OPCODE (OT_bcc, 2): /* Bcond.B - 8 bit. */ + op[1] = disp; + reloc_type = keep_reloc ? BFD_RELOC_8_PCREL : BFD_RELOC_NONE; + break; + case OPCODE (OT_bcc, 5): /* Bcond.W - synthetic. */ + op[0] ^= 1; /* Invert condition. */ + op[1] = 5; /* Displacement. */ + op[2] = 0x38; + disp -= 2; +#if RX_OPCODE_BIG_ENDIAN + op[3] = (disp >> 8) & 0xff; + op[4] = disp; +#else + op[4] = (disp >> 8) & 0xff; + op[3] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; + reloc_adjust = 2; + break; + case OPCODE (OT_bcc, 6): /* Bcond.S - synthetic. */ + op[0] ^= 1; /* Invert condition. */ + op[1] = 6; /* Displacement. */ + op[2] = 0x04; + disp -= 2; +#if RX_OPCODE_BIG_ENDIAN + op[3] = (disp >> 16) & 0xff; + op[4] = (disp >> 8) & 0xff; + op[5] = disp; +#else + op[5] = (disp >> 16) & 0xff; + op[4] = (disp >> 8) & 0xff; + op[3] = disp; +#endif + reloc_type = keep_reloc ? BFD_RELOC_24_PCREL : BFD_RELOC_NONE; + reloc_adjust = 2; + break; + + default: + /* These are opcodes we'll relax in th linker, later. */ + if (rxb->n_fixups) + reloc_type = rxb->fixups[ri].fixP->fx_r_type; + break; + } + break; + + case RX_RELAX_IMM: + { + int nbytes = fragP->fr_subtype - fragP->tc_frag_data->relax[ri].val_ofs; + int li; + char * imm = op + fragP->tc_frag_data->relax[ri].val_ofs; + + switch (nbytes) + { + case 1: + li = 1; + imm[0] = addr0; + reloc_type = BFD_RELOC_8; + break; + case 2: + li = 2; +#if RX_OPCODE_BIG_ENDIAN + imm[1] = addr0; + imm[0] = addr0 >> 8; +#else + imm[0] = addr0; + imm[1] = addr0 >> 8; +#endif + reloc_type = BFD_RELOC_RX_16_OP; + break; + case 3: + li = 3; +#if RX_OPCODE_BIG_ENDIAN + imm[2] = addr0; + imm[1] = addr0 >> 8; + imm[0] = addr0 >> 16; +#else + imm[0] = addr0; + imm[1] = addr0 >> 8; + imm[2] = addr0 >> 16; +#endif + reloc_type = BFD_RELOC_RX_24_OP; + break; + case 4: + li = 0; +#if RX_OPCODE_BIG_ENDIAN + imm[3] = addr0; + imm[2] = addr0 >> 8; + imm[1] = addr0 >> 16; + imm[0] = addr0 >> 24; +#else + imm[0] = addr0; + imm[1] = addr0 >> 8; + imm[2] = addr0 >> 16; + imm[3] = addr0 >> 24; +#endif + reloc_type = BFD_RELOC_RX_32_OP; + break; + default: + as_bad (_("invalid immediate size")); + li = -1; + } + + switch (fragP->tc_frag_data->relax[ri].field_pos) + { + case 6: + op[0] &= 0xfc; + op[0] |= li; + break; + case 12: + op[1] &= 0xf3; + op[1] |= li << 2; + break; + case 20: + op[2] &= 0xf3; + op[2] |= li << 2; + break; + default: + as_bad (_("invalid immediate field position")); + } + } + break; + + default: + if (rxb->n_fixups) + { + reloc_type = fix->fx_r_type; + reloc_adjust = 0; + } + break; + } + + if (rxb->n_fixups) + { + + fix->fx_r_type = reloc_type; + fix->fx_where += reloc_adjust; + switch (reloc_type) + { + case BFD_RELOC_NONE: + fix->fx_size = 0; + break; + case BFD_RELOC_8: + fix->fx_size = 1; + break; + case BFD_RELOC_16_PCREL: + case BFD_RELOC_RX_16_OP: + fix->fx_size = 2; + break; + case BFD_RELOC_24_PCREL: + case BFD_RELOC_RX_24_OP: + fix->fx_size = 3; + break; + case BFD_RELOC_RX_32_OP: + fix->fx_size = 4; + break; + } + } + + fragP->fr_fix = fragP->fr_subtype + (fragP->fr_opcode - fragP->fr_literal); + tprintf ("fragP->fr_fix now %ld (%d + (%p - %p)\n", fragP->fr_fix, + fragP->fr_subtype, fragP->fr_opcode, fragP->fr_literal); + fragP->fr_var = 0; + + if (fragP->fr_next != NULL + && ((offsetT) (fragP->fr_next->fr_address - fragP->fr_address) + != fragP->fr_fix)) + as_bad (_("bad frag at %p : fix %ld addr %ld %ld \n"), fragP, + fragP->fr_fix, fragP->fr_address, fragP->fr_next->fr_address); +} + +#undef OPCODE + +int +rx_validate_fix_sub (struct fix * f) +{ + /* We permit the subtraction of two symbols as a 32-bit relocation. */ + if (f->fx_r_type == BFD_RELOC_RX_DIFF + && ! f->fx_pcrel + && f->fx_size == 4) + return 1; + return 0; +} + +long +md_pcrel_from_section (fixS * fixP, segT sec) +{ + long rv; + + if (fixP->fx_addsy != NULL + && (! S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != sec)) + /* The symbol is undefined (or is defined but not in this section). + Let the linker figure it out. */ + return 0; + + rv = fixP->fx_frag->fr_address + fixP->fx_where; + switch (fixP->fx_r_type) + { + case BFD_RELOC_RX_DIR3U_PCREL: + return rv; + default: + return rv - 1; + } +} + +void +rx_cons_fix_new (fragS * frag, + int where, + int size, + expressionS * exp) +{ + bfd_reloc_code_real_type type; + + switch (size) + { + case 1: + type = BFD_RELOC_8; + break; + case 2: + type = BFD_RELOC_16; + break; + case 3: + type = BFD_RELOC_24; + break; + case 4: + type = BFD_RELOC_32; + break; + default: + as_bad (_("unsupported constant size %d\n"), size); + return; + } + + if (exp->X_op == O_subtract && exp->X_op_symbol) + { + if (size != 4 && size != 2 && size != 1) + as_bad (_("difference of two symbols only supported with .long, .short, or .byte")); + else + type = BFD_RELOC_RX_DIFF; + } + + fix_new_exp (frag, where, (int) size, exp, 0, type); +} + +void +md_apply_fix (struct fix * f ATTRIBUTE_UNUSED, + valueT * t ATTRIBUTE_UNUSED, + segT s ATTRIBUTE_UNUSED) +{ + /* Instruction bytes are always little endian. */ + char * op; + unsigned long val; + + if (f->fx_addsy && S_FORCE_RELOC (f->fx_addsy, 1)) + return; + if (f->fx_subsy && S_FORCE_RELOC (f->fx_subsy, 1)) + return; + +#define OP2(x) op[target_big_endian ? 1-x : x] +#define OP3(x) op[target_big_endian ? 2-x : x] +#define OP4(x) op[target_big_endian ? 3-x : x] + + op = f->fx_frag->fr_literal + f->fx_where; + val = (unsigned long) * t; + + /* Opcode words are always the same endian. Data words are either + big or little endian. */ + + switch (f->fx_r_type) + { + case BFD_RELOC_NONE: + break; + + case BFD_RELOC_RX_RELAX: + f->fx_done = 1; + break; + + case BFD_RELOC_RX_DIR3U_PCREL: + if (val < 3 || val > 10) + as_bad_where (f->fx_file, f->fx_line, + _("jump not 3..10 bytes away (is %d)"), (int) val); + op[0] &= 0xf8; + op[0] |= val & 0x07; + break; + + case BFD_RELOC_8: + case BFD_RELOC_8_PCREL: + case BFD_RELOC_RX_8U: + op[0] = val; + break; + + case BFD_RELOC_16: + OP2(1) = val & 0xff; + OP2(0) = (val >> 8) & 0xff; + break; + + case BFD_RELOC_16_PCREL: + case BFD_RELOC_RX_16_OP: + case BFD_RELOC_RX_16U: +#if RX_OPCODE_BIG_ENDIAN + op[1] = val & 0xff; + op[0] = (val >> 8) & 0xff; +#else + op[0] = val & 0xff; + op[1] = (val >> 8) & 0xff; +#endif + break; + + case BFD_RELOC_24: + OP3(0) = val & 0xff; + OP3(1) = (val >> 8) & 0xff; + OP3(2) = (val >> 16) & 0xff; + break; + + case BFD_RELOC_24_PCREL: + case BFD_RELOC_RX_24_OP: + case BFD_RELOC_RX_24U: +#if RX_OPCODE_BIG_ENDIAN + op[2] = val & 0xff; + op[1] = (val >> 8) & 0xff; + op[0] = (val >> 16) & 0xff; +#else + op[0] = val & 0xff; + op[1] = (val >> 8) & 0xff; + op[2] = (val >> 16) & 0xff; +#endif + break; + + case BFD_RELOC_RX_DIFF: + switch (f->fx_size) + { + case 1: + op[0] = val & 0xff; + break; + case 2: + OP2(0) = val & 0xff; + OP2(1) = (val >> 8) & 0xff; + break; + case 4: + OP4(0) = val & 0xff; + OP4(1) = (val >> 8) & 0xff; + OP4(2) = (val >> 16) & 0xff; + OP4(3) = (val >> 24) & 0xff; + break; + } + break; + + case BFD_RELOC_32: + OP4(0) = val & 0xff; + OP4(1) = (val >> 8) & 0xff; + OP4(2) = (val >> 16) & 0xff; + OP4(3) = (val >> 24) & 0xff; + break; + + case BFD_RELOC_RX_32_OP: +#if RX_OPCODE_BIG_ENDIAN + op[3] = val & 0xff; + op[2] = (val >> 8) & 0xff; + op[1] = (val >> 16) & 0xff; + op[0] = (val >> 24) & 0xff; +#else + op[0] = val & 0xff; + op[1] = (val >> 8) & 0xff; + op[2] = (val >> 16) & 0xff; + op[3] = (val >> 24) & 0xff; +#endif + break; + + case BFD_RELOC_RX_NEG8: + op[0] = - val; + break; + + case BFD_RELOC_RX_NEG16: + val = -val; +#if RX_OPCODE_BIG_ENDIAN + op[1] = val & 0xff; + op[0] = (val >> 8) & 0xff; +#else + op[0] = val & 0xff; + op[1] = (val >> 8) & 0xff; +#endif + break; + + case BFD_RELOC_RX_NEG24: + val = -val; +#if RX_OPCODE_BIG_ENDIAN + op[2] = val & 0xff; + op[1] = (val >> 8) & 0xff; + op[0] = (val >> 16) & 0xff; +#else + op[0] = val & 0xff; + op[1] = (val >> 8) & 0xff; + op[2] = (val >> 16) & 0xff; +#endif + break; + + case BFD_RELOC_RX_NEG32: + val = -val; +#if RX_OPCODE_BIG_ENDIAN + op[3] = val & 0xff; + op[2] = (val >> 8) & 0xff; + op[1] = (val >> 16) & 0xff; + op[0] = (val >> 24) & 0xff; +#else + op[0] = val & 0xff; + op[1] = (val >> 8) & 0xff; + op[2] = (val >> 16) & 0xff; + op[3] = (val >> 24) & 0xff; +#endif + break; + + case BFD_RELOC_RX_GPRELL: + val >>= 1; + case BFD_RELOC_RX_GPRELW: + val >>= 1; + case BFD_RELOC_RX_GPRELB: +#if RX_OPCODE_BIG_ENDIAN + op[1] = val & 0xff; + op[0] = (val >> 8) & 0xff; +#else + op[0] = val & 0xff; + op[1] = (val >> 8) & 0xff; +#endif + break; + + default: + as_bad (_("Unknown reloc in md_apply_fix: %s"), + bfd_get_reloc_code_name (f->fx_r_type)); + break; + } + + if (f->fx_addsy == NULL) + f->fx_done = 1; +} + +arelent ** +tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp) +{ + static arelent * reloc[5]; + + if (fixp->fx_r_type == BFD_RELOC_NONE) + { + reloc[0] = NULL; + return reloc; + } + + if (fixp->fx_subsy + && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) + { + fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy); + fixp->fx_subsy = NULL; + } + + reloc[0] = (arelent *) xmalloc (sizeof (arelent)); + reloc[0]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + * reloc[0]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + reloc[0]->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc[0]->addend = fixp->fx_offset; + + /* Certain BFD relocations cannot be translated directly into + a single (non-Red Hat) RX relocation, but instead need + multiple RX relocations - handle them here. */ + switch (fixp->fx_r_type) + { + case BFD_RELOC_RX_DIFF: + reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[1] = (arelent *) xmalloc (sizeof (arelent)); + reloc[1]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + * reloc[1]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); + reloc[1]->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc[1]->addend = 0; + reloc[1]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[2] = (arelent *) xmalloc (sizeof (arelent)); + reloc[2]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_OP_SUBTRACT); + reloc[2]->addend = 0; + reloc[2]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[2]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[3] = (arelent *) xmalloc (sizeof (arelent)); + switch (fixp->fx_size) + { + case 1: + reloc[3]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_ABS8); + break; + case 2: + reloc[3]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_ABS16); + break; + case 4: + reloc[3]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_ABS32); + break; + } + reloc[3]->addend = 0; + reloc[3]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[3]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[4] = NULL; + break; + + case BFD_RELOC_RX_GPRELL: + reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[1] = (arelent *) xmalloc (sizeof (arelent)); + reloc[1]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + if (gp_symbol == NULL) + { + if (symbol_table_frozen) + { + symbolS * gp; + + gp = symbol_find ("__gp"); + if (gp == NULL) + as_bad (("unable to create __gp symbol: please re-assemble with the -msmall-data-limit option specified")); + else + gp_symbol = symbol_get_bfdsym (gp); + } + else + gp_symbol = symbol_get_bfdsym (symbol_find_or_make ("__gp")); + } + * reloc[1]->sym_ptr_ptr = gp_symbol; + reloc[1]->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc[1]->addend = 0; + reloc[1]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[2] = (arelent *) xmalloc (sizeof (arelent)); + reloc[2]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_OP_SUBTRACT); + reloc[2]->addend = 0; + reloc[2]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[2]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[3] = (arelent *) xmalloc (sizeof (arelent)); + reloc[3]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_ABS16UL); + reloc[3]->addend = 0; + reloc[3]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[3]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[4] = NULL; + break; + + case BFD_RELOC_RX_GPRELW: + reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[1] = (arelent *) xmalloc (sizeof (arelent)); + reloc[1]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + if (gp_symbol == NULL) + { + if (symbol_table_frozen) + { + symbolS * gp; + + gp = symbol_find ("__gp"); + if (gp == NULL) + as_bad (("unable to create __gp symbol: please re-assemble with the -msmall-data-limit option specified")); + else + gp_symbol = symbol_get_bfdsym (gp); + } + else + gp_symbol = symbol_get_bfdsym (symbol_find_or_make ("__gp")); + } + * reloc[1]->sym_ptr_ptr = gp_symbol; + reloc[1]->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc[1]->addend = 0; + reloc[1]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[2] = (arelent *) xmalloc (sizeof (arelent)); + reloc[2]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_OP_SUBTRACT); + reloc[2]->addend = 0; + reloc[2]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[2]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[3] = (arelent *) xmalloc (sizeof (arelent)); + reloc[3]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_ABS16UW); + reloc[3]->addend = 0; + reloc[3]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[3]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[4] = NULL; + break; + + case BFD_RELOC_RX_GPRELB: + reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[1] = (arelent *) xmalloc (sizeof (arelent)); + reloc[1]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + if (gp_symbol == NULL) + { + if (symbol_table_frozen) + { + symbolS * gp; + + gp = symbol_find ("__gp"); + if (gp == NULL) + as_bad (("unable to create __gp symbol: please re-assemble with the -msmall-data-limit option specified")); + else + gp_symbol = symbol_get_bfdsym (gp); + } + else + gp_symbol = symbol_get_bfdsym (symbol_find_or_make ("__gp")); + } + * reloc[1]->sym_ptr_ptr = gp_symbol; + reloc[1]->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc[1]->addend = 0; + reloc[1]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_SYM); + + reloc[2] = (arelent *) xmalloc (sizeof (arelent)); + reloc[2]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_OP_SUBTRACT); + reloc[2]->addend = 0; + reloc[2]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[2]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[3] = (arelent *) xmalloc (sizeof (arelent)); + reloc[3]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RX_ABS16U); + reloc[3]->addend = 0; + reloc[3]->sym_ptr_ptr = reloc[1]->sym_ptr_ptr; + reloc[3]->address = fixp->fx_frag->fr_address + fixp->fx_where; + + reloc[4] = NULL; + break; + + default: + reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); + reloc[1] = NULL; + break; + } + + return reloc; +} + +/* Set the ELF specific flags. */ + +void +rx_elf_final_processing (void) +{ + elf_elfheader (stdoutput)->e_flags |= elf_flags; +} + +/* Scan the current input line for occurances of Renesas + local labels and replace them with the GAS version. */ + +void +rx_start_line (void) +{ + int in_double_quote = 0; + int in_single_quote = 0; + int done = 0; + char * p = input_line_pointer; + + /* Scan the line looking for question marks. Skip past quote enclosed regions. */ + do + { + switch (*p) + { + case '\n': + case 0: + done = 1; + break; + + case '"': + in_double_quote = ! in_double_quote; + break; + + case '\'': + in_single_quote = ! in_single_quote; + break; + + case '?': + if (in_double_quote || in_single_quote) + break; + + if (p[1] == ':') + *p = '1'; + else if (p[1] == '+') + { + p[0] = '1'; + p[1] = 'f'; + } + else if (p[1] == '-') + { + p[0] = '1'; + p[1] = 'b'; + } + break; + + default: + break; + } + + p ++; + } + while (! done); +} diff --git a/gas/config/tc-rx.h b/gas/config/tc-rx.h new file mode 100644 index 00000000000..592eb35c0d8 --- /dev/null +++ b/gas/config/tc-rx.h @@ -0,0 +1,93 @@ +/* tc-rx.h - header file for Renesas RX + Copyright 2008, 2009 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#define TC_RX + +extern int target_big_endian; + +#define LISTING_HEADER (target_big_endian ? "RX GAS BE" : "RX GAS LE") +#define LISTING_LHS_WIDTH 8 +#define LISTING_WORD_SIZE 1 + +#define TARGET_ARCH bfd_arch_rx + +/* Instruction bytes are big endian, data bytes can be either. */ +#define TARGET_BYTES_BIG_ENDIAN 0 + +#define TARGET_FORMAT (target_big_endian ? "elf32-rx-be" : "elf32-rx-le") + +/* We don't need to handle .word strangely. */ +#define WORKING_DOT_WORD + +/* Permit temporary numeric labels. */ +#define LOCAL_LABELS_FB 1 +/* But make sure that the binutils treat them as locals. */ +#define LOCAL_LABEL_PREFIX '.' + +/* Allow classic-style constants. */ +#define NUMBERS_WITH_SUFFIX 1 + +/* .-foo gets turned into PC relative relocs. */ +#define DIFF_EXPR_OK + +#define md_end rx_md_end +extern void rx_md_end (void); + +#define md_relax_frag rx_relax_frag +extern int rx_relax_frag (segT, fragS *, long); + +#define TC_FRAG_TYPE struct rx_bytesT * +#define TC_FRAG_INIT rx_frag_init +extern void rx_frag_init (fragS *); + +/* Call md_pcrel_from_section(), not md_pcrel_from(). */ +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) +extern long md_pcrel_from_section (struct fix *, segT); + +/* RX doesn't have a 32 bit PCREL relocations. */ +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 + +#define TC_VALIDATE_FIX_SUB(FIX, SEG) \ + rx_validate_fix_sub (FIX) +extern int rx_validate_fix_sub (struct fix *); + +#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ + rx_cons_fix_new (FRAG, WHERE, NBYTES, EXP) +extern void rx_cons_fix_new (fragS *, int, int, expressionS *); + +#define tc_fix_adjustable(x) 0 + +#define HANDLE_ALIGN(FRAG) rx_handle_align (FRAG) +extern void rx_handle_align (fragS *); + +#define RELOC_EXPANSION_POSSIBLE 1 +#define MAX_RELOC_EXPANSION 4 + +#define elf_tc_final_processing rx_elf_final_processing +extern void rx_elf_final_processing (void); + +extern bfd_boolean rx_use_conventional_section_names; +#define TEXT_SECTION_NAME (rx_use_conventional_section_names ? ".text" : "P") +#define DATA_SECTION_NAME (rx_use_conventional_section_names ? ".data" : "D_1") +#define BSS_SECTION_NAME (rx_use_conventional_section_names ? ".bss" : "B_1") + +#define md_start_line_hook rx_start_line +extern void rx_start_line (void); diff --git a/gas/configure b/gas/configure index a0d17636fa3..374a6b092ed 100755 --- a/gas/configure +++ b/gas/configure @@ -12029,6 +12029,13 @@ _ACEOF fi ;; + rx) + echo ${extra_objects} | grep -s "rx-parse.o" + if test $? -ne 0 ; then + extra_objects="$extra_objects rx-parse.o" + fi + ;; + xstormy16) using_cgen=yes ;; diff --git a/gas/configure.in b/gas/configure.in index 2c456e0a6ab..8441e138e31 100644 --- a/gas/configure.in +++ b/gas/configure.in @@ -353,6 +353,13 @@ changequote([,])dnl fi ;; + rx) + echo ${extra_objects} | grep -s "rx-parse.o" + if test $? -ne 0 ; then + extra_objects="$extra_objects rx-parse.o" + fi + ;; + xstormy16) using_cgen=yes ;; diff --git a/gas/configure.tgt b/gas/configure.tgt index 054f2b8b4a8..043f445269f 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -65,6 +65,7 @@ case ${cpu} in powerpc*le*) cpu_type=ppc endian=little ;; powerpc*) cpu_type=ppc endian=big ;; rs6000*) cpu_type=ppc ;; + rx) cpu_type=rx ;; s390x*) cpu_type=s390 arch=s390x ;; s390*) cpu_type=s390 arch=s390 ;; score*l) cpu_type=score endian=little ;; diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am index e00243c4c67..36a89d9917c 100644 --- a/gas/doc/Makefile.am +++ b/gas/doc/Makefile.am @@ -58,6 +58,7 @@ CPU_DOCS = \ c-pdp11.texi \ c-pj.texi \ c-ppc.texi \ + c-rx.texi \ c-s390.texi \ c-score.texi \ c-sh.texi \ diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in index 74e3c91322a..74bdb7eaca9 100644 --- a/gas/doc/Makefile.in +++ b/gas/doc/Makefile.in @@ -296,6 +296,7 @@ CPU_DOCS = \ c-pdp11.texi \ c-pj.texi \ c-ppc.texi \ + c-rx.texi \ c-s390.texi \ c-score.texi \ c-sh.texi \ diff --git a/gas/doc/all.texi b/gas/doc/all.texi index b16d26c237c..9ed3647ccff 100644 --- a/gas/doc/all.texi +++ b/gas/doc/all.texi @@ -58,6 +58,7 @@ @set PDP11 @set PJ @set PPC +@set RX @set S390 @set SCORE @set SH diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 2d9188d3e50..e676f84fb36 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -421,6 +421,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}] [@b{-msolaris}|@b{-mno-solaris}] @end ifset +@ifset RX + +@emph{Target RX options:} + [@b{-mlittle-endian}|@b{-mbig-endian}] + [@b{-m32bit-ints}|@b{-m16bit-ints}] + [@b{-m32bit-doubles}|@b{-m64bit-doubles}] +@end ifset @ifset S390 @emph{Target s390 options:} diff --git a/gas/doc/c-rx.texi b/gas/doc/c-rx.texi new file mode 100644 index 00000000000..33ffe1933aa --- /dev/null +++ b/gas/doc/c-rx.texi @@ -0,0 +1,145 @@ +@c Copyright 2008, 2009 +@c Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC +@page +@node RX-Dependent +@chapter RX Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter RX Dependent Features +@end ifclear + +@cindex RX support +@menu +* RX-Opts:: RX Assembler Command Line Options +* RX-Modifiers:: Symbolic Operand Modifiers +* RX-Directives:: Assembler Directives +* RX-Float:: Floating Point +@end menu + +@node RX-Opts +@section RX Options +@cindex options, RX +@cindex RX options + +The Renesas RX port of @code{@value{AS}} has a few target specfic +command line options: + +@table @code + +@cindex @samp{-m32bit-doubles} +@item -m32bit-doubles +This option controls the ABI and indicates to use a 32-bit float ABI. +It has no effect on the assembled instructions, but it does influence +the behaviour of the @samp{.double} pseudo-op. +This is the default. + +@cindex @samp{-m64bit-doubles} +@item -m64bit-doubles +This option controls the ABI and indicates to use a 64-bit float ABI. +It has no effect on the assembled instructions, but it does influence +the behaviour of the @samp{.double} pseudo-op. + +@cindex @samp{-mbig-endian} +@item -mbig-endian +This option controls the ABI and indicates to use a big-endian data +ABI. It has no effect on the assembled instructions, but it does +influence the behaviour of the @samp{.short}, @samp{.hword}, @samp{.int}, +@samp{.word}, @samp{.long}, @samp{.quad} and @samp{.octa} pseudo-ops. + +@cindex @samp{-mlittle-endian} +@item -mlittle-endian +This option controls the ABI and indicates to use a little-endian data +ABI. It has no effect on the assembled instructions, but it does +influence the behaviour of the @samp{.short}, @samp{.hword}, @samp{.int}, +@samp{.word}, @samp{.long}, @samp{.quad} and @samp{.octa} pseudo-ops. +This is the default. + +@cindex @samp{-muse-conventional-section-names} +@item -muse-conventional-section-names +This option controls the default names given to the code (.text), +initialised data (.data) and uninitialised data sections (.bss). + +@cindex @samp{-muse-renesas-section-names} +@item -muse-renesas-section-names +This option controls the default names given to the code (.P), +initialised data (.D_1) and uninitialised data sections (.B_1). +This is the default. + +@cindex @samp{-msmall-data-limit} +@item -msmall-data-limit +This option tells the assembler that the small data limit feature of +the RX port of GCC is being used. This results in the assembler +generating an undefined reference to a symbol called __gp for use by +the relocations that are needed to support the small data limit +feature. This option is not enabled by default as it would otherwise +pollute the symbol table. + +@end table + +@node RX-Modifiers +@section Symbolic Operand Modifiers + +@cindex RX modifiers +@cindex syntax, RX + +The assembler supports several modifiers when using symbol addresses +in RX instruction operands. The general syntax is the following: + +@smallexample +%modifier(symbol) +@end smallexample + +@table @code +@cindex symbol modifiers + +@item %gp +@c FIXME: Add documentation here. + +@end table + +@node RX-Directives +@section Assembler Directives + +@cindex assembler directives, RX +@cindex RX assembler directives + +The RX version of @code{@value{AS}} has the following specific +assembler directives: + +@table @code + +@item .3byte +@cindex assembler directive .3byte, RX +@cindex RX assembler directive .3byte +Inserts a 3-byte value into the output file at the current location. + +@end table + +@node RX-Float +@section Floating Point + +@cindex floating point, RX +@cindex RX floating point + +The floating point formats generated by directives are these. + +@table @code +@cindex @code{float} directive, RX + +@item .float +@code{Single} precision (32-bit) floating point constants. + +@cindex @code{double} directive, RX +@item .double +If the @option{-m64bit-doubles} command line option has been specified +then then @code{double} directive generates @code{double} precision +(64-bit) floating point constants, otherwise it generates +@code{single} precision (32-bit) floating point constants. To force +the generation of 64-bit floating point constants used the @code{dc.d} +directive instead. + +@end table diff --git a/gas/read.c b/gas/read.c index 5ebe288a9c1..2fa01178964 100644 --- a/gas/read.c +++ b/gas/read.c @@ -2981,6 +2981,57 @@ do_repeat (int count, const char *start, const char *end) buffer_limit = input_scrub_next_buffer (&input_line_pointer); } +/* Like do_repeat except that any text matching EXPANDER in the + block is replaced by the itteration count. */ + +void +do_repeat_with_expander (int count, + const char * start, + const char * end, + const char * expander) +{ + sb one; + sb many; + + sb_new (&one); + if (!buffer_and_nest (start, end, &one, get_non_macro_line_sb)) + { + as_bad (_("%s without %s"), start, end); + return; + } + + sb_new (&many); + + if (expander != NULL && strstr (one.ptr, expander) != NULL) + { + while (count -- > 0) + { + int len; + char * sub; + sb processed; + + sb_new (& processed); + sb_add_sb (& processed, & one); + sub = strstr (processed.ptr, expander); + len = sprintf (sub, "%d", count); + gas_assert (len < 8); + strcpy (sub + len, sub + 8); + processed.len -= (8 - len); + sb_add_sb (& many, & processed); + sb_kill (& processed); + } + } + else + while (count-- > 0) + sb_add_sb (&many, &one); + + sb_kill (&one); + + input_scrub_include_sb (&many, input_line_pointer, 1); + sb_kill (&many); + buffer_limit = input_scrub_next_buffer (&input_line_pointer); +} + /* Skip to end of current repeat loop; EXTRA indicates how many additional input buffers to skip. Assumes that conditionals preceding the loop end are properly nested. diff --git a/gas/read.h b/gas/read.h index 1446611b9b2..82ccc759eed 100644 --- a/gas/read.h +++ b/gas/read.h @@ -127,6 +127,7 @@ extern void stabs_generate_asm_lineno (void); extern void stabs_generate_asm_func (const char *, const char *); extern void stabs_generate_asm_endfunc (const char *, const char *); extern void do_repeat (int,const char *,const char *); +extern void do_repeat_with_expander (int, const char *, const char *, const char *); extern void end_repeat (int); extern void do_parse_cons_expression (expressionS *, int); diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index deb9d07201a..8c151a41819 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * gas/rx: New directory. + * gas/rx/*: New set of test cases. + * gas/elf/section2.e-rx: New expected output file. + * gas/all/gas.exp: Add support for RX target. + * gas/elf/elf.exp: Likewise. + * gas/lns/lns.exp: Likewise. + * gas/macros/macros.exp: Likewise. + 2009-09-29 Peter Bergner <bergner@vnet.ibm.com> * gas/ppc/vsx.s ("lxsdux", "lxvd2ux", "lxvw4ux", "stxsdux", diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index 2b93f57f4a3..80082367eb6 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -38,8 +38,11 @@ if { ![istarget cris-*-*] && ![istarget crisv32-*-*] # The MN10300 port supports link time relaxation which in turn allows # for link time resolution of the differneces of two symbols which are # undefined at assembly time. Hence this test will not pass for the -# MN10300. -if { ![istarget hppa*-*-*] && ![istarget mn10300-*-*] && ![istarget am3*-*-*] } then { +# MN10300. The same thing is true for the RX port as well. +if { ![istarget hppa*-*-*] + && ![istarget rx-*-*] + && ![istarget mn10300-*-*] + && ![istarget am3*-*-*] } then { gas_test_error "diff1.s" "" "difference of two undefined symbols" } @@ -109,12 +112,12 @@ case $target_triplet in { # symbol `sym' required but not present setup_xfail "*arm*-*-*aout*" "*arm*-*-*coff" \ "*arm*-*-pe" "m68hc*-*-*" "maxq-*-*" \ - "vax*-*-*" "z8k-*-*" + "rx-*-*" "vax*-*-*" "z8k-*-*" run_dump_test redef2 setup_xfail "*-*-aix*" "*-*-coff" "*-*-cygwin" "*-*-mingw*" "*-*-pe*" \ "bfin-*-*" "hppa*-*-hpux*" \ "m68hc*-*-*" "maxq-*-*" "or32-*-*" \ - "vax*-*-*" "z8k-*-*" + "rx-*-*" "vax*-*-*" "z8k-*-*" run_dump_test redef3 gas_test_error "redef4.s" "" ".set for symbol already used as label" gas_test_error "redef5.s" "" ".set for symbol already defined through .comm" @@ -163,7 +166,7 @@ proc general_info_section {} { gas_start "comment.s" "-agn" while 1 { expect { - -re "^ \[^\n\]*\t: \-agn\[^\n\]*\n" { set x1 1 } + -re "^ \[^\n\]*\t: .*\-agn\[^\n\]*\n" { set x1 1 } -re "^ \[^\n\]*\t: \[^\n\]*comment\.s\[^\n\]*\n" { set x2 1 } -re "^ \[^\n\]*\t: a\.out\[^\n\]*\n" { set x3 1 } -re "\[^\n\]*\n" { } @@ -300,6 +303,7 @@ case $target_triplet in { { hppa*-*-* } { } { *c4x*-*-* } { } { *c54x*-*-* } { } + { rx-*-* } { } default { test_cond remote_download host "$srcdir/$subdir/incbin.dat" diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index caf8436824a..e65d2cfa105 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -62,6 +62,9 @@ if { ([istarget "*-*-*elf*"] if {[istarget "xtensa*-*-*"]} then { set target_machine -xtensa } + if {[istarget "rx-*-*"]} then { + set target_machine -rx + } if { ([istarget "*arm*-*-*"] || [istarget "xscale*-*-*"]) } { @@ -111,6 +114,7 @@ if { ([istarget "*-*-*elf*"] { mn10200-*-* } { } { mn10300-*-* } { } { *c54x*-*-* } { } + { rx-*-* } { } default { # The next test can fail if the target does not convert fixups # against ordinary symbols into relocations against section symbols. diff --git a/gas/testsuite/gas/elf/section2.e-rx b/gas/testsuite/gas/elf/section2.e-rx new file mode 100644 index 00000000000..574219d9a60 --- /dev/null +++ b/gas/testsuite/gas/elf/section2.e-rx @@ -0,0 +1,9 @@ + +Symbol table '.symtab' contains . entries: + Num: Value[ ]* Size Type Bind Vis Ndx Name + 0: 0+0 0 NOTYPE LOCAL DEFAULT UND + 1: 0+0 0 SECTION LOCAL DEFAULT 1 + 2: 0+0 0 SECTION LOCAL DEFAULT 2 + 3: 0+0 0 SECTION LOCAL DEFAULT 3 + 4: 0+0 0 SECTION LOCAL DEFAULT 4 +#... diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp index 025a8568778..4fba663c85a 100644 --- a/gas/testsuite/gas/lns/lns.exp +++ b/gas/testsuite/gas/lns/lns.exp @@ -13,6 +13,7 @@ if { && ![istarget i960-*-*] && ![istarget mcore-*-*] && ![istarget or32-*-*] + && ![istarget rx-*-*] && ![istarget s390*-*-*] } { # Use alternate file for targets using DW_LNS_fixed_advance_pc opcodes. diff --git a/gas/testsuite/gas/macros/macros.exp b/gas/testsuite/gas/macros/macros.exp index f8d5c8012f4..9a4aec814b7 100644 --- a/gas/testsuite/gas/macros/macros.exp +++ b/gas/testsuite/gas/macros/macros.exp @@ -65,6 +65,7 @@ case $target_triplet in { { m68*-*-* } { } { m88*-*-* } { } { mmix-* } { } + { rx-*-* } { } { z80-* } { } default { run_list_test dot "-alm" } } diff --git a/gas/testsuite/gas/rx/abs.d b/gas/testsuite/gas/rx/abs.d new file mode 100644 index 00000000000..1a91231d581 --- /dev/null +++ b/gas/testsuite/gas/rx/abs.d @@ -0,0 +1,14 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e 20 abs r0 + 2: 7e 2f abs r15 + 4: fc 0f 00 abs r0, r0 + 7: fc 0f 0f abs r0, r15 + a: fc 0f f0 abs r15, r0 + d: fc 0f ff abs r15, r15 diff --git a/gas/testsuite/gas/rx/abs.sm b/gas/testsuite/gas/rx/abs.sm new file mode 100644 index 00000000000..7352a55d5ad --- /dev/null +++ b/gas/testsuite/gas/rx/abs.sm @@ -0,0 +1,2 @@ + abs {reg} + abs {reg},{reg} diff --git a/gas/testsuite/gas/rx/adc.d b/gas/testsuite/gas/rx/adc.d new file mode 100644 index 00000000000..c78363e510b --- /dev/null +++ b/gas/testsuite/gas/rx/adc.d @@ -0,0 +1,40 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 20 80 adc #-128, r0 + 4: fd 74 2f 80 adc #-128, r15 + 8: fd 74 20 7f adc #127, r0 + c: fd 74 2f 7f adc #127, r15 + 10: fd 78 20 00 80 adc #0xffff8000, r0 + 15: fd 78 2f 00 80 adc #0xffff8000, r15 + 1a: fd 7c 20 00 80 00 adc #0x8000, r0 + 20: fd 7c 2f 00 80 00 adc #0x8000, r15 + 26: fd 7c 20 00 00 80 adc #0xff800000, r0 + 2c: fd 7c 2f 00 00 80 adc #0xff800000, r15 + 32: fd 7c 20 ff ff 7f adc #0x7fffff, r0 + 38: fd 7c 2f ff ff 7f adc #0x7fffff, r15 + 3e: fd 70 20 00 00 00 80 adc #0x80000000, r0 + 45: fd 70 2f 00 00 00 80 adc #0x80000000, r15 + 4c: fd 70 20 ff ff ff 7f adc #0x7fffffff, r0 + 53: fd 70 2f ff ff ff 7f adc #0x7fffffff, r15 + 5a: fc 0b 00 adc r0, r0 + 5d: fc 0b 0f adc r0, r15 + 60: fc 0b f0 adc r15, r0 + 63: fc 0b ff adc r15, r15 + 66: 06 a0 02 00 adc \[r0\]\.l, r0 + 6a: 06 a0 02 0f adc \[r0\]\.l, r15 + 6e: 06 a0 02 f0 adc \[r15\]\.l, r0 + 72: 06 a0 02 ff adc \[r15\]\.l, r15 + 76: 06 a1 02 00 3f adc 252\[r0\]\.l, r0 + 7b: 06 a1 02 0f 3f adc 252\[r0\]\.l, r15 + 80: 06 a1 02 f0 3f adc 252\[r15\]\.l, r0 + 85: 06 a1 02 ff 3f adc 252\[r15\]\.l, r15 + 8a: 06 a2 02 00 ff 3f adc 65532\[r0\]\.l, r0 + 90: 06 a2 02 0f ff 3f adc 65532\[r0\]\.l, r15 + 96: 06 a2 02 f0 ff 3f adc 65532\[r15\]\.l, r0 + 9c: 06 a2 02 ff ff 3f adc 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/adc.sm b/gas/testsuite/gas/rx/adc.sm new file mode 100644 index 00000000000..eea007a6721 --- /dev/null +++ b/gas/testsuite/gas/rx/adc.sm @@ -0,0 +1,4 @@ + adc #{imm},{reg} + adc {reg},{reg} + adc {dsp}[{reg}].L,{reg} + diff --git a/gas/testsuite/gas/rx/add.d b/gas/testsuite/gas/rx/add.d new file mode 100644 index 00000000000..1bf50059f74 --- /dev/null +++ b/gas/testsuite/gas/rx/add.d @@ -0,0 +1,132 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 62 00 add #0, r0 + 2: 62 0f add #0, r15 + 4: 62 f0 add #15, r0 + 6: 62 ff add #15, r15 + 8: 71 00 80 add #-128, r0, r0 + b: 71 ff 80 add #-128, r15, r15 + e: 71 00 7f add #127, r0, r0 + 11: 71 ff 7f add #127, r15, r15 + 14: 72 00 00 80 add #0xffff8000, r0, r0 + 18: 72 ff 00 80 add #0xffff8000, r15, r15 + 1c: 73 00 00 80 00 add #0x8000, r0, r0 + 21: 73 ff 00 80 00 add #0x8000, r15, r15 + 26: 73 00 00 00 80 add #0xff800000, r0, r0 + 2b: 73 ff 00 00 80 add #0xff800000, r15, r15 + 30: 73 00 ff ff 7f add #0x7fffff, r0, r0 + 35: 73 ff ff ff 7f add #0x7fffff, r15, r15 + 3a: 70 00 00 00 00 80 add #0x80000000, r0, r0 + 40: 70 ff 00 00 00 80 add #0x80000000, r15, r15 + 46: 70 00 ff ff ff 7f add #0x7fffffff, r0, r0 + 4c: 70 ff ff ff ff 7f add #0x7fffffff, r15, r15 + 52: 4b 00 add r0, r0 + 54: 4b 0f add r0, r15 + 56: 4b f0 add r15, r0 + 58: 4b ff add r15, r15 + 5a: 48 00 add \[r0\]\.ub, r0 + 5c: 48 0f add \[r0\]\.ub, r15 + 5e: 06 08 00 add \[r0\]\.b, r0 + 61: 06 08 0f add \[r0\]\.b, r15 + 64: 06 c8 00 add \[r0\]\.uw, r0 + 67: 06 c8 0f add \[r0\]\.uw, r15 + 6a: 06 48 00 add \[r0\]\.w, r0 + 6d: 06 48 0f add \[r0\]\.w, r15 + 70: 06 88 00 add \[r0\]\.l, r0 + 73: 06 88 0f add \[r0\]\.l, r15 + 76: 48 f0 add \[r15\]\.ub, r0 + 78: 48 ff add \[r15\]\.ub, r15 + 7a: 06 08 f0 add \[r15\]\.b, r0 + 7d: 06 08 ff add \[r15\]\.b, r15 + 80: 06 c8 f0 add \[r15\]\.uw, r0 + 83: 06 c8 ff add \[r15\]\.uw, r15 + 86: 06 48 f0 add \[r15\]\.w, r0 + 89: 06 48 ff add \[r15\]\.w, r15 + 8c: 06 88 f0 add \[r15\]\.l, r0 + 8f: 06 88 ff add \[r15\]\.l, r15 + 92: 49 00 fc add 252\[r0\]\.ub, r0 + 95: 49 0f fc add 252\[r0\]\.ub, r15 + 98: 06 09 00 fc add 252\[r0\]\.b, r0 + 9c: 06 09 0f fc add 252\[r0\]\.b, r15 + a0: 06 c9 00 7e add 252\[r0\]\.uw, r0 + a4: 06 c9 0f 7e add 252\[r0\]\.uw, r15 + a8: 06 49 00 7e add 252\[r0\]\.w, r0 + ac: 06 49 0f 7e add 252\[r0\]\.w, r15 + b0: 06 89 00 3f add 252\[r0\]\.l, r0 + b4: 06 89 0f 3f add 252\[r0\]\.l, r15 + b8: 49 f0 fc add 252\[r15\]\.ub, r0 + bb: 49 ff fc add 252\[r15\]\.ub, r15 + be: 06 09 f0 fc add 252\[r15\]\.b, r0 + c2: 06 09 ff fc add 252\[r15\]\.b, r15 + c6: 06 c9 f0 7e add 252\[r15\]\.uw, r0 + ca: 06 c9 ff 7e add 252\[r15\]\.uw, r15 + ce: 06 49 f0 7e add 252\[r15\]\.w, r0 + d2: 06 49 ff 7e add 252\[r15\]\.w, r15 + d6: 06 89 f0 3f add 252\[r15\]\.l, r0 + da: 06 89 ff 3f add 252\[r15\]\.l, r15 + de: 4a 00 fc ff add 65532\[r0\]\.ub, r0 + e2: 4a 0f fc ff add 65532\[r0\]\.ub, r15 + e6: 06 0a 00 fc ff add 65532\[r0\]\.b, r0 + eb: 06 0a 0f fc ff add 65532\[r0\]\.b, r15 + f0: 06 ca 00 fe 7f add 65532\[r0\]\.uw, r0 + f5: 06 ca 0f fe 7f add 65532\[r0\]\.uw, r15 + fa: 06 4a 00 fe 7f add 65532\[r0\]\.w, r0 + ff: 06 4a 0f fe 7f add 65532\[r0\]\.w, r15 + 104: 06 8a 00 ff 3f add 65532\[r0\]\.l, r0 + 109: 06 8a 0f ff 3f add 65532\[r0\]\.l, r15 + 10e: 4a f0 fc ff add 65532\[r15\]\.ub, r0 + 112: 4a ff fc ff add 65532\[r15\]\.ub, r15 + 116: 06 0a f0 fc ff add 65532\[r15\]\.b, r0 + 11b: 06 0a ff fc ff add 65532\[r15\]\.b, r15 + 120: 06 ca f0 fe 7f add 65532\[r15\]\.uw, r0 + 125: 06 ca ff fe 7f add 65532\[r15\]\.uw, r15 + 12a: 06 4a f0 fe 7f add 65532\[r15\]\.w, r0 + 12f: 06 4a ff fe 7f add 65532\[r15\]\.w, r15 + 134: 06 8a f0 ff 3f add 65532\[r15\]\.l, r0 + 139: 06 8a ff ff 3f add 65532\[r15\]\.l, r15 + 13e: 71 00 80 add #-128, r0, r0 + 141: 71 0f 80 add #-128, r0, r15 + 144: 71 f0 80 add #-128, r15, r0 + 147: 71 ff 80 add #-128, r15, r15 + 14a: 71 00 7f add #127, r0, r0 + 14d: 71 0f 7f add #127, r0, r15 + 150: 71 f0 7f add #127, r15, r0 + 153: 71 ff 7f add #127, r15, r15 + 156: 72 00 00 80 add #0xffff8000, r0, r0 + 15a: 72 0f 00 80 add #0xffff8000, r0, r15 + 15e: 72 f0 00 80 add #0xffff8000, r15, r0 + 162: 72 ff 00 80 add #0xffff8000, r15, r15 + 166: 73 00 00 80 00 add #0x8000, r0, r0 + 16b: 73 0f 00 80 00 add #0x8000, r0, r15 + 170: 73 f0 00 80 00 add #0x8000, r15, r0 + 175: 73 ff 00 80 00 add #0x8000, r15, r15 + 17a: 73 00 00 00 80 add #0xff800000, r0, r0 + 17f: 73 0f 00 00 80 add #0xff800000, r0, r15 + 184: 73 f0 00 00 80 add #0xff800000, r15, r0 + 189: 73 ff 00 00 80 add #0xff800000, r15, r15 + 18e: 73 00 ff ff 7f add #0x7fffff, r0, r0 + 193: 73 0f ff ff 7f add #0x7fffff, r0, r15 + 198: 73 f0 ff ff 7f add #0x7fffff, r15, r0 + 19d: 73 ff ff ff 7f add #0x7fffff, r15, r15 + 1a2: 70 00 00 00 00 80 add #0x80000000, r0, r0 + 1a8: 70 0f 00 00 00 80 add #0x80000000, r0, r15 + 1ae: 70 f0 00 00 00 80 add #0x80000000, r15, r0 + 1b4: 70 ff 00 00 00 80 add #0x80000000, r15, r15 + 1ba: 70 00 ff ff ff 7f add #0x7fffffff, r0, r0 + 1c0: 70 0f ff ff ff 7f add #0x7fffffff, r0, r15 + 1c6: 70 f0 ff ff ff 7f add #0x7fffffff, r15, r0 + 1cc: 70 ff ff ff ff 7f add #0x7fffffff, r15, r15 + 1d2: ff 20 00 add r0, r0, r0 + 1d5: ff 2f 00 add r0, r0, r15 + 1d8: ff 20 0f add r0, r15, r0 + 1db: ff 2f 0f add r0, r15, r15 + 1de: ff 20 f0 add r15, r0, r0 + 1e1: ff 2f f0 add r15, r0, r15 + 1e4: ff 20 ff add r15, r15, r0 + 1e7: ff 2f ff add r15, r15, r15 diff --git a/gas/testsuite/gas/rx/add.sm b/gas/testsuite/gas/rx/add.sm new file mode 100644 index 00000000000..27708f90e13 --- /dev/null +++ b/gas/testsuite/gas/rx/add.sm @@ -0,0 +1,8 @@ + add #{uimm4},{reg} + add #{imm},{reg} + + add {reg},{reg} + add {memx},{reg} + + add #{imm},{reg},{reg} + add {reg},{reg},{reg} diff --git a/gas/testsuite/gas/rx/and.d b/gas/testsuite/gas/rx/and.d new file mode 100644 index 00000000000..5aaafbdd8f0 --- /dev/null +++ b/gas/testsuite/gas/rx/and.d @@ -0,0 +1,100 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 64 00 and #0, r0 + 2: 64 0f and #0, r15 + 4: 64 f0 and #15, r0 + 6: 64 ff and #15, r15 + 8: 75 20 80 and #-128, r0 + b: 75 2f 80 and #-128, r15 + e: 75 20 7f and #127, r0 + 11: 75 2f 7f and #127, r15 + 14: 76 20 00 80 and #0xffff8000, r0 + 18: 76 2f 00 80 and #0xffff8000, r15 + 1c: 77 20 00 80 00 and #0x8000, r0 + 21: 77 2f 00 80 00 and #0x8000, r15 + 26: 77 20 00 00 80 and #0xff800000, r0 + 2b: 77 2f 00 00 80 and #0xff800000, r15 + 30: 77 20 ff ff 7f and #0x7fffff, r0 + 35: 77 2f ff ff 7f and #0x7fffff, r15 + 3a: 74 20 00 00 00 80 and #0x80000000, r0 + 40: 74 2f 00 00 00 80 and #0x80000000, r15 + 46: 74 20 ff ff ff 7f and #0x7fffffff, r0 + 4c: 74 2f ff ff ff 7f and #0x7fffffff, r15 + 52: 53 00 and r0, r0 + 54: 53 0f and r0, r15 + 56: 53 f0 and r15, r0 + 58: 53 ff and r15, r15 + 5a: 50 00 and \[r0\]\.ub, r0 + 5c: 50 0f and \[r0\]\.ub, r15 + 5e: 06 10 00 and \[r0\]\.b, r0 + 61: 06 10 0f and \[r0\]\.b, r15 + 64: 06 d0 00 and \[r0\]\.uw, r0 + 67: 06 d0 0f and \[r0\]\.uw, r15 + 6a: 06 50 00 and \[r0\]\.w, r0 + 6d: 06 50 0f and \[r0\]\.w, r15 + 70: 06 90 00 and \[r0\]\.l, r0 + 73: 06 90 0f and \[r0\]\.l, r15 + 76: 50 f0 and \[r15\]\.ub, r0 + 78: 50 ff and \[r15\]\.ub, r15 + 7a: 06 10 f0 and \[r15\]\.b, r0 + 7d: 06 10 ff and \[r15\]\.b, r15 + 80: 06 d0 f0 and \[r15\]\.uw, r0 + 83: 06 d0 ff and \[r15\]\.uw, r15 + 86: 06 50 f0 and \[r15\]\.w, r0 + 89: 06 50 ff and \[r15\]\.w, r15 + 8c: 06 90 f0 and \[r15\]\.l, r0 + 8f: 06 90 ff and \[r15\]\.l, r15 + 92: 51 00 fc and 252\[r0\]\.ub, r0 + 95: 51 0f fc and 252\[r0\]\.ub, r15 + 98: 06 11 00 fc and 252\[r0\]\.b, r0 + 9c: 06 11 0f fc and 252\[r0\]\.b, r15 + a0: 06 d1 00 7e and 252\[r0\]\.uw, r0 + a4: 06 d1 0f 7e and 252\[r0\]\.uw, r15 + a8: 06 51 00 7e and 252\[r0\]\.w, r0 + ac: 06 51 0f 7e and 252\[r0\]\.w, r15 + b0: 06 91 00 3f and 252\[r0\]\.l, r0 + b4: 06 91 0f 3f and 252\[r0\]\.l, r15 + b8: 51 f0 fc and 252\[r15\]\.ub, r0 + bb: 51 ff fc and 252\[r15\]\.ub, r15 + be: 06 11 f0 fc and 252\[r15\]\.b, r0 + c2: 06 11 ff fc and 252\[r15\]\.b, r15 + c6: 06 d1 f0 7e and 252\[r15\]\.uw, r0 + ca: 06 d1 ff 7e and 252\[r15\]\.uw, r15 + ce: 06 51 f0 7e and 252\[r15\]\.w, r0 + d2: 06 51 ff 7e and 252\[r15\]\.w, r15 + d6: 06 91 f0 3f and 252\[r15\]\.l, r0 + da: 06 91 ff 3f and 252\[r15\]\.l, r15 + de: 52 00 fc ff and 65532\[r0\]\.ub, r0 + e2: 52 0f fc ff and 65532\[r0\]\.ub, r15 + e6: 06 12 00 fc ff and 65532\[r0\]\.b, r0 + eb: 06 12 0f fc ff and 65532\[r0\]\.b, r15 + f0: 06 d2 00 fe 7f and 65532\[r0\]\.uw, r0 + f5: 06 d2 0f fe 7f and 65532\[r0\]\.uw, r15 + fa: 06 52 00 fe 7f and 65532\[r0\]\.w, r0 + ff: 06 52 0f fe 7f and 65532\[r0\]\.w, r15 + 104: 06 92 00 ff 3f and 65532\[r0\]\.l, r0 + 109: 06 92 0f ff 3f and 65532\[r0\]\.l, r15 + 10e: 52 f0 fc ff and 65532\[r15\]\.ub, r0 + 112: 52 ff fc ff and 65532\[r15\]\.ub, r15 + 116: 06 12 f0 fc ff and 65532\[r15\]\.b, r0 + 11b: 06 12 ff fc ff and 65532\[r15\]\.b, r15 + 120: 06 d2 f0 fe 7f and 65532\[r15\]\.uw, r0 + 125: 06 d2 ff fe 7f and 65532\[r15\]\.uw, r15 + 12a: 06 52 f0 fe 7f and 65532\[r15\]\.w, r0 + 12f: 06 52 ff fe 7f and 65532\[r15\]\.w, r15 + 134: 06 92 f0 ff 3f and 65532\[r15\]\.l, r0 + 139: 06 92 ff ff 3f and 65532\[r15\]\.l, r15 + 13e: ff 40 00 and r0, r0, r0 + 141: ff 4f 00 and r0, r0, r15 + 144: ff 40 0f and r0, r15, r0 + 147: ff 4f 0f and r0, r15, r15 + 14a: ff 40 f0 and r15, r0, r0 + 14d: ff 4f f0 and r15, r0, r15 + 150: ff 40 ff and r15, r15, r0 + 153: ff 4f ff and r15, r15, r15 diff --git a/gas/testsuite/gas/rx/and.sm b/gas/testsuite/gas/rx/and.sm new file mode 100644 index 00000000000..7c4cff23f0e --- /dev/null +++ b/gas/testsuite/gas/rx/and.sm @@ -0,0 +1,7 @@ + and #{uimm4},{reg} + and #{imm},{reg} + + and {reg},{reg} + and {memx},{reg} + + and {reg},{reg},{reg} diff --git a/gas/testsuite/gas/rx/bclr.d b/gas/testsuite/gas/rx/bclr.d new file mode 100644 index 00000000000..a5ad6319505 --- /dev/null +++ b/gas/testsuite/gas/rx/bclr.d @@ -0,0 +1,40 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: f0 08 bclr #0, \[r0\]\.b + 2: f0 f8 bclr #0, \[r15\]\.b + 4: f1 08 fc bclr #0, 252\[r0\]\.b + 7: f1 f8 fc bclr #0, 252\[r15\]\.b + a: f2 08 fc ff bclr #0, 65532\[r0\]\.b + e: f2 f8 fc ff bclr #0, 65532\[r15\]\.b + 12: f0 0f bclr #7, \[r0\]\.b + 14: f0 ff bclr #7, \[r15\]\.b + 16: f1 0f fc bclr #7, 252\[r0\]\.b + 19: f1 ff fc bclr #7, 252\[r15\]\.b + 1c: f2 0f fc ff bclr #7, 65532\[r0\]\.b + 20: f2 ff fc ff bclr #7, 65532\[r15\]\.b + 24: fc 64 00 bclr r0, \[r0\]\.b + 27: fc 64 f0 bclr r0, \[r15\]\.b + 2a: fc 65 00 fc bclr r0, 252\[r0\]\.b + 2e: fc 65 f0 fc bclr r0, 252\[r15\]\.b + 32: fc 66 00 fc ff bclr r0, 65532\[r0\]\.b + 37: fc 66 f0 fc ff bclr r0, 65532\[r15\]\.b + 3c: fc 64 0f bclr r15, \[r0\]\.b + 3f: fc 64 ff bclr r15, \[r15\]\.b + 42: fc 65 0f fc bclr r15, 252\[r0\]\.b + 46: fc 65 ff fc bclr r15, 252\[r15\]\.b + 4a: fc 66 0f fc ff bclr r15, 65532\[r0\]\.b + 4f: fc 66 ff fc ff bclr r15, 65532\[r15\]\.b + 54: 7a 00 bclr #0, r0 + 56: 7a 0f bclr #0, r15 + 58: 7b f0 bclr #31, r0 + 5a: 7b ff bclr #31, r15 + 5c: fc 67 00 bclr r0, r0 + 5f: fc 67 f0 bclr r0, r15 + 62: fc 67 0f bclr r15, r0 + 65: fc 67 ff bclr r15, r15 diff --git a/gas/testsuite/gas/rx/bclr.sm b/gas/testsuite/gas/rx/bclr.sm new file mode 100644 index 00000000000..a46a780dc00 --- /dev/null +++ b/gas/testsuite/gas/rx/bclr.sm @@ -0,0 +1,5 @@ + bclr #{uimm3}, {dsp}[{reg}].B + bclr {reg}, {dsp}[{reg}].B + + bclr #{uimm5}, {reg} + bclr {reg}, {reg} diff --git a/gas/testsuite/gas/rx/bcnd.d b/gas/testsuite/gas/rx/bcnd.d new file mode 100644 index 00000000000..77d1f775fac --- /dev/null +++ b/gas/testsuite/gas/rx/bcnd.d @@ -0,0 +1,104 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 13 beq\.s 0x3 + 1: 12 beq\.s 0xb + 2: 10 beq\.s 0xa + 2: R_RX_DIR3U_PCREL foo + 3: 1b bne\.s 0x6 + 4: 1a bne\.s 0xe + 5: 18 bne\.s 0xd + 5: R_RX_DIR3U_PCREL foo + 6: 22 80 bc\.b 0xffffff86 + 8: 22 7f bc\.b 0x87 + a: 22 00 bc\.b 0xa + b: R_RX_DIR8S_PCREL foo + c: 22 80 bc\.b 0xffffff8c + e: 22 7f bc\.b 0x8d + 10: 22 00 bc\.b 0x10 + 11: R_RX_DIR8S_PCREL foo + 12: 20 80 beq\.b 0xffffff92 + 14: 20 7f beq\.b 0x93 + 16: 20 00 beq\.b 0x16 + 17: R_RX_DIR8S_PCREL foo + 18: 20 80 beq\.b 0xffffff98 + 1a: 20 7f beq\.b 0x99 + 1c: 20 00 beq\.b 0x1c + 1d: R_RX_DIR8S_PCREL foo + 1e: 24 80 bgtu\.b 0xffffff9e + 20: 24 7f bgtu\.b 0x9f + 22: 24 00 bgtu\.b 0x22 + 23: R_RX_DIR8S_PCREL foo + 24: 26 80 bpz\.b 0xffffffa4 + 26: 26 7f bpz\.b 0xa5 + 28: 26 00 bpz\.b 0x28 + 29: R_RX_DIR8S_PCREL foo + 2a: 28 80 bge\.b 0xffffffaa + 2c: 28 7f bge\.b 0xab + 2e: 28 00 bge\.b 0x2e + 2f: R_RX_DIR8S_PCREL foo + 30: 2a 80 bgt\.b 0xffffffb0 + 32: 2a 7f bgt\.b 0xb1 + 34: 2a 00 bgt\.b 0x34 + 35: R_RX_DIR8S_PCREL foo + 36: 2c 80 bo\.b 0xffffffb6 + 38: 2c 7f bo\.b 0xb7 + 3a: 2c 00 bo\.b 0x3a + 3b: R_RX_DIR8S_PCREL foo + 3c: 23 80 bnc\.b 0xffffffbc + 3e: 23 7f bnc\.b 0xbd + 40: 23 00 bnc\.b 0x40 + 41: R_RX_DIR8S_PCREL foo + 42: 23 80 bnc\.b 0xffffffc2 + 44: 23 7f bnc\.b 0xc3 + 46: 23 00 bnc\.b 0x46 + 47: R_RX_DIR8S_PCREL foo + 48: 21 80 bne\.b 0xffffffc8 + 4a: 21 7f bne\.b 0xc9 + 4c: 21 00 bne\.b 0x4c + 4d: R_RX_DIR8S_PCREL foo + 4e: 21 80 bne\.b 0xffffffce + 50: 21 7f bne\.b 0xcf + 52: 21 00 bne\.b 0x52 + 53: R_RX_DIR8S_PCREL foo + 54: 25 80 bleu\.b 0xffffffd4 + 56: 25 7f bleu\.b 0xd5 + 58: 25 00 bleu\.b 0x58 + 59: R_RX_DIR8S_PCREL foo + 5a: 27 80 bn\.b 0xffffffda + 5c: 27 7f bn\.b 0xdb + 5e: 27 00 bn\.b 0x5e + 5f: R_RX_DIR8S_PCREL foo + 60: 29 80 blt\.b 0xffffffe0 + 62: 29 7f blt\.b 0xe1 + 64: 29 00 blt\.b 0x64 + 65: R_RX_DIR8S_PCREL foo + 66: 2b 80 ble\.b 0xffffffe6 + 68: 2b 7f ble\.b 0xe7 + 6a: 2b 00 ble\.b 0x6a + 6b: R_RX_DIR8S_PCREL foo + 6c: 2d 80 bno\.b 0xffffffec + 6e: 2d 7f bno\.b 0xed + 70: 2d 00 bno\.b 0x70 + 71: R_RX_DIR8S_PCREL foo + 72: 3a 00 80 beq\.w 0xffff8072 + 75: 3a ff 7f beq\.w 0x8074 + 78: 3a 00 00 beq\.w 0x78 + 79: R_RX_DIR16S_PCREL foo + 7b: 3b 00 80 bne\.w 0xffff807b + 7e: 3b ff 7f bne\.w 0x807d + 81: 3b 00 00 bne\.w 0x81 + 82: R_RX_DIR16S_PCREL foo + 84: 3a 00 80 beq\.w 0xffff8084 + 87: 3a ff 7f beq\.w 0x8086 + 8a: 3a fc 7f beq\.w 0x8086 + 8b: R_RX_DIR16S_PCREL foo + 8d: 3b 00 80 bne\.w 0xffff808d + 90: 3b ff 7f bne\.w 0x808f + 93: 3b fc 7f bne\.w 0x808f + 94: R_RX_DIR16S_PCREL foo diff --git a/gas/testsuite/gas/rx/bcnd.sm b/gas/testsuite/gas/rx/bcnd.sm new file mode 100644 index 00000000000..05e806fc4da --- /dev/null +++ b/gas/testsuite/gas/rx/bcnd.sm @@ -0,0 +1,5 @@ + b{eq;ne}.s {lab_s} + b{cnd}.b {lab_b} + b{eq;ne}.w {lab_w} + b{eq;ne} {lab_w} + diff --git a/gas/testsuite/gas/rx/bmcnd.d b/gas/testsuite/gas/rx/bmcnd.d new file mode 100644 index 00000000000..e0d765f84b8 --- /dev/null +++ b/gas/testsuite/gas/rx/bmcnd.d @@ -0,0 +1,296 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc e0 02 bmc #0, \[r0\]\.b + 3: fc e0 f2 bmc #0, \[r15\]\.b + 6: fc e1 02 fc bmc #0, 252\[r0\]\.b + a: fc e1 f2 fc bmc #0, 252\[r15\]\.b + e: fc e2 02 fc ff bmc #0, 65532\[r0\]\.b + 13: fc e2 f2 fc ff bmc #0, 65532\[r15\]\.b + 18: fc fc 02 bmc #7, \[r0\]\.b + 1b: fc fc f2 bmc #7, \[r15\]\.b + 1e: fc fd 02 fc bmc #7, 252\[r0\]\.b + 22: fc fd f2 fc bmc #7, 252\[r15\]\.b + 26: fc fe 02 fc ff bmc #7, 65532\[r0\]\.b + 2b: fc fe f2 fc ff bmc #7, 65532\[r15\]\.b + 30: fc e0 02 bmc #0, \[r0\]\.b + 33: fc e0 f2 bmc #0, \[r15\]\.b + 36: fc e1 02 fc bmc #0, 252\[r0\]\.b + 3a: fc e1 f2 fc bmc #0, 252\[r15\]\.b + 3e: fc e2 02 fc ff bmc #0, 65532\[r0\]\.b + 43: fc e2 f2 fc ff bmc #0, 65532\[r15\]\.b + 48: fc fc 02 bmc #7, \[r0\]\.b + 4b: fc fc f2 bmc #7, \[r15\]\.b + 4e: fc fd 02 fc bmc #7, 252\[r0\]\.b + 52: fc fd f2 fc bmc #7, 252\[r15\]\.b + 56: fc fe 02 fc ff bmc #7, 65532\[r0\]\.b + 5b: fc fe f2 fc ff bmc #7, 65532\[r15\]\.b + 60: fc e0 00 bmeq #0, \[r0\]\.b + 63: fc e0 f0 bmeq #0, \[r15\]\.b + 66: fc e1 00 fc bmeq #0, 252\[r0\]\.b + 6a: fc e1 f0 fc bmeq #0, 252\[r15\]\.b + 6e: fc e2 00 fc ff bmeq #0, 65532\[r0\]\.b + 73: fc e2 f0 fc ff bmeq #0, 65532\[r15\]\.b + 78: fc fc 00 bmeq #7, \[r0\]\.b + 7b: fc fc f0 bmeq #7, \[r15\]\.b + 7e: fc fd 00 fc bmeq #7, 252\[r0\]\.b + 82: fc fd f0 fc bmeq #7, 252\[r15\]\.b + 86: fc fe 00 fc ff bmeq #7, 65532\[r0\]\.b + 8b: fc fe f0 fc ff bmeq #7, 65532\[r15\]\.b + 90: fc e0 00 bmeq #0, \[r0\]\.b + 93: fc e0 f0 bmeq #0, \[r15\]\.b + 96: fc e1 00 fc bmeq #0, 252\[r0\]\.b + 9a: fc e1 f0 fc bmeq #0, 252\[r15\]\.b + 9e: fc e2 00 fc ff bmeq #0, 65532\[r0\]\.b + a3: fc e2 f0 fc ff bmeq #0, 65532\[r15\]\.b + a8: fc fc 00 bmeq #7, \[r0\]\.b + ab: fc fc f0 bmeq #7, \[r15\]\.b + ae: fc fd 00 fc bmeq #7, 252\[r0\]\.b + b2: fc fd f0 fc bmeq #7, 252\[r15\]\.b + b6: fc fe 00 fc ff bmeq #7, 65532\[r0\]\.b + bb: fc fe f0 fc ff bmeq #7, 65532\[r15\]\.b + c0: fc e0 04 bmgtu #0, \[r0\]\.b + c3: fc e0 f4 bmgtu #0, \[r15\]\.b + c6: fc e1 04 fc bmgtu #0, 252\[r0\]\.b + ca: fc e1 f4 fc bmgtu #0, 252\[r15\]\.b + ce: fc e2 04 fc ff bmgtu #0, 65532\[r0\]\.b + d3: fc e2 f4 fc ff bmgtu #0, 65532\[r15\]\.b + d8: fc fc 04 bmgtu #7, \[r0\]\.b + db: fc fc f4 bmgtu #7, \[r15\]\.b + de: fc fd 04 fc bmgtu #7, 252\[r0\]\.b + e2: fc fd f4 fc bmgtu #7, 252\[r15\]\.b + e6: fc fe 04 fc ff bmgtu #7, 65532\[r0\]\.b + eb: fc fe f4 fc ff bmgtu #7, 65532\[r15\]\.b + f0: fc e0 06 bmpz #0, \[r0\]\.b + f3: fc e0 f6 bmpz #0, \[r15\]\.b + f6: fc e1 06 fc bmpz #0, 252\[r0\]\.b + fa: fc e1 f6 fc bmpz #0, 252\[r15\]\.b + fe: fc e2 06 fc ff bmpz #0, 65532\[r0\]\.b + 103: fc e2 f6 fc ff bmpz #0, 65532\[r15\]\.b + 108: fc fc 06 bmpz #7, \[r0\]\.b + 10b: fc fc f6 bmpz #7, \[r15\]\.b + 10e: fc fd 06 fc bmpz #7, 252\[r0\]\.b + 112: fc fd f6 fc bmpz #7, 252\[r15\]\.b + 116: fc fe 06 fc ff bmpz #7, 65532\[r0\]\.b + 11b: fc fe f6 fc ff bmpz #7, 65532\[r15\]\.b + 120: fc e0 08 bmge #0, \[r0\]\.b + 123: fc e0 f8 bmge #0, \[r15\]\.b + 126: fc e1 08 fc bmge #0, 252\[r0\]\.b + 12a: fc e1 f8 fc bmge #0, 252\[r15\]\.b + 12e: fc e2 08 fc ff bmge #0, 65532\[r0\]\.b + 133: fc e2 f8 fc ff bmge #0, 65532\[r15\]\.b + 138: fc fc 08 bmge #7, \[r0\]\.b + 13b: fc fc f8 bmge #7, \[r15\]\.b + 13e: fc fd 08 fc bmge #7, 252\[r0\]\.b + 142: fc fd f8 fc bmge #7, 252\[r15\]\.b + 146: fc fe 08 fc ff bmge #7, 65532\[r0\]\.b + 14b: fc fe f8 fc ff bmge #7, 65532\[r15\]\.b + 150: fc e0 0a bmgt #0, \[r0\]\.b + 153: fc e0 fa bmgt #0, \[r15\]\.b + 156: fc e1 0a fc bmgt #0, 252\[r0\]\.b + 15a: fc e1 fa fc bmgt #0, 252\[r15\]\.b + 15e: fc e2 0a fc ff bmgt #0, 65532\[r0\]\.b + 163: fc e2 fa fc ff bmgt #0, 65532\[r15\]\.b + 168: fc fc 0a bmgt #7, \[r0\]\.b + 16b: fc fc fa bmgt #7, \[r15\]\.b + 16e: fc fd 0a fc bmgt #7, 252\[r0\]\.b + 172: fc fd fa fc bmgt #7, 252\[r15\]\.b + 176: fc fe 0a fc ff bmgt #7, 65532\[r0\]\.b + 17b: fc fe fa fc ff bmgt #7, 65532\[r15\]\.b + 180: fc e0 0c bmo #0, \[r0\]\.b + 183: fc e0 fc bmo #0, \[r15\]\.b + 186: fc e1 0c fc bmo #0, 252\[r0\]\.b + 18a: fc e1 fc fc bmo #0, 252\[r15\]\.b + 18e: fc e2 0c fc ff bmo #0, 65532\[r0\]\.b + 193: fc e2 fc fc ff bmo #0, 65532\[r15\]\.b + 198: fc fc 0c bmo #7, \[r0\]\.b + 19b: fc fc fc bmo #7, \[r15\]\.b + 19e: fc fd 0c fc bmo #7, 252\[r0\]\.b + 1a2: fc fd fc fc bmo #7, 252\[r15\]\.b + 1a6: fc fe 0c fc ff bmo #7, 65532\[r0\]\.b + 1ab: fc fe fc fc ff bmo #7, 65532\[r15\]\.b + 1b0: fc e0 03 bmnc #0, \[r0\]\.b + 1b3: fc e0 f3 bmnc #0, \[r15\]\.b + 1b6: fc e1 03 fc bmnc #0, 252\[r0\]\.b + 1ba: fc e1 f3 fc bmnc #0, 252\[r15\]\.b + 1be: fc e2 03 fc ff bmnc #0, 65532\[r0\]\.b + 1c3: fc e2 f3 fc ff bmnc #0, 65532\[r15\]\.b + 1c8: fc fc 03 bmnc #7, \[r0\]\.b + 1cb: fc fc f3 bmnc #7, \[r15\]\.b + 1ce: fc fd 03 fc bmnc #7, 252\[r0\]\.b + 1d2: fc fd f3 fc bmnc #7, 252\[r15\]\.b + 1d6: fc fe 03 fc ff bmnc #7, 65532\[r0\]\.b + 1db: fc fe f3 fc ff bmnc #7, 65532\[r15\]\.b + 1e0: fc e0 03 bmnc #0, \[r0\]\.b + 1e3: fc e0 f3 bmnc #0, \[r15\]\.b + 1e6: fc e1 03 fc bmnc #0, 252\[r0\]\.b + 1ea: fc e1 f3 fc bmnc #0, 252\[r15\]\.b + 1ee: fc e2 03 fc ff bmnc #0, 65532\[r0\]\.b + 1f3: fc e2 f3 fc ff bmnc #0, 65532\[r15\]\.b + 1f8: fc fc 03 bmnc #7, \[r0\]\.b + 1fb: fc fc f3 bmnc #7, \[r15\]\.b + 1fe: fc fd 03 fc bmnc #7, 252\[r0\]\.b + 202: fc fd f3 fc bmnc #7, 252\[r15\]\.b + 206: fc fe 03 fc ff bmnc #7, 65532\[r0\]\.b + 20b: fc fe f3 fc ff bmnc #7, 65532\[r15\]\.b + 210: fc e0 01 bmne #0, \[r0\]\.b + 213: fc e0 f1 bmne #0, \[r15\]\.b + 216: fc e1 01 fc bmne #0, 252\[r0\]\.b + 21a: fc e1 f1 fc bmne #0, 252\[r15\]\.b + 21e: fc e2 01 fc ff bmne #0, 65532\[r0\]\.b + 223: fc e2 f1 fc ff bmne #0, 65532\[r15\]\.b + 228: fc fc 01 bmne #7, \[r0\]\.b + 22b: fc fc f1 bmne #7, \[r15\]\.b + 22e: fc fd 01 fc bmne #7, 252\[r0\]\.b + 232: fc fd f1 fc bmne #7, 252\[r15\]\.b + 236: fc fe 01 fc ff bmne #7, 65532\[r0\]\.b + 23b: fc fe f1 fc ff bmne #7, 65532\[r15\]\.b + 240: fc e0 01 bmne #0, \[r0\]\.b + 243: fc e0 f1 bmne #0, \[r15\]\.b + 246: fc e1 01 fc bmne #0, 252\[r0\]\.b + 24a: fc e1 f1 fc bmne #0, 252\[r15\]\.b + 24e: fc e2 01 fc ff bmne #0, 65532\[r0\]\.b + 253: fc e2 f1 fc ff bmne #0, 65532\[r15\]\.b + 258: fc fc 01 bmne #7, \[r0\]\.b + 25b: fc fc f1 bmne #7, \[r15\]\.b + 25e: fc fd 01 fc bmne #7, 252\[r0\]\.b + 262: fc fd f1 fc bmne #7, 252\[r15\]\.b + 266: fc fe 01 fc ff bmne #7, 65532\[r0\]\.b + 26b: fc fe f1 fc ff bmne #7, 65532\[r15\]\.b + 270: fc e0 05 bmleu #0, \[r0\]\.b + 273: fc e0 f5 bmleu #0, \[r15\]\.b + 276: fc e1 05 fc bmleu #0, 252\[r0\]\.b + 27a: fc e1 f5 fc bmleu #0, 252\[r15\]\.b + 27e: fc e2 05 fc ff bmleu #0, 65532\[r0\]\.b + 283: fc e2 f5 fc ff bmleu #0, 65532\[r15\]\.b + 288: fc fc 05 bmleu #7, \[r0\]\.b + 28b: fc fc f5 bmleu #7, \[r15\]\.b + 28e: fc fd 05 fc bmleu #7, 252\[r0\]\.b + 292: fc fd f5 fc bmleu #7, 252\[r15\]\.b + 296: fc fe 05 fc ff bmleu #7, 65532\[r0\]\.b + 29b: fc fe f5 fc ff bmleu #7, 65532\[r15\]\.b + 2a0: fc e0 07 bmn #0, \[r0\]\.b + 2a3: fc e0 f7 bmn #0, \[r15\]\.b + 2a6: fc e1 07 fc bmn #0, 252\[r0\]\.b + 2aa: fc e1 f7 fc bmn #0, 252\[r15\]\.b + 2ae: fc e2 07 fc ff bmn #0, 65532\[r0\]\.b + 2b3: fc e2 f7 fc ff bmn #0, 65532\[r15\]\.b + 2b8: fc fc 07 bmn #7, \[r0\]\.b + 2bb: fc fc f7 bmn #7, \[r15\]\.b + 2be: fc fd 07 fc bmn #7, 252\[r0\]\.b + 2c2: fc fd f7 fc bmn #7, 252\[r15\]\.b + 2c6: fc fe 07 fc ff bmn #7, 65532\[r0\]\.b + 2cb: fc fe f7 fc ff bmn #7, 65532\[r15\]\.b + 2d0: fc e0 09 bmlt #0, \[r0\]\.b + 2d3: fc e0 f9 bmlt #0, \[r15\]\.b + 2d6: fc e1 09 fc bmlt #0, 252\[r0\]\.b + 2da: fc e1 f9 fc bmlt #0, 252\[r15\]\.b + 2de: fc e2 09 fc ff bmlt #0, 65532\[r0\]\.b + 2e3: fc e2 f9 fc ff bmlt #0, 65532\[r15\]\.b + 2e8: fc fc 09 bmlt #7, \[r0\]\.b + 2eb: fc fc f9 bmlt #7, \[r15\]\.b + 2ee: fc fd 09 fc bmlt #7, 252\[r0\]\.b + 2f2: fc fd f9 fc bmlt #7, 252\[r15\]\.b + 2f6: fc fe 09 fc ff bmlt #7, 65532\[r0\]\.b + 2fb: fc fe f9 fc ff bmlt #7, 65532\[r15\]\.b + 300: fc e0 0b bmle #0, \[r0\]\.b + 303: fc e0 fb bmle #0, \[r15\]\.b + 306: fc e1 0b fc bmle #0, 252\[r0\]\.b + 30a: fc e1 fb fc bmle #0, 252\[r15\]\.b + 30e: fc e2 0b fc ff bmle #0, 65532\[r0\]\.b + 313: fc e2 fb fc ff bmle #0, 65532\[r15\]\.b + 318: fc fc 0b bmle #7, \[r0\]\.b + 31b: fc fc fb bmle #7, \[r15\]\.b + 31e: fc fd 0b fc bmle #7, 252\[r0\]\.b + 322: fc fd fb fc bmle #7, 252\[r15\]\.b + 326: fc fe 0b fc ff bmle #7, 65532\[r0\]\.b + 32b: fc fe fb fc ff bmle #7, 65532\[r15\]\.b + 330: fc e0 0d bmno #0, \[r0\]\.b + 333: fc e0 fd bmno #0, \[r15\]\.b + 336: fc e1 0d fc bmno #0, 252\[r0\]\.b + 33a: fc e1 fd fc bmno #0, 252\[r15\]\.b + 33e: fc e2 0d fc ff bmno #0, 65532\[r0\]\.b + 343: fc e2 fd fc ff bmno #0, 65532\[r15\]\.b + 348: fc fc 0d bmno #7, \[r0\]\.b + 34b: fc fc fd bmno #7, \[r15\]\.b + 34e: fc fd 0d fc bmno #7, 252\[r0\]\.b + 352: fc fd fd fc bmno #7, 252\[r15\]\.b + 356: fc fe 0d fc ff bmno #7, 65532\[r0\]\.b + 35b: fc fe fd fc ff bmno #7, 65532\[r15\]\.b + 360: fd e0 20 bmc #0, r0 + 363: fd e0 2f bmc #0, r15 + 366: fd ff 20 bmc #31, r0 + 369: fd ff 2f bmc #31, r15 + 36c: fd e0 20 bmc #0, r0 + 36f: fd e0 2f bmc #0, r15 + 372: fd ff 20 bmc #31, r0 + 375: fd ff 2f bmc #31, r15 + 378: fd e0 00 bmeq #0, r0 + 37b: fd e0 0f bmeq #0, r15 + 37e: fd ff 00 bmeq #31, r0 + 381: fd ff 0f bmeq #31, r15 + 384: fd e0 00 bmeq #0, r0 + 387: fd e0 0f bmeq #0, r15 + 38a: fd ff 00 bmeq #31, r0 + 38d: fd ff 0f bmeq #31, r15 + 390: fd e0 40 bmgtu #0, r0 + 393: fd e0 4f bmgtu #0, r15 + 396: fd ff 40 bmgtu #31, r0 + 399: fd ff 4f bmgtu #31, r15 + 39c: fd e0 60 bmpz #0, r0 + 39f: fd e0 6f bmpz #0, r15 + 3a2: fd ff 60 bmpz #31, r0 + 3a5: fd ff 6f bmpz #31, r15 + 3a8: fd e0 80 bmge #0, r0 + 3ab: fd e0 8f bmge #0, r15 + 3ae: fd ff 80 bmge #31, r0 + 3b1: fd ff 8f bmge #31, r15 + 3b4: fd e0 a0 bmgt #0, r0 + 3b7: fd e0 af bmgt #0, r15 + 3ba: fd ff a0 bmgt #31, r0 + 3bd: fd ff af bmgt #31, r15 + 3c0: fd e0 c0 bmo #0, r0 + 3c3: fd e0 cf bmo #0, r15 + 3c6: fd ff c0 bmo #31, r0 + 3c9: fd ff cf bmo #31, r15 + 3cc: fd e0 30 bmnc #0, r0 + 3cf: fd e0 3f bmnc #0, r15 + 3d2: fd ff 30 bmnc #31, r0 + 3d5: fd ff 3f bmnc #31, r15 + 3d8: fd e0 30 bmnc #0, r0 + 3db: fd e0 3f bmnc #0, r15 + 3de: fd ff 30 bmnc #31, r0 + 3e1: fd ff 3f bmnc #31, r15 + 3e4: fd e0 10 bmne #0, r0 + 3e7: fd e0 1f bmne #0, r15 + 3ea: fd ff 10 bmne #31, r0 + 3ed: fd ff 1f bmne #31, r15 + 3f0: fd e0 10 bmne #0, r0 + 3f3: fd e0 1f bmne #0, r15 + 3f6: fd ff 10 bmne #31, r0 + 3f9: fd ff 1f bmne #31, r15 + 3fc: fd e0 50 bmleu #0, r0 + 3ff: fd e0 5f bmleu #0, r15 + 402: fd ff 50 bmleu #31, r0 + 405: fd ff 5f bmleu #31, r15 + 408: fd e0 70 bmn #0, r0 + 40b: fd e0 7f bmn #0, r15 + 40e: fd ff 70 bmn #31, r0 + 411: fd ff 7f bmn #31, r15 + 414: fd e0 90 bmlt #0, r0 + 417: fd e0 9f bmlt #0, r15 + 41a: fd ff 90 bmlt #31, r0 + 41d: fd ff 9f bmlt #31, r15 + 420: fd e0 b0 bmle #0, r0 + 423: fd e0 bf bmle #0, r15 + 426: fd ff b0 bmle #31, r0 + 429: fd ff bf bmle #31, r15 + 42c: fd e0 d0 bmno #0, r0 + 42f: fd e0 df bmno #0, r15 + 432: fd ff d0 bmno #31, r0 + 435: fd ff df bmno #31, r15 diff --git a/gas/testsuite/gas/rx/bmcnd.sm b/gas/testsuite/gas/rx/bmcnd.sm new file mode 100644 index 00000000000..7ec587bd4c2 --- /dev/null +++ b/gas/testsuite/gas/rx/bmcnd.sm @@ -0,0 +1,2 @@ + bm{cnd} #{uimm3}, {dsp}[{reg}].B + bm{cnd} #{uimm5}, {reg} diff --git a/gas/testsuite/gas/rx/bnot.d b/gas/testsuite/gas/rx/bnot.d new file mode 100644 index 00000000000..452c70189c5 --- /dev/null +++ b/gas/testsuite/gas/rx/bnot.d @@ -0,0 +1,40 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc e0 0f bnot #0, \[r0\]\.b + 3: fc e0 ff bnot #0, \[r15\]\.b + 6: fc e1 0f fc bnot #0, 252\[r0\]\.b + a: fc e1 ff fc bnot #0, 252\[r15\]\.b + e: fc e2 0f fc ff bnot #0, 65532\[r0\]\.b + 13: fc e2 ff fc ff bnot #0, 65532\[r15\]\.b + 18: fc fc 0f bnot #7, \[r0\]\.b + 1b: fc fc ff bnot #7, \[r15\]\.b + 1e: fc fd 0f fc bnot #7, 252\[r0\]\.b + 22: fc fd ff fc bnot #7, 252\[r15\]\.b + 26: fc fe 0f fc ff bnot #7, 65532\[r0\]\.b + 2b: fc fe ff fc ff bnot #7, 65532\[r15\]\.b + 30: fc 6c 00 bnot r0, \[r0\]\.b + 33: fc 6c f0 bnot r0, \[r15\]\.b + 36: fc 6d 00 fc bnot r0, 252\[r0\]\.b + 3a: fc 6d f0 fc bnot r0, 252\[r15\]\.b + 3e: fc 6e 00 fc ff bnot r0, 65532\[r0\]\.b + 43: fc 6e f0 fc ff bnot r0, 65532\[r15\]\.b + 48: fc 6c 0f bnot r15, \[r0\]\.b + 4b: fc 6c ff bnot r15, \[r15\]\.b + 4e: fc 6d 0f fc bnot r15, 252\[r0\]\.b + 52: fc 6d ff fc bnot r15, 252\[r15\]\.b + 56: fc 6e 0f fc ff bnot r15, 65532\[r0\]\.b + 5b: fc 6e ff fc ff bnot r15, 65532\[r15\]\.b + 60: fd e0 f0 bnot #0, r0 + 63: fd e0 ff bnot #0, r15 + 66: fd ff f0 bnot #31, r0 + 69: fd ff ff bnot #31, r15 + 6c: fc 6f 00 bnot r0, r0 + 6f: fc 6f f0 bnot r0, r15 + 72: fc 6f 0f bnot r15, r0 + 75: fc 6f ff bnot r15, r15 diff --git a/gas/testsuite/gas/rx/bnot.sm b/gas/testsuite/gas/rx/bnot.sm new file mode 100644 index 00000000000..dd08a7c2102 --- /dev/null +++ b/gas/testsuite/gas/rx/bnot.sm @@ -0,0 +1,5 @@ + bnot #{uimm3}, {dsp}[{reg}].B + bnot {reg}, {dsp}[{reg}].B + + bnot #{uimm5}, {reg} + bnot {reg}, {reg} diff --git a/gas/testsuite/gas/rx/bra.d b/gas/testsuite/gas/rx/bra.d new file mode 100644 index 00000000000..be8def4c793 --- /dev/null +++ b/gas/testsuite/gas/rx/bra.d @@ -0,0 +1,30 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 0b bra\.s 0x3 + 1: 0a bra\.s 0xb + 2: 08 bra\.s 0xa + 2: R_RX_DIR3U_PCREL foo + 3: 2e 80 bra\.b 0xffffff83 + 5: 2e 7f bra\.b 0x84 + 7: 2e 00 bra\.b 0x7 + 8: R_RX_DIR8S_PCREL foo + 9: 38 00 80 bra\.w 0xffff8009 + c: 38 ff 7f bra\.w 0x800b + f: 38 00 00 bra\.w 0xf + 10: R_RX_DIR16S_PCREL foo + 12: 04 00 00 80 bra\.a 0xff800012 + 16: 04 ff ff 7f bra\.a 0x800015 + 1a: 04 00 00 00 bra\.a 0x1a + 1b: R_RX_DIR24S_PCREL foo + 1e: 04 00 00 80 bra\.a 0xff80001e + 22: 04 ff ff 7f bra\.a 0x800021 + 26: 04 fb ff 7f bra\.a 0x800021 + 27: R_RX_DIR24S_PCREL foo + 2a: 7f 40 bra\.l r0 + 2c: 7f 4f bra\.l r15 diff --git a/gas/testsuite/gas/rx/bra.sm b/gas/testsuite/gas/rx/bra.sm new file mode 100644 index 00000000000..23b6445495b --- /dev/null +++ b/gas/testsuite/gas/rx/bra.sm @@ -0,0 +1,6 @@ + bra.s {lab_s} + bra.b {lab_b} + bra.w {lab_w} + bra.a {lab_a} + bra {lab_a} + bra.l {reg} diff --git a/gas/testsuite/gas/rx/brk.d b/gas/testsuite/gas/rx/brk.d new file mode 100644 index 00000000000..fe895f98285 --- /dev/null +++ b/gas/testsuite/gas/rx/brk.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 brk + 1: 03 nop diff --git a/gas/testsuite/gas/rx/brk.sm b/gas/testsuite/gas/rx/brk.sm new file mode 100644 index 00000000000..c1701118c7a --- /dev/null +++ b/gas/testsuite/gas/rx/brk.sm @@ -0,0 +1,2 @@ + brk + nop diff --git a/gas/testsuite/gas/rx/bset.d b/gas/testsuite/gas/rx/bset.d new file mode 100644 index 00000000000..4f540e71bb6 --- /dev/null +++ b/gas/testsuite/gas/rx/bset.d @@ -0,0 +1,40 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: f0 00 bset #0, \[r0\]\.b + 2: f0 f0 bset #0, \[r15\]\.b + 4: f1 00 fc bset #0, 252\[r0\]\.b + 7: f1 f0 fc bset #0, 252\[r15\]\.b + a: f2 00 fc ff bset #0, 65532\[r0\]\.b + e: f2 f0 fc ff bset #0, 65532\[r15\]\.b + 12: f0 07 bset #7, \[r0\]\.b + 14: f0 f7 bset #7, \[r15\]\.b + 16: f1 07 fc bset #7, 252\[r0\]\.b + 19: f1 f7 fc bset #7, 252\[r15\]\.b + 1c: f2 07 fc ff bset #7, 65532\[r0\]\.b + 20: f2 f7 fc ff bset #7, 65532\[r15\]\.b + 24: fc 60 00 bset r0, \[r0\]\.b + 27: fc 60 f0 bset r0, \[r15\]\.b + 2a: fc 61 00 fc bset r0, 252\[r0\]\.b + 2e: fc 61 f0 fc bset r0, 252\[r15\]\.b + 32: fc 62 00 fc ff bset r0, 65532\[r0\]\.b + 37: fc 62 f0 fc ff bset r0, 65532\[r15\]\.b + 3c: fc 60 0f bset r15, \[r0\]\.b + 3f: fc 60 ff bset r15, \[r15\]\.b + 42: fc 61 0f fc bset r15, 252\[r0\]\.b + 46: fc 61 ff fc bset r15, 252\[r15\]\.b + 4a: fc 62 0f fc ff bset r15, 65532\[r0\]\.b + 4f: fc 62 ff fc ff bset r15, 65532\[r15\]\.b + 54: 78 00 bset #0, r0 + 56: 78 0f bset #0, r15 + 58: 79 f0 bset #31, r0 + 5a: 79 ff bset #31, r15 + 5c: fc 63 00 bset r0, r0 + 5f: fc 63 f0 bset r0, r15 + 62: fc 63 0f bset r15, r0 + 65: fc 63 ff bset r15, r15 diff --git a/gas/testsuite/gas/rx/bset.sm b/gas/testsuite/gas/rx/bset.sm new file mode 100644 index 00000000000..a76626e237d --- /dev/null +++ b/gas/testsuite/gas/rx/bset.sm @@ -0,0 +1,5 @@ + bset #{uimm3}, {dsp}[{reg}].B + bset {reg}, {dsp}[{reg}].B + + bset #{uimm5}, {reg} + bset {reg}, {reg} diff --git a/gas/testsuite/gas/rx/bsr.d b/gas/testsuite/gas/rx/bsr.d new file mode 100644 index 00000000000..23a27c7ff17 --- /dev/null +++ b/gas/testsuite/gas/rx/bsr.d @@ -0,0 +1,18 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 39 00 80 bsr\.w 0xffff8000 + 3: 39 ff 7f bsr\.w 0x8002 + 6: 39 00 00 bsr\.w 0x6 + 7: R_RX_DIR16S_PCREL foo + 9: 05 00 00 80 bsr\.a 0xff800009 + d: 05 ff ff 7f bsr\.a 0x80000c + 11: 05 00 00 00 bsr\.a 0x11 + 12: R_RX_DIR24S_PCREL foo + 15: 7f 50 bsr\.l r0 + 17: 7f 5f bsr\.l r15 diff --git a/gas/testsuite/gas/rx/bsr.sm b/gas/testsuite/gas/rx/bsr.sm new file mode 100644 index 00000000000..bce74d8c94e --- /dev/null +++ b/gas/testsuite/gas/rx/bsr.sm @@ -0,0 +1,3 @@ + bsr.w {lab_w} + bsr.a {lab_a} + bsr.l {reg} diff --git a/gas/testsuite/gas/rx/btst.d b/gas/testsuite/gas/rx/btst.d new file mode 100644 index 00000000000..8cb45d34dbf --- /dev/null +++ b/gas/testsuite/gas/rx/btst.d @@ -0,0 +1,40 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: f4 00 btst #0, \[r0\]\.b + 2: f4 f0 btst #0, \[r15\]\.b + 4: f5 00 fc btst #0, 252\[r0\]\.b + 7: f5 f0 fc btst #0, 252\[r15\]\.b + a: f6 00 fc ff btst #0, 65532\[r0\]\.b + e: f6 f0 fc ff btst #0, 65532\[r15\]\.b + 12: f4 07 btst #7, \[r0\]\.b + 14: f4 f7 btst #7, \[r15\]\.b + 16: f5 07 fc btst #7, 252\[r0\]\.b + 19: f5 f7 fc btst #7, 252\[r15\]\.b + 1c: f6 07 fc ff btst #7, 65532\[r0\]\.b + 20: f6 f7 fc ff btst #7, 65532\[r15\]\.b + 24: fc 68 00 btst r0, \[r0\]\.b + 27: fc 68 f0 btst r0, \[r15\]\.b + 2a: fc 69 00 fc btst r0, 252\[r0\]\.b + 2e: fc 69 f0 fc btst r0, 252\[r15\]\.b + 32: fc 6a 00 fc ff btst r0, 65532\[r0\]\.b + 37: fc 6a f0 fc ff btst r0, 65532\[r15\]\.b + 3c: fc 68 0f btst r15, \[r0\]\.b + 3f: fc 68 ff btst r15, \[r15\]\.b + 42: fc 69 0f fc btst r15, 252\[r0\]\.b + 46: fc 69 ff fc btst r15, 252\[r15\]\.b + 4a: fc 6a 0f fc ff btst r15, 65532\[r0\]\.b + 4f: fc 6a ff fc ff btst r15, 65532\[r15\]\.b + 54: 7c 00 btst #0, r0 + 56: 7c 0f btst #0, r15 + 58: 7d f0 btst #31, r0 + 5a: 7d ff btst #31, r15 + 5c: fc 6b 00 btst r0, r0 + 5f: fc 6b f0 btst r0, r15 + 62: fc 6b 0f btst r15, r0 + 65: fc 6b ff btst r15, r15 diff --git a/gas/testsuite/gas/rx/btst.sm b/gas/testsuite/gas/rx/btst.sm new file mode 100644 index 00000000000..5166d31e943 --- /dev/null +++ b/gas/testsuite/gas/rx/btst.sm @@ -0,0 +1,5 @@ + btst #{uimm3}, {dsp}[{reg}].B + btst {reg}, {dsp}[{reg}].B + + btst #{uimm5}, {reg} + btst {reg}, {reg} diff --git a/gas/testsuite/gas/rx/clrpsw.d b/gas/testsuite/gas/rx/clrpsw.d new file mode 100644 index 00000000000..c82b440ee94 --- /dev/null +++ b/gas/testsuite/gas/rx/clrpsw.d @@ -0,0 +1,14 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f b9 clrpsw u + 2: 7f b8 clrpsw i + 4: 7f b3 clrpsw o + 6: 7f b2 clrpsw s + 8: 7f b1 clrpsw z + a: 7f b0 clrpsw c diff --git a/gas/testsuite/gas/rx/clrpsw.sm b/gas/testsuite/gas/rx/clrpsw.sm new file mode 100644 index 00000000000..69ed4e6f0d6 --- /dev/null +++ b/gas/testsuite/gas/rx/clrpsw.sm @@ -0,0 +1 @@ + clrpsw {pswf} diff --git a/gas/testsuite/gas/rx/cmp.d b/gas/testsuite/gas/rx/cmp.d new file mode 100644 index 00000000000..2b8ad6d514d --- /dev/null +++ b/gas/testsuite/gas/rx/cmp.d @@ -0,0 +1,96 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 61 00 cmp #0, r0 + 2: 61 0f cmp #0, r15 + 4: 61 f0 cmp #15, r0 + 6: 61 ff cmp #15, r15 + 8: 61 00 cmp #0, r0 + a: 61 0f cmp #0, r15 + c: 75 50 ff cmp #255, r0 + f: 75 5f ff cmp #255, r15 + 12: 75 00 80 cmp #-128, r0 + 15: 75 0f 80 cmp #-128, r15 + 18: 75 50 7f cmp #127, r0 + 1b: 75 5f 7f cmp #127, r15 + 1e: 76 00 00 80 cmp #0xffff8000, r0 + 22: 76 0f 00 80 cmp #0xffff8000, r15 + 26: 77 00 00 80 00 cmp #0x8000, r0 + 2b: 77 0f 00 80 00 cmp #0x8000, r15 + 30: 77 00 00 00 80 cmp #0xff800000, r0 + 35: 77 0f 00 00 80 cmp #0xff800000, r15 + 3a: 77 00 ff ff 7f cmp #0x7fffff, r0 + 3f: 77 0f ff ff 7f cmp #0x7fffff, r15 + 44: 74 00 00 00 00 80 cmp #0x80000000, r0 + 4a: 74 0f 00 00 00 80 cmp #0x80000000, r15 + 50: 74 00 ff ff ff 7f cmp #0x7fffffff, r0 + 56: 74 0f ff ff ff 7f cmp #0x7fffffff, r15 + 5c: 47 00 cmp r0, r0 + 5e: 47 0f cmp r0, r15 + 60: 47 f0 cmp r15, r0 + 62: 47 ff cmp r15, r15 + 64: 44 00 cmp \[r0\]\.ub, r0 + 66: 44 0f cmp \[r0\]\.ub, r15 + 68: 06 04 00 cmp \[r0\]\.b, r0 + 6b: 06 04 0f cmp \[r0\]\.b, r15 + 6e: 06 c4 00 cmp \[r0\]\.uw, r0 + 71: 06 c4 0f cmp \[r0\]\.uw, r15 + 74: 06 44 00 cmp \[r0\]\.w, r0 + 77: 06 44 0f cmp \[r0\]\.w, r15 + 7a: 06 84 00 cmp \[r0\]\.l, r0 + 7d: 06 84 0f cmp \[r0\]\.l, r15 + 80: 44 f0 cmp \[r15\]\.ub, r0 + 82: 44 ff cmp \[r15\]\.ub, r15 + 84: 06 04 f0 cmp \[r15\]\.b, r0 + 87: 06 04 ff cmp \[r15\]\.b, r15 + 8a: 06 c4 f0 cmp \[r15\]\.uw, r0 + 8d: 06 c4 ff cmp \[r15\]\.uw, r15 + 90: 06 44 f0 cmp \[r15\]\.w, r0 + 93: 06 44 ff cmp \[r15\]\.w, r15 + 96: 06 84 f0 cmp \[r15\]\.l, r0 + 99: 06 84 ff cmp \[r15\]\.l, r15 + 9c: 45 00 fc cmp 252\[r0\]\.ub, r0 + 9f: 45 0f fc cmp 252\[r0\]\.ub, r15 + a2: 06 05 00 fc cmp 252\[r0\]\.b, r0 + a6: 06 05 0f fc cmp 252\[r0\]\.b, r15 + aa: 06 c5 00 7e cmp 252\[r0\]\.uw, r0 + ae: 06 c5 0f 7e cmp 252\[r0\]\.uw, r15 + b2: 06 45 00 7e cmp 252\[r0\]\.w, r0 + b6: 06 45 0f 7e cmp 252\[r0\]\.w, r15 + ba: 06 85 00 3f cmp 252\[r0\]\.l, r0 + be: 06 85 0f 3f cmp 252\[r0\]\.l, r15 + c2: 45 f0 fc cmp 252\[r15\]\.ub, r0 + c5: 45 ff fc cmp 252\[r15\]\.ub, r15 + c8: 06 05 f0 fc cmp 252\[r15\]\.b, r0 + cc: 06 05 ff fc cmp 252\[r15\]\.b, r15 + d0: 06 c5 f0 7e cmp 252\[r15\]\.uw, r0 + d4: 06 c5 ff 7e cmp 252\[r15\]\.uw, r15 + d8: 06 45 f0 7e cmp 252\[r15\]\.w, r0 + dc: 06 45 ff 7e cmp 252\[r15\]\.w, r15 + e0: 06 85 f0 3f cmp 252\[r15\]\.l, r0 + e4: 06 85 ff 3f cmp 252\[r15\]\.l, r15 + e8: 46 00 fc ff cmp 65532\[r0\]\.ub, r0 + ec: 46 0f fc ff cmp 65532\[r0\]\.ub, r15 + f0: 06 06 00 fc ff cmp 65532\[r0\]\.b, r0 + f5: 06 06 0f fc ff cmp 65532\[r0\]\.b, r15 + fa: 06 c6 00 fe 7f cmp 65532\[r0\]\.uw, r0 + ff: 06 c6 0f fe 7f cmp 65532\[r0\]\.uw, r15 + 104: 06 46 00 fe 7f cmp 65532\[r0\]\.w, r0 + 109: 06 46 0f fe 7f cmp 65532\[r0\]\.w, r15 + 10e: 06 86 00 ff 3f cmp 65532\[r0\]\.l, r0 + 113: 06 86 0f ff 3f cmp 65532\[r0\]\.l, r15 + 118: 46 f0 fc ff cmp 65532\[r15\]\.ub, r0 + 11c: 46 ff fc ff cmp 65532\[r15\]\.ub, r15 + 120: 06 06 f0 fc ff cmp 65532\[r15\]\.b, r0 + 125: 06 06 ff fc ff cmp 65532\[r15\]\.b, r15 + 12a: 06 c6 f0 fe 7f cmp 65532\[r15\]\.uw, r0 + 12f: 06 c6 ff fe 7f cmp 65532\[r15\]\.uw, r15 + 134: 06 46 f0 fe 7f cmp 65532\[r15\]\.w, r0 + 139: 06 46 ff fe 7f cmp 65532\[r15\]\.w, r15 + 13e: 06 86 f0 ff 3f cmp 65532\[r15\]\.l, r0 + 143: 06 86 ff ff 3f cmp 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/cmp.sm b/gas/testsuite/gas/rx/cmp.sm new file mode 100644 index 00000000000..be2a7900ebd --- /dev/null +++ b/gas/testsuite/gas/rx/cmp.sm @@ -0,0 +1,6 @@ + cmp #{uimm4},{reg} + cmp #{uimm8},{reg} + cmp #{imm},{reg} + cmp {reg},{reg} + cmp {memx},{reg} + diff --git a/gas/testsuite/gas/rx/dbt.d b/gas/testsuite/gas/rx/dbt.d new file mode 100644 index 00000000000..30aefd86edd --- /dev/null +++ b/gas/testsuite/gas/rx/dbt.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 01 dbt diff --git a/gas/testsuite/gas/rx/dbt.sm b/gas/testsuite/gas/rx/dbt.sm new file mode 100644 index 00000000000..e72f3aa34f0 --- /dev/null +++ b/gas/testsuite/gas/rx/dbt.sm @@ -0,0 +1 @@ + dbt diff --git a/gas/testsuite/gas/rx/div.d b/gas/testsuite/gas/rx/div.d new file mode 100644 index 00000000000..b0aa5eead27 --- /dev/null +++ b/gas/testsuite/gas/rx/div.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 80 80 div #-128, r0 + 4: fd 74 8f 80 div #-128, r15 + 8: fd 74 80 7f div #127, r0 + c: fd 74 8f 7f div #127, r15 + 10: fd 78 80 00 80 div #0xffff8000, r0 + 15: fd 78 8f 00 80 div #0xffff8000, r15 + 1a: fd 7c 80 00 80 00 div #0x8000, r0 + 20: fd 7c 8f 00 80 00 div #0x8000, r15 + 26: fd 7c 80 00 00 80 div #0xff800000, r0 + 2c: fd 7c 8f 00 00 80 div #0xff800000, r15 + 32: fd 7c 80 ff ff 7f div #0x7fffff, r0 + 38: fd 7c 8f ff ff 7f div #0x7fffff, r15 + 3e: fd 70 80 00 00 00 80 div #0x80000000, r0 + 45: fd 70 8f 00 00 00 80 div #0x80000000, r15 + 4c: fd 70 80 ff ff ff 7f div #0x7fffffff, r0 + 53: fd 70 8f ff ff ff 7f div #0x7fffffff, r15 + 5a: fc 23 00 div r0, r0 + 5d: fc 23 0f div r0, r15 + 60: fc 23 f0 div r15, r0 + 63: fc 23 ff div r15, r15 + 66: fc 20 00 div \[r0\]\.ub, r0 + 69: fc 20 0f div \[r0\]\.ub, r15 + 6c: 06 20 08 00 div \[r0\]\.b, r0 + 70: 06 20 08 0f div \[r0\]\.b, r15 + 74: 06 e0 08 00 div \[r0\]\.uw, r0 + 78: 06 e0 08 0f div \[r0\]\.uw, r15 + 7c: 06 60 08 00 div \[r0\]\.w, r0 + 80: 06 60 08 0f div \[r0\]\.w, r15 + 84: 06 a0 08 00 div \[r0\]\.l, r0 + 88: 06 a0 08 0f div \[r0\]\.l, r15 + 8c: fc 20 f0 div \[r15\]\.ub, r0 + 8f: fc 20 ff div \[r15\]\.ub, r15 + 92: 06 20 08 f0 div \[r15\]\.b, r0 + 96: 06 20 08 ff div \[r15\]\.b, r15 + 9a: 06 e0 08 f0 div \[r15\]\.uw, r0 + 9e: 06 e0 08 ff div \[r15\]\.uw, r15 + a2: 06 60 08 f0 div \[r15\]\.w, r0 + a6: 06 60 08 ff div \[r15\]\.w, r15 + aa: 06 a0 08 f0 div \[r15\]\.l, r0 + ae: 06 a0 08 ff div \[r15\]\.l, r15 + b2: fc 21 00 fc div 252\[r0\]\.ub, r0 + b6: fc 21 0f fc div 252\[r0\]\.ub, r15 + ba: 06 21 08 00 fc div 252\[r0\]\.b, r0 + bf: 06 21 08 0f fc div 252\[r0\]\.b, r15 + c4: 06 e1 08 00 7e div 252\[r0\]\.uw, r0 + c9: 06 e1 08 0f 7e div 252\[r0\]\.uw, r15 + ce: 06 61 08 00 7e div 252\[r0\]\.w, r0 + d3: 06 61 08 0f 7e div 252\[r0\]\.w, r15 + d8: 06 a1 08 00 3f div 252\[r0\]\.l, r0 + dd: 06 a1 08 0f 3f div 252\[r0\]\.l, r15 + e2: fc 21 f0 fc div 252\[r15\]\.ub, r0 + e6: fc 21 ff fc div 252\[r15\]\.ub, r15 + ea: 06 21 08 f0 fc div 252\[r15\]\.b, r0 + ef: 06 21 08 ff fc div 252\[r15\]\.b, r15 + f4: 06 e1 08 f0 7e div 252\[r15\]\.uw, r0 + f9: 06 e1 08 ff 7e div 252\[r15\]\.uw, r15 + fe: 06 61 08 f0 7e div 252\[r15\]\.w, r0 + 103: 06 61 08 ff 7e div 252\[r15\]\.w, r15 + 108: 06 a1 08 f0 3f div 252\[r15\]\.l, r0 + 10d: 06 a1 08 ff 3f div 252\[r15\]\.l, r15 + 112: fc 22 00 fc ff div 65532\[r0\]\.ub, r0 + 117: fc 22 0f fc ff div 65532\[r0\]\.ub, r15 + 11c: 06 22 08 00 fc ff div 65532\[r0\]\.b, r0 + 122: 06 22 08 0f fc ff div 65532\[r0\]\.b, r15 + 128: 06 e2 08 00 fe 7f div 65532\[r0\]\.uw, r0 + 12e: 06 e2 08 0f fe 7f div 65532\[r0\]\.uw, r15 + 134: 06 62 08 00 fe 7f div 65532\[r0\]\.w, r0 + 13a: 06 62 08 0f fe 7f div 65532\[r0\]\.w, r15 + 140: 06 a2 08 00 ff 3f div 65532\[r0\]\.l, r0 + 146: 06 a2 08 0f ff 3f div 65532\[r0\]\.l, r15 + 14c: fc 22 f0 fc ff div 65532\[r15\]\.ub, r0 + 151: fc 22 ff fc ff div 65532\[r15\]\.ub, r15 + 156: 06 22 08 f0 fc ff div 65532\[r15\]\.b, r0 + 15c: 06 22 08 ff fc ff div 65532\[r15\]\.b, r15 + 162: 06 e2 08 f0 fe 7f div 65532\[r15\]\.uw, r0 + 168: 06 e2 08 ff fe 7f div 65532\[r15\]\.uw, r15 + 16e: 06 62 08 f0 fe 7f div 65532\[r15\]\.w, r0 + 174: 06 62 08 ff fe 7f div 65532\[r15\]\.w, r15 + 17a: 06 a2 08 f0 ff 3f div 65532\[r15\]\.l, r0 + 180: 06 a2 08 ff ff 3f div 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/div.sm b/gas/testsuite/gas/rx/div.sm new file mode 100644 index 00000000000..1a5587a71fa --- /dev/null +++ b/gas/testsuite/gas/rx/div.sm @@ -0,0 +1,4 @@ + div #{imm},{reg} + div {reg},{reg} + div {memx},{reg} + diff --git a/gas/testsuite/gas/rx/divu.d b/gas/testsuite/gas/rx/divu.d new file mode 100644 index 00000000000..f3802947103 --- /dev/null +++ b/gas/testsuite/gas/rx/divu.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 90 80 divu #-128, r0 + 4: fd 74 9f 80 divu #-128, r15 + 8: fd 74 90 7f divu #127, r0 + c: fd 74 9f 7f divu #127, r15 + 10: fd 78 90 00 80 divu #0xffff8000, r0 + 15: fd 78 9f 00 80 divu #0xffff8000, r15 + 1a: fd 7c 90 00 80 00 divu #0x8000, r0 + 20: fd 7c 9f 00 80 00 divu #0x8000, r15 + 26: fd 7c 90 00 00 80 divu #0xff800000, r0 + 2c: fd 7c 9f 00 00 80 divu #0xff800000, r15 + 32: fd 7c 90 ff ff 7f divu #0x7fffff, r0 + 38: fd 7c 9f ff ff 7f divu #0x7fffff, r15 + 3e: fd 70 90 00 00 00 80 divu #0x80000000, r0 + 45: fd 70 9f 00 00 00 80 divu #0x80000000, r15 + 4c: fd 70 90 ff ff ff 7f divu #0x7fffffff, r0 + 53: fd 70 9f ff ff ff 7f divu #0x7fffffff, r15 + 5a: fc 27 00 divu r0, r0 + 5d: fc 27 0f divu r0, r15 + 60: fc 27 f0 divu r15, r0 + 63: fc 27 ff divu r15, r15 + 66: fc 24 00 divu \[r0\]\.ub, r0 + 69: fc 24 0f divu \[r0\]\.ub, r15 + 6c: 06 20 09 00 divu \[r0\]\.b, r0 + 70: 06 20 09 0f divu \[r0\]\.b, r15 + 74: 06 e0 09 00 divu \[r0\]\.uw, r0 + 78: 06 e0 09 0f divu \[r0\]\.uw, r15 + 7c: 06 60 09 00 divu \[r0\]\.w, r0 + 80: 06 60 09 0f divu \[r0\]\.w, r15 + 84: 06 a0 09 00 divu \[r0\]\.l, r0 + 88: 06 a0 09 0f divu \[r0\]\.l, r15 + 8c: fc 24 f0 divu \[r15\]\.ub, r0 + 8f: fc 24 ff divu \[r15\]\.ub, r15 + 92: 06 20 09 f0 divu \[r15\]\.b, r0 + 96: 06 20 09 ff divu \[r15\]\.b, r15 + 9a: 06 e0 09 f0 divu \[r15\]\.uw, r0 + 9e: 06 e0 09 ff divu \[r15\]\.uw, r15 + a2: 06 60 09 f0 divu \[r15\]\.w, r0 + a6: 06 60 09 ff divu \[r15\]\.w, r15 + aa: 06 a0 09 f0 divu \[r15\]\.l, r0 + ae: 06 a0 09 ff divu \[r15\]\.l, r15 + b2: fc 25 00 fc divu 252\[r0\]\.ub, r0 + b6: fc 25 0f fc divu 252\[r0\]\.ub, r15 + ba: 06 21 09 00 fc divu 252\[r0\]\.b, r0 + bf: 06 21 09 0f fc divu 252\[r0\]\.b, r15 + c4: 06 e1 09 00 7e divu 252\[r0\]\.uw, r0 + c9: 06 e1 09 0f 7e divu 252\[r0\]\.uw, r15 + ce: 06 61 09 00 7e divu 252\[r0\]\.w, r0 + d3: 06 61 09 0f 7e divu 252\[r0\]\.w, r15 + d8: 06 a1 09 00 3f divu 252\[r0\]\.l, r0 + dd: 06 a1 09 0f 3f divu 252\[r0\]\.l, r15 + e2: fc 25 f0 fc divu 252\[r15\]\.ub, r0 + e6: fc 25 ff fc divu 252\[r15\]\.ub, r15 + ea: 06 21 09 f0 fc divu 252\[r15\]\.b, r0 + ef: 06 21 09 ff fc divu 252\[r15\]\.b, r15 + f4: 06 e1 09 f0 7e divu 252\[r15\]\.uw, r0 + f9: 06 e1 09 ff 7e divu 252\[r15\]\.uw, r15 + fe: 06 61 09 f0 7e divu 252\[r15\]\.w, r0 + 103: 06 61 09 ff 7e divu 252\[r15\]\.w, r15 + 108: 06 a1 09 f0 3f divu 252\[r15\]\.l, r0 + 10d: 06 a1 09 ff 3f divu 252\[r15\]\.l, r15 + 112: fc 26 00 fc ff divu 65532\[r0\]\.ub, r0 + 117: fc 26 0f fc ff divu 65532\[r0\]\.ub, r15 + 11c: 06 22 09 00 fc ff divu 65532\[r0\]\.b, r0 + 122: 06 22 09 0f fc ff divu 65532\[r0\]\.b, r15 + 128: 06 e2 09 00 fe 7f divu 65532\[r0\]\.uw, r0 + 12e: 06 e2 09 0f fe 7f divu 65532\[r0\]\.uw, r15 + 134: 06 62 09 00 fe 7f divu 65532\[r0\]\.w, r0 + 13a: 06 62 09 0f fe 7f divu 65532\[r0\]\.w, r15 + 140: 06 a2 09 00 ff 3f divu 65532\[r0\]\.l, r0 + 146: 06 a2 09 0f ff 3f divu 65532\[r0\]\.l, r15 + 14c: fc 26 f0 fc ff divu 65532\[r15\]\.ub, r0 + 151: fc 26 ff fc ff divu 65532\[r15\]\.ub, r15 + 156: 06 22 09 f0 fc ff divu 65532\[r15\]\.b, r0 + 15c: 06 22 09 ff fc ff divu 65532\[r15\]\.b, r15 + 162: 06 e2 09 f0 fe 7f divu 65532\[r15\]\.uw, r0 + 168: 06 e2 09 ff fe 7f divu 65532\[r15\]\.uw, r15 + 16e: 06 62 09 f0 fe 7f divu 65532\[r15\]\.w, r0 + 174: 06 62 09 ff fe 7f divu 65532\[r15\]\.w, r15 + 17a: 06 a2 09 f0 ff 3f divu 65532\[r15\]\.l, r0 + 180: 06 a2 09 ff ff 3f divu 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/divu.sm b/gas/testsuite/gas/rx/divu.sm new file mode 100644 index 00000000000..95b5f1f8234 --- /dev/null +++ b/gas/testsuite/gas/rx/divu.sm @@ -0,0 +1,4 @@ + divu #{imm},{reg} + divu {reg},{reg} + divu {memx},{reg} + diff --git a/gas/testsuite/gas/rx/emul.d b/gas/testsuite/gas/rx/emul.d new file mode 100644 index 00000000000..49ecdcd722f --- /dev/null +++ b/gas/testsuite/gas/rx/emul.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 60 80 emul #-128, r0 + 4: fd 74 6e 80 emul #-128, r14 + 8: fd 74 60 7f emul #127, r0 + c: fd 74 6e 7f emul #127, r14 + 10: fd 78 60 00 80 emul #0xffff8000, r0 + 15: fd 78 6e 00 80 emul #0xffff8000, r14 + 1a: fd 7c 60 00 80 00 emul #0x8000, r0 + 20: fd 7c 6e 00 80 00 emul #0x8000, r14 + 26: fd 7c 60 00 00 80 emul #0xff800000, r0 + 2c: fd 7c 6e 00 00 80 emul #0xff800000, r14 + 32: fd 7c 60 ff ff 7f emul #0x7fffff, r0 + 38: fd 7c 6e ff ff 7f emul #0x7fffff, r14 + 3e: fd 70 60 00 00 00 80 emul #0x80000000, r0 + 45: fd 70 6e 00 00 00 80 emul #0x80000000, r14 + 4c: fd 70 60 ff ff ff 7f emul #0x7fffffff, r0 + 53: fd 70 6e ff ff ff 7f emul #0x7fffffff, r14 + 5a: fc 1b 00 emul r0, r0 + 5d: fc 1b 0e emul r0, r14 + 60: fc 1b f0 emul r15, r0 + 63: fc 1b fe emul r15, r14 + 66: fc 18 00 emul \[r0\]\.ub, r0 + 69: fc 18 0e emul \[r0\]\.ub, r14 + 6c: 06 20 06 00 emul \[r0\]\.b, r0 + 70: 06 20 06 0e emul \[r0\]\.b, r14 + 74: 06 e0 06 00 emul \[r0\]\.uw, r0 + 78: 06 e0 06 0e emul \[r0\]\.uw, r14 + 7c: 06 60 06 00 emul \[r0\]\.w, r0 + 80: 06 60 06 0e emul \[r0\]\.w, r14 + 84: 06 a0 06 00 emul \[r0\]\.l, r0 + 88: 06 a0 06 0e emul \[r0\]\.l, r14 + 8c: fc 18 f0 emul \[r15\]\.ub, r0 + 8f: fc 18 fe emul \[r15\]\.ub, r14 + 92: 06 20 06 f0 emul \[r15\]\.b, r0 + 96: 06 20 06 fe emul \[r15\]\.b, r14 + 9a: 06 e0 06 f0 emul \[r15\]\.uw, r0 + 9e: 06 e0 06 fe emul \[r15\]\.uw, r14 + a2: 06 60 06 f0 emul \[r15\]\.w, r0 + a6: 06 60 06 fe emul \[r15\]\.w, r14 + aa: 06 a0 06 f0 emul \[r15\]\.l, r0 + ae: 06 a0 06 fe emul \[r15\]\.l, r14 + b2: fc 19 00 fc emul 252\[r0\]\.ub, r0 + b6: fc 19 0e fc emul 252\[r0\]\.ub, r14 + ba: 06 21 06 00 fc emul 252\[r0\]\.b, r0 + bf: 06 21 06 0e fc emul 252\[r0\]\.b, r14 + c4: 06 e1 06 00 7e emul 252\[r0\]\.uw, r0 + c9: 06 e1 06 0e 7e emul 252\[r0\]\.uw, r14 + ce: 06 61 06 00 7e emul 252\[r0\]\.w, r0 + d3: 06 61 06 0e 7e emul 252\[r0\]\.w, r14 + d8: 06 a1 06 00 3f emul 252\[r0\]\.l, r0 + dd: 06 a1 06 0e 3f emul 252\[r0\]\.l, r14 + e2: fc 19 f0 fc emul 252\[r15\]\.ub, r0 + e6: fc 19 fe fc emul 252\[r15\]\.ub, r14 + ea: 06 21 06 f0 fc emul 252\[r15\]\.b, r0 + ef: 06 21 06 fe fc emul 252\[r15\]\.b, r14 + f4: 06 e1 06 f0 7e emul 252\[r15\]\.uw, r0 + f9: 06 e1 06 fe 7e emul 252\[r15\]\.uw, r14 + fe: 06 61 06 f0 7e emul 252\[r15\]\.w, r0 + 103: 06 61 06 fe 7e emul 252\[r15\]\.w, r14 + 108: 06 a1 06 f0 3f emul 252\[r15\]\.l, r0 + 10d: 06 a1 06 fe 3f emul 252\[r15\]\.l, r14 + 112: fc 1a 00 fc ff emul 65532\[r0\]\.ub, r0 + 117: fc 1a 0e fc ff emul 65532\[r0\]\.ub, r14 + 11c: 06 22 06 00 fc ff emul 65532\[r0\]\.b, r0 + 122: 06 22 06 0e fc ff emul 65532\[r0\]\.b, r14 + 128: 06 e2 06 00 fe 7f emul 65532\[r0\]\.uw, r0 + 12e: 06 e2 06 0e fe 7f emul 65532\[r0\]\.uw, r14 + 134: 06 62 06 00 fe 7f emul 65532\[r0\]\.w, r0 + 13a: 06 62 06 0e fe 7f emul 65532\[r0\]\.w, r14 + 140: 06 a2 06 00 ff 3f emul 65532\[r0\]\.l, r0 + 146: 06 a2 06 0e ff 3f emul 65532\[r0\]\.l, r14 + 14c: fc 1a f0 fc ff emul 65532\[r15\]\.ub, r0 + 151: fc 1a fe fc ff emul 65532\[r15\]\.ub, r14 + 156: 06 22 06 f0 fc ff emul 65532\[r15\]\.b, r0 + 15c: 06 22 06 fe fc ff emul 65532\[r15\]\.b, r14 + 162: 06 e2 06 f0 fe 7f emul 65532\[r15\]\.uw, r0 + 168: 06 e2 06 fe fe 7f emul 65532\[r15\]\.uw, r14 + 16e: 06 62 06 f0 fe 7f emul 65532\[r15\]\.w, r0 + 174: 06 62 06 fe fe 7f emul 65532\[r15\]\.w, r14 + 17a: 06 a2 06 f0 ff 3f emul 65532\[r15\]\.l, r0 + 180: 06 a2 06 fe ff 3f emul 65532\[r15\]\.l, r14 diff --git a/gas/testsuite/gas/rx/emul.sm b/gas/testsuite/gas/rx/emul.sm new file mode 100644 index 00000000000..10a357d0026 --- /dev/null +++ b/gas/testsuite/gas/rx/emul.sm @@ -0,0 +1,4 @@ + emul #{imm},{reg2} + emul {reg},{reg2} + emul {memx},{reg2} + diff --git a/gas/testsuite/gas/rx/emulu.d b/gas/testsuite/gas/rx/emulu.d new file mode 100644 index 00000000000..6cafe882a73 --- /dev/null +++ b/gas/testsuite/gas/rx/emulu.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 70 80 emulu #-128, r0 + 4: fd 74 7e 80 emulu #-128, r14 + 8: fd 74 70 7f emulu #127, r0 + c: fd 74 7e 7f emulu #127, r14 + 10: fd 78 70 00 80 emulu #0xffff8000, r0 + 15: fd 78 7e 00 80 emulu #0xffff8000, r14 + 1a: fd 7c 70 00 80 00 emulu #0x8000, r0 + 20: fd 7c 7e 00 80 00 emulu #0x8000, r14 + 26: fd 7c 70 00 00 80 emulu #0xff800000, r0 + 2c: fd 7c 7e 00 00 80 emulu #0xff800000, r14 + 32: fd 7c 70 ff ff 7f emulu #0x7fffff, r0 + 38: fd 7c 7e ff ff 7f emulu #0x7fffff, r14 + 3e: fd 70 70 00 00 00 80 emulu #0x80000000, r0 + 45: fd 70 7e 00 00 00 80 emulu #0x80000000, r14 + 4c: fd 70 70 ff ff ff 7f emulu #0x7fffffff, r0 + 53: fd 70 7e ff ff ff 7f emulu #0x7fffffff, r14 + 5a: fc 1f 00 emulu r0, r0 + 5d: fc 1f 0e emulu r0, r14 + 60: fc 1f f0 emulu r15, r0 + 63: fc 1f fe emulu r15, r14 + 66: fc 1c 00 emulu \[r0\]\.ub, r0 + 69: fc 1c 0e emulu \[r0\]\.ub, r14 + 6c: 06 20 07 00 emulu \[r0\]\.b, r0 + 70: 06 20 07 0e emulu \[r0\]\.b, r14 + 74: 06 e0 07 00 emulu \[r0\]\.uw, r0 + 78: 06 e0 07 0e emulu \[r0\]\.uw, r14 + 7c: 06 60 07 00 emulu \[r0\]\.w, r0 + 80: 06 60 07 0e emulu \[r0\]\.w, r14 + 84: 06 a0 07 00 emulu \[r0\]\.l, r0 + 88: 06 a0 07 0e emulu \[r0\]\.l, r14 + 8c: fc 1c f0 emulu \[r15\]\.ub, r0 + 8f: fc 1c fe emulu \[r15\]\.ub, r14 + 92: 06 20 07 f0 emulu \[r15\]\.b, r0 + 96: 06 20 07 fe emulu \[r15\]\.b, r14 + 9a: 06 e0 07 f0 emulu \[r15\]\.uw, r0 + 9e: 06 e0 07 fe emulu \[r15\]\.uw, r14 + a2: 06 60 07 f0 emulu \[r15\]\.w, r0 + a6: 06 60 07 fe emulu \[r15\]\.w, r14 + aa: 06 a0 07 f0 emulu \[r15\]\.l, r0 + ae: 06 a0 07 fe emulu \[r15\]\.l, r14 + b2: fc 1d 00 fc emulu 252\[r0\]\.ub, r0 + b6: fc 1d 0e fc emulu 252\[r0\]\.ub, r14 + ba: 06 21 07 00 fc emulu 252\[r0\]\.b, r0 + bf: 06 21 07 0e fc emulu 252\[r0\]\.b, r14 + c4: 06 e1 07 00 7e emulu 252\[r0\]\.uw, r0 + c9: 06 e1 07 0e 7e emulu 252\[r0\]\.uw, r14 + ce: 06 61 07 00 7e emulu 252\[r0\]\.w, r0 + d3: 06 61 07 0e 7e emulu 252\[r0\]\.w, r14 + d8: 06 a1 07 00 3f emulu 252\[r0\]\.l, r0 + dd: 06 a1 07 0e 3f emulu 252\[r0\]\.l, r14 + e2: fc 1d f0 fc emulu 252\[r15\]\.ub, r0 + e6: fc 1d fe fc emulu 252\[r15\]\.ub, r14 + ea: 06 21 07 f0 fc emulu 252\[r15\]\.b, r0 + ef: 06 21 07 fe fc emulu 252\[r15\]\.b, r14 + f4: 06 e1 07 f0 7e emulu 252\[r15\]\.uw, r0 + f9: 06 e1 07 fe 7e emulu 252\[r15\]\.uw, r14 + fe: 06 61 07 f0 7e emulu 252\[r15\]\.w, r0 + 103: 06 61 07 fe 7e emulu 252\[r15\]\.w, r14 + 108: 06 a1 07 f0 3f emulu 252\[r15\]\.l, r0 + 10d: 06 a1 07 fe 3f emulu 252\[r15\]\.l, r14 + 112: fc 1e 00 fc ff emulu 65532\[r0\]\.ub, r0 + 117: fc 1e 0e fc ff emulu 65532\[r0\]\.ub, r14 + 11c: 06 22 07 00 fc ff emulu 65532\[r0\]\.b, r0 + 122: 06 22 07 0e fc ff emulu 65532\[r0\]\.b, r14 + 128: 06 e2 07 00 fe 7f emulu 65532\[r0\]\.uw, r0 + 12e: 06 e2 07 0e fe 7f emulu 65532\[r0\]\.uw, r14 + 134: 06 62 07 00 fe 7f emulu 65532\[r0\]\.w, r0 + 13a: 06 62 07 0e fe 7f emulu 65532\[r0\]\.w, r14 + 140: 06 a2 07 00 ff 3f emulu 65532\[r0\]\.l, r0 + 146: 06 a2 07 0e ff 3f emulu 65532\[r0\]\.l, r14 + 14c: fc 1e f0 fc ff emulu 65532\[r15\]\.ub, r0 + 151: fc 1e fe fc ff emulu 65532\[r15\]\.ub, r14 + 156: 06 22 07 f0 fc ff emulu 65532\[r15\]\.b, r0 + 15c: 06 22 07 fe fc ff emulu 65532\[r15\]\.b, r14 + 162: 06 e2 07 f0 fe 7f emulu 65532\[r15\]\.uw, r0 + 168: 06 e2 07 fe fe 7f emulu 65532\[r15\]\.uw, r14 + 16e: 06 62 07 f0 fe 7f emulu 65532\[r15\]\.w, r0 + 174: 06 62 07 fe fe 7f emulu 65532\[r15\]\.w, r14 + 17a: 06 a2 07 f0 ff 3f emulu 65532\[r15\]\.l, r0 + 180: 06 a2 07 fe ff 3f emulu 65532\[r15\]\.l, r14 diff --git a/gas/testsuite/gas/rx/emulu.sm b/gas/testsuite/gas/rx/emulu.sm new file mode 100644 index 00000000000..c8b13ef5c82 --- /dev/null +++ b/gas/testsuite/gas/rx/emulu.sm @@ -0,0 +1,4 @@ + emulu #{imm},{reg2} + emulu {reg},{reg2} + emulu {memx},{reg2} + diff --git a/gas/testsuite/gas/rx/explode b/gas/testsuite/gas/rx/explode new file mode 100755 index 00000000000..f4d26feff07 --- /dev/null +++ b/gas/testsuite/gas/rx/explode @@ -0,0 +1,199 @@ +#!/usr/bin/perl +# -*- perl -*- + +# Copyright (C) 2006 Red Hat Inc. +# +# This file is part of GAS, the GNU Assembler. +# +# GAS is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GAS is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GAS; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. */ + +%myfiles = (); + +$incdir = "."; + +while ($ARGV[0] =~ /^-/) { + $opt = shift; + if ($opt eq "-I") { + $incdir = shift; + } +} + +$infile = shift; +$outfile = shift; + +$inbase = $infile; +$inbase =~ s@.*/@@; +$inbase =~ s@[^a-zA-Z0-9].*@@; + +$t = 0; +$errors = 0; + +if ($outfile) { + open(OUT, ">$outfile"); +} else { + open(OUT, ">&STDOUT"); +} + +open(I, "$incdir/macros.inc") || die("$incdir/macros.inc: $!"); +&read_file(); +close I; +open(I, $infile) || die("$infile: $!"); +&read_file(); +close I; + +sub read_file { + while (<I>) { + $line ++; + next if /^;/; + s/[\r\n]+$//; + if (/^macro\s+(\S+)\s+(.*)/) { + ($name, $val) = ($1,$2); + print "set macro \"$name\" to \"$val\"\n" if $t; + $macro{$name} = $val; + } elsif (/\S/) { + &explode($_); + } + } +} + +exit ($errors); + +# There's no way to quote braces so you can output them :-P + +sub explode { + my ($s) = @_; + my ($a, $b, $p, $e, @params); + + print "explode($s)\n" if $t; + + ($b, $a, @params) = &split_braces($s); + @params = explode_params (@params); + if (! $a && ! @params) { + if ($t) { + print "\033[33m$s\033[0m\n"; + } else { + print OUT "$s\n"; + } + return; + } + if (@params == 1 && defined $macro{$params[0]}) { + $p = $macro{$params[0]}; + &explode ("$b$p$a"); + } else { + for $p (@params) { + &explode ("$b$p$a"); + } + } +} + +sub explode_params { + my (@p) = @_; + my ($p,@r); + + @r = (); + while (@p) { + $p = shift @p; + ($b,$a,@e) = split_braces ($p); + if (defined $a) { + for $e (reverse @e) { + unshift (@p, "$b$e$a"); + } + } else { + push (@r, $p); + } + } + return @r; +} + +sub getmacro { + my ($v) = $macro{$_[0]}; + if (! defined $v) { + print STDERR "$line: Error: macro $_[0] not defined\n"; + $errors ++; + } + return $v; +} + +sub expand_macros { + my ($l) = @_; + 0 while $l =~ s/{([^{};]+)}/&getmacro($1)/ge; + return $l; +} + +# returns (before, after, list of variances) +sub split_braces { + my ($l) = @_; + my (@l, $i, $a, @parms, $b, $n,$p); + + print "split_braces($l) = (" if $t; + + $l = &expand_macros ($l); + + if ($l !~ /\{.*\}/) { + print "nothing)\n" if $t; + return ($l); + } + if ($l =~ /^{([^{};]+)}/) { + print "macro:", $macro{$1}, ")\n" if $t; + return (&getmacro($1), ""); + } + + $n = 0; + @parms = (''); + $p = 0; + + ($a, $l) = $l =~ m@^([^\{]*)\{(.*)@; + @l = split(//, $l); + + while (defined ($i = shift @l)) { + if ($n == 0) { + print "\033[32m$i" if $t; + if ($i eq '}') { + print "\033[0m$a, ", join('', @l), ", (", join("\033[31m;\033[0m", @parms), ")\n" if $t; + return ($a, join('',@l), @parms); + } elsif ($i eq ';') { + $p ++; + $parms[$p] = ''; + } else { + $parms[$p] .= $i; + $n ++ if $i eq '{'; + } + } else { + print "\033[34m$i" if $t; + $n ++ if $i eq '{'; + $n -- if $i eq '}'; + $parms[$p] .= $i; + } + } + print "$a, <null>, (", join(';', @parms), ")\n" if $t; + return ($a, "", @parms); +} + +__END__; + +macro rest c,d + foo {a;b},{{rest};e;} + +expands to: + + foo a,c + foo a,d + foo a,e + foo a, + foo b,c + foo b,d + foo b,e + foo b, diff --git a/gas/testsuite/gas/rx/fadd.d b/gas/testsuite/gas/rx/fadd.d new file mode 100644 index 00000000000..406052bfbf4 --- /dev/null +++ b/gas/testsuite/gas/rx/fadd.d @@ -0,0 +1,28 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 72 20 00 00 00 80 fadd #0x80000000, r0 + 7: fd 72 2f 00 00 00 80 fadd #0x80000000, r15 + e: fd 72 20 ff ff ff ff fadd #-1, r0 + 15: fd 72 2f ff ff ff ff fadd #-1, r15 + 1c: fc 8b 00 fadd r0, r0 + 1f: fc 8b 0f fadd r0, r15 + 22: fc 8b f0 fadd r15, r0 + 25: fc 8b ff fadd r15, r15 + 28: fc 88 00 fadd \[r0\]\.l, r0 + 2b: fc 88 0f fadd \[r0\]\.l, r15 + 2e: fc 88 f0 fadd \[r15\]\.l, r0 + 31: fc 88 ff fadd \[r15\]\.l, r15 + 34: fc 89 00 3f fadd 252\[r0\]\.l, r0 + 38: fc 89 0f 3f fadd 252\[r0\]\.l, r15 + 3c: fc 89 f0 3f fadd 252\[r15\]\.l, r0 + 40: fc 89 ff 3f fadd 252\[r15\]\.l, r15 + 44: fc 8a 00 ff 3f fadd 65532\[r0\]\.l, r0 + 49: fc 8a 0f ff 3f fadd 65532\[r0\]\.l, r15 + 4e: fc 8a f0 ff 3f fadd 65532\[r15\]\.l, r0 + 53: fc 8a ff ff 3f fadd 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/fadd.sm b/gas/testsuite/gas/rx/fadd.sm new file mode 100644 index 00000000000..94021af7f98 --- /dev/null +++ b/gas/testsuite/gas/rx/fadd.sm @@ -0,0 +1,3 @@ + fadd #{imm32},{reg} + fadd {reg},{reg} + fadd {mem}.L,{reg} diff --git a/gas/testsuite/gas/rx/fcmp.d b/gas/testsuite/gas/rx/fcmp.d new file mode 100644 index 00000000000..3a32ead0418 --- /dev/null +++ b/gas/testsuite/gas/rx/fcmp.d @@ -0,0 +1,28 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 72 10 00 00 00 80 fcmp #0x80000000, r0 + 7: fd 72 1f 00 00 00 80 fcmp #0x80000000, r15 + e: fd 72 10 ff ff ff ff fcmp #-1, r0 + 15: fd 72 1f ff ff ff ff fcmp #-1, r15 + 1c: fc 87 00 fcmp r0, r0 + 1f: fc 87 0f fcmp r0, r15 + 22: fc 87 f0 fcmp r15, r0 + 25: fc 87 ff fcmp r15, r15 + 28: fc 84 00 fcmp \[r0\]\.l, r0 + 2b: fc 84 0f fcmp \[r0\]\.l, r15 + 2e: fc 84 f0 fcmp \[r15\]\.l, r0 + 31: fc 84 ff fcmp \[r15\]\.l, r15 + 34: fc 85 00 3f fcmp 252\[r0\]\.l, r0 + 38: fc 85 0f 3f fcmp 252\[r0\]\.l, r15 + 3c: fc 85 f0 3f fcmp 252\[r15\]\.l, r0 + 40: fc 85 ff 3f fcmp 252\[r15\]\.l, r15 + 44: fc 86 00 ff 3f fcmp 65532\[r0\]\.l, r0 + 49: fc 86 0f ff 3f fcmp 65532\[r0\]\.l, r15 + 4e: fc 86 f0 ff 3f fcmp 65532\[r15\]\.l, r0 + 53: fc 86 ff ff 3f fcmp 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/fcmp.sm b/gas/testsuite/gas/rx/fcmp.sm new file mode 100644 index 00000000000..7e43cbc869e --- /dev/null +++ b/gas/testsuite/gas/rx/fcmp.sm @@ -0,0 +1,3 @@ + fcmp #{imm32},{reg} + fcmp {reg},{reg} + fcmp {mem}.L,{reg} diff --git a/gas/testsuite/gas/rx/fdiv.d b/gas/testsuite/gas/rx/fdiv.d new file mode 100644 index 00000000000..0e78882f39d --- /dev/null +++ b/gas/testsuite/gas/rx/fdiv.d @@ -0,0 +1,28 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 72 40 00 00 00 80 fdiv #0x80000000, r0 + 7: fd 72 4f 00 00 00 80 fdiv #0x80000000, r15 + e: fd 72 40 ff ff ff ff fdiv #-1, r0 + 15: fd 72 4f ff ff ff ff fdiv #-1, r15 + 1c: fc 93 00 fdiv r0, r0 + 1f: fc 93 0f fdiv r0, r15 + 22: fc 93 f0 fdiv r15, r0 + 25: fc 93 ff fdiv r15, r15 + 28: fc 90 00 fdiv \[r0\]\.l, r0 + 2b: fc 90 0f fdiv \[r0\]\.l, r15 + 2e: fc 90 f0 fdiv \[r15\]\.l, r0 + 31: fc 90 ff fdiv \[r15\]\.l, r15 + 34: fc 91 00 3f fdiv 252\[r0\]\.l, r0 + 38: fc 91 0f 3f fdiv 252\[r0\]\.l, r15 + 3c: fc 91 f0 3f fdiv 252\[r15\]\.l, r0 + 40: fc 91 ff 3f fdiv 252\[r15\]\.l, r15 + 44: fc 92 00 ff 3f fdiv 65532\[r0\]\.l, r0 + 49: fc 92 0f ff 3f fdiv 65532\[r0\]\.l, r15 + 4e: fc 92 f0 ff 3f fdiv 65532\[r15\]\.l, r0 + 53: fc 92 ff ff 3f fdiv 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/fdiv.sm b/gas/testsuite/gas/rx/fdiv.sm new file mode 100644 index 00000000000..371084995e9 --- /dev/null +++ b/gas/testsuite/gas/rx/fdiv.sm @@ -0,0 +1,3 @@ + fdiv #{imm32},{reg} + fdiv {reg},{reg} + fdiv {mem}.L,{reg} diff --git a/gas/testsuite/gas/rx/fmul.d b/gas/testsuite/gas/rx/fmul.d new file mode 100644 index 00000000000..7fec0af139c --- /dev/null +++ b/gas/testsuite/gas/rx/fmul.d @@ -0,0 +1,28 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 72 30 00 00 00 80 fmul #0x80000000, r0 + 7: fd 72 3f 00 00 00 80 fmul #0x80000000, r15 + e: fd 72 30 ff ff ff ff fmul #-1, r0 + 15: fd 72 3f ff ff ff ff fmul #-1, r15 + 1c: fc 8f 00 fmul r0, r0 + 1f: fc 8f 0f fmul r0, r15 + 22: fc 8f f0 fmul r15, r0 + 25: fc 8f ff fmul r15, r15 + 28: fc 8c 00 fmul \[r0\]\.l, r0 + 2b: fc 8c 0f fmul \[r0\]\.l, r15 + 2e: fc 8c f0 fmul \[r15\]\.l, r0 + 31: fc 8c ff fmul \[r15\]\.l, r15 + 34: fc 8d 00 3f fmul 252\[r0\]\.l, r0 + 38: fc 8d 0f 3f fmul 252\[r0\]\.l, r15 + 3c: fc 8d f0 3f fmul 252\[r15\]\.l, r0 + 40: fc 8d ff 3f fmul 252\[r15\]\.l, r15 + 44: fc 8e 00 ff 3f fmul 65532\[r0\]\.l, r0 + 49: fc 8e 0f ff 3f fmul 65532\[r0\]\.l, r15 + 4e: fc 8e f0 ff 3f fmul 65532\[r15\]\.l, r0 + 53: fc 8e ff ff 3f fmul 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/fmul.sm b/gas/testsuite/gas/rx/fmul.sm new file mode 100644 index 00000000000..e68f24f2924 --- /dev/null +++ b/gas/testsuite/gas/rx/fmul.sm @@ -0,0 +1,3 @@ + fmul #{imm32},{reg} + fmul {reg},{reg} + fmul {mem}.L,{reg} diff --git a/gas/testsuite/gas/rx/fsub.d b/gas/testsuite/gas/rx/fsub.d new file mode 100644 index 00000000000..5d26e5ae5e1 --- /dev/null +++ b/gas/testsuite/gas/rx/fsub.d @@ -0,0 +1,28 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 72 00 00 00 00 80 fsub #0x80000000, r0 + 7: fd 72 0f 00 00 00 80 fsub #0x80000000, r15 + e: fd 72 00 ff ff ff ff fsub #-1, r0 + 15: fd 72 0f ff ff ff ff fsub #-1, r15 + 1c: fc 83 00 fsub r0, r0 + 1f: fc 83 0f fsub r0, r15 + 22: fc 83 f0 fsub r15, r0 + 25: fc 83 ff fsub r15, r15 + 28: fc 80 00 fsub \[r0\]\.l, r0 + 2b: fc 80 0f fsub \[r0\]\.l, r15 + 2e: fc 80 f0 fsub \[r15\]\.l, r0 + 31: fc 80 ff fsub \[r15\]\.l, r15 + 34: fc 81 00 3f fsub 252\[r0\]\.l, r0 + 38: fc 81 0f 3f fsub 252\[r0\]\.l, r15 + 3c: fc 81 f0 3f fsub 252\[r15\]\.l, r0 + 40: fc 81 ff 3f fsub 252\[r15\]\.l, r15 + 44: fc 82 00 ff 3f fsub 65532\[r0\]\.l, r0 + 49: fc 82 0f ff 3f fsub 65532\[r0\]\.l, r15 + 4e: fc 82 f0 ff 3f fsub 65532\[r15\]\.l, r0 + 53: fc 82 ff ff 3f fsub 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/fsub.sm b/gas/testsuite/gas/rx/fsub.sm new file mode 100644 index 00000000000..64b93c9cad8 --- /dev/null +++ b/gas/testsuite/gas/rx/fsub.sm @@ -0,0 +1,3 @@ + fsub #{imm32},{reg} + fsub {reg},{reg} + fsub {mem}.L,{reg} diff --git a/gas/testsuite/gas/rx/ftoi.d b/gas/testsuite/gas/rx/ftoi.d new file mode 100644 index 00000000000..f5075e786bb --- /dev/null +++ b/gas/testsuite/gas/rx/ftoi.d @@ -0,0 +1,24 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc 97 00 ftoi r0, r0 + 3: fc 97 0f ftoi r0, r15 + 6: fc 97 f0 ftoi r15, r0 + 9: fc 97 ff ftoi r15, r15 + c: fc 94 00 ftoi \[r0\]\.l, r0 + f: fc 94 0f ftoi \[r0\]\.l, r15 + 12: fc 94 f0 ftoi \[r15\]\.l, r0 + 15: fc 94 ff ftoi \[r15\]\.l, r15 + 18: fc 95 00 3f ftoi 252\[r0\]\.l, r0 + 1c: fc 95 0f 3f ftoi 252\[r0\]\.l, r15 + 20: fc 95 f0 3f ftoi 252\[r15\]\.l, r0 + 24: fc 95 ff 3f ftoi 252\[r15\]\.l, r15 + 28: fc 96 00 ff 3f ftoi 65532\[r0\]\.l, r0 + 2d: fc 96 0f ff 3f ftoi 65532\[r0\]\.l, r15 + 32: fc 96 f0 ff 3f ftoi 65532\[r15\]\.l, r0 + 37: fc 96 ff ff 3f ftoi 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/ftoi.sm b/gas/testsuite/gas/rx/ftoi.sm new file mode 100644 index 00000000000..a112d1aef35 --- /dev/null +++ b/gas/testsuite/gas/rx/ftoi.sm @@ -0,0 +1,2 @@ + ftoi {reg},{reg} + ftoi {mem}.L,{reg} diff --git a/gas/testsuite/gas/rx/gprel.d b/gas/testsuite/gas/rx/gprel.d new file mode 100644 index 00000000000..6e7c8879351 --- /dev/null +++ b/gas/testsuite/gas/rx/gprel.d @@ -0,0 +1,53 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section .text: + +00000000 <_start>: + 0: ce f1 04 00 mov\.b 4\[r15\], r1 + 2: R_RX_SYM _foo + 2: R_RX_SYM __gp + 2: R_RX_OPsub __gp + 2: R_RX_ABS16U __gp + 4: ce f1 08 00 mov\.b 8\[r15\], r1 + 6: R_RX_SYM _bar + 6: R_RX_SYM __gp + 6: R_RX_OPsub __gp + 6: R_RX_ABS16U __gp + 8: ce f1 00 00 mov\.b \[r15\], r1 + a: R_RX_SYM _grill + a: R_RX_SYM __gp + a: R_RX_OPsub __gp + a: R_RX_ABS16U __gp + c: de f1 02 00 mov\.w 4\[r15\], r1 + e: R_RX_SYM _foo + e: R_RX_SYM __gp + e: R_RX_OPsub __gp + e: R_RX_ABS16UW __gp + 10: de f1 04 00 mov\.w 8\[r15\], r1 + 12: R_RX_SYM _bar + 12: R_RX_SYM __gp + 12: R_RX_OPsub __gp + 12: R_RX_ABS16UW __gp + 14: de f1 00 00 mov\.w \[r15\], r1 + 16: R_RX_SYM _grill + 16: R_RX_SYM __gp + 16: R_RX_OPsub __gp + 16: R_RX_ABS16UW __gp + 18: ee f1 01 00 mov\.l 4\[r15\], r1 + 1a: R_RX_SYM _foo + 1a: R_RX_SYM __gp + 1a: R_RX_OPsub __gp + 1a: R_RX_ABS16UL __gp + 1c: ee f1 02 00 mov\.l 8\[r15\], r1 + 1e: R_RX_SYM _bar + 1e: R_RX_SYM __gp + 1e: R_RX_OPsub __gp + 1e: R_RX_ABS16UL __gp + 20: ee f1 00 00 mov\.l \[r15\], r1 + 22: R_RX_SYM _grill + 22: R_RX_SYM __gp + 22: R_RX_OPsub __gp + 22: R_RX_ABS16UL __gp diff --git a/gas/testsuite/gas/rx/gprel.sm b/gas/testsuite/gas/rx/gprel.sm new file mode 100644 index 00000000000..c2f29baf773 --- /dev/null +++ b/gas/testsuite/gas/rx/gprel.sm @@ -0,0 +1,9 @@ + .text + .global _start +_start: + mov{bwl} %gp({_foo;_bar;_grill})[r15], r1 + + .data +__gp: .long 0 +_foo: .long 5 +_bar: .long 6 diff --git a/gas/testsuite/gas/rx/int.d b/gas/testsuite/gas/rx/int.d new file mode 100644 index 00000000000..dc161cf3890 --- /dev/null +++ b/gas/testsuite/gas/rx/int.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 75 60 00 int #0 + 3: 75 60 ff int #255 diff --git a/gas/testsuite/gas/rx/int.sm b/gas/testsuite/gas/rx/int.sm new file mode 100644 index 00000000000..8d957a8b201 --- /dev/null +++ b/gas/testsuite/gas/rx/int.sm @@ -0,0 +1 @@ + int #{uimm8} diff --git a/gas/testsuite/gas/rx/itof.d b/gas/testsuite/gas/rx/itof.d new file mode 100644 index 00000000000..6102de1e31f --- /dev/null +++ b/gas/testsuite/gas/rx/itof.d @@ -0,0 +1,72 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc 47 00 itof r0, r0 + 3: fc 47 0f itof r0, r15 + 6: fc 47 f0 itof r15, r0 + 9: fc 47 ff itof r15, r15 + c: fc 44 00 itof \[r0\]\.ub, r0 + f: fc 44 0f itof \[r0\]\.ub, r15 + 12: 06 20 11 00 itof \[r0\]\.b, r0 + 16: 06 20 11 0f itof \[r0\]\.b, r15 + 1a: 06 e0 11 00 itof \[r0\]\.uw, r0 + 1e: 06 e0 11 0f itof \[r0\]\.uw, r15 + 22: 06 60 11 00 itof \[r0\]\.w, r0 + 26: 06 60 11 0f itof \[r0\]\.w, r15 + 2a: 06 a0 11 00 itof \[r0\]\.l, r0 + 2e: 06 a0 11 0f itof \[r0\]\.l, r15 + 32: fc 44 f0 itof \[r15\]\.ub, r0 + 35: fc 44 ff itof \[r15\]\.ub, r15 + 38: 06 20 11 f0 itof \[r15\]\.b, r0 + 3c: 06 20 11 ff itof \[r15\]\.b, r15 + 40: 06 e0 11 f0 itof \[r15\]\.uw, r0 + 44: 06 e0 11 ff itof \[r15\]\.uw, r15 + 48: 06 60 11 f0 itof \[r15\]\.w, r0 + 4c: 06 60 11 ff itof \[r15\]\.w, r15 + 50: 06 a0 11 f0 itof \[r15\]\.l, r0 + 54: 06 a0 11 ff itof \[r15\]\.l, r15 + 58: fc 45 00 fc itof 252\[r0\]\.ub, r0 + 5c: fc 45 0f fc itof 252\[r0\]\.ub, r15 + 60: 06 21 11 00 fc itof 252\[r0\]\.b, r0 + 65: 06 21 11 0f fc itof 252\[r0\]\.b, r15 + 6a: 06 e1 11 00 7e itof 252\[r0\]\.uw, r0 + 6f: 06 e1 11 0f 7e itof 252\[r0\]\.uw, r15 + 74: 06 61 11 00 7e itof 252\[r0\]\.w, r0 + 79: 06 61 11 0f 7e itof 252\[r0\]\.w, r15 + 7e: 06 a1 11 00 3f itof 252\[r0\]\.l, r0 + 83: 06 a1 11 0f 3f itof 252\[r0\]\.l, r15 + 88: fc 45 f0 fc itof 252\[r15\]\.ub, r0 + 8c: fc 45 ff fc itof 252\[r15\]\.ub, r15 + 90: 06 21 11 f0 fc itof 252\[r15\]\.b, r0 + 95: 06 21 11 ff fc itof 252\[r15\]\.b, r15 + 9a: 06 e1 11 f0 7e itof 252\[r15\]\.uw, r0 + 9f: 06 e1 11 ff 7e itof 252\[r15\]\.uw, r15 + a4: 06 61 11 f0 7e itof 252\[r15\]\.w, r0 + a9: 06 61 11 ff 7e itof 252\[r15\]\.w, r15 + ae: 06 a1 11 f0 3f itof 252\[r15\]\.l, r0 + b3: 06 a1 11 ff 3f itof 252\[r15\]\.l, r15 + b8: fc 46 00 fc ff itof 65532\[r0\]\.ub, r0 + bd: fc 46 0f fc ff itof 65532\[r0\]\.ub, r15 + c2: 06 22 11 00 fc ff itof 65532\[r0\]\.b, r0 + c8: 06 22 11 0f fc ff itof 65532\[r0\]\.b, r15 + ce: 06 e2 11 00 fe 7f itof 65532\[r0\]\.uw, r0 + d4: 06 e2 11 0f fe 7f itof 65532\[r0\]\.uw, r15 + da: 06 62 11 00 fe 7f itof 65532\[r0\]\.w, r0 + e0: 06 62 11 0f fe 7f itof 65532\[r0\]\.w, r15 + e6: 06 a2 11 00 ff 3f itof 65532\[r0\]\.l, r0 + ec: 06 a2 11 0f ff 3f itof 65532\[r0\]\.l, r15 + f2: fc 46 f0 fc ff itof 65532\[r15\]\.ub, r0 + f7: fc 46 ff fc ff itof 65532\[r15\]\.ub, r15 + fc: 06 22 11 f0 fc ff itof 65532\[r15\]\.b, r0 + 102: 06 22 11 ff fc ff itof 65532\[r15\]\.b, r15 + 108: 06 e2 11 f0 fe 7f itof 65532\[r15\]\.uw, r0 + 10e: 06 e2 11 ff fe 7f itof 65532\[r15\]\.uw, r15 + 114: 06 62 11 f0 fe 7f itof 65532\[r15\]\.w, r0 + 11a: 06 62 11 ff fe 7f itof 65532\[r15\]\.w, r15 + 120: 06 a2 11 f0 ff 3f itof 65532\[r15\]\.l, r0 + 126: 06 a2 11 ff ff 3f itof 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/itof.sm b/gas/testsuite/gas/rx/itof.sm new file mode 100644 index 00000000000..aa3783c01b1 --- /dev/null +++ b/gas/testsuite/gas/rx/itof.sm @@ -0,0 +1,2 @@ + itof {reg},{reg} + itof {memx},{reg} diff --git a/gas/testsuite/gas/rx/jmp.d b/gas/testsuite/gas/rx/jmp.d new file mode 100644 index 00000000000..1cbfd5a29a1 --- /dev/null +++ b/gas/testsuite/gas/rx/jmp.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 00 jmp r0 + 2: 7f 0f jmp r15 diff --git a/gas/testsuite/gas/rx/jmp.sm b/gas/testsuite/gas/rx/jmp.sm new file mode 100644 index 00000000000..e858c642ab4 --- /dev/null +++ b/gas/testsuite/gas/rx/jmp.sm @@ -0,0 +1 @@ + jmp {reg} diff --git a/gas/testsuite/gas/rx/jsr.d b/gas/testsuite/gas/rx/jsr.d new file mode 100644 index 00000000000..77d7f37a860 --- /dev/null +++ b/gas/testsuite/gas/rx/jsr.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 10 jsr r0 + 2: 7f 1f jsr r15 diff --git a/gas/testsuite/gas/rx/jsr.sm b/gas/testsuite/gas/rx/jsr.sm new file mode 100644 index 00000000000..7a52c1bd4d7 --- /dev/null +++ b/gas/testsuite/gas/rx/jsr.sm @@ -0,0 +1 @@ + jsr {reg} diff --git a/gas/testsuite/gas/rx/machi.d b/gas/testsuite/gas/rx/machi.d new file mode 100644 index 00000000000..08006966596 --- /dev/null +++ b/gas/testsuite/gas/rx/machi.d @@ -0,0 +1,12 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 04 00 machi r0, r0 + 3: fd 04 0f machi r0, r15 + 6: fd 04 f0 machi r15, r0 + 9: fd 04 ff machi r15, r15 diff --git a/gas/testsuite/gas/rx/machi.sm b/gas/testsuite/gas/rx/machi.sm new file mode 100644 index 00000000000..f3651d004e1 --- /dev/null +++ b/gas/testsuite/gas/rx/machi.sm @@ -0,0 +1 @@ + machi {reg},{reg} diff --git a/gas/testsuite/gas/rx/maclo.d b/gas/testsuite/gas/rx/maclo.d new file mode 100644 index 00000000000..41ee1f2f844 --- /dev/null +++ b/gas/testsuite/gas/rx/maclo.d @@ -0,0 +1,12 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 05 00 maclo r0, r0 + 3: fd 05 0f maclo r0, r15 + 6: fd 05 f0 maclo r15, r0 + 9: fd 05 ff maclo r15, r15 diff --git a/gas/testsuite/gas/rx/maclo.sm b/gas/testsuite/gas/rx/maclo.sm new file mode 100644 index 00000000000..84a019cdc0b --- /dev/null +++ b/gas/testsuite/gas/rx/maclo.sm @@ -0,0 +1 @@ + maclo {reg},{reg} diff --git a/gas/testsuite/gas/rx/macros.inc b/gas/testsuite/gas/rx/macros.inc new file mode 100644 index 00000000000..d025ac9a630 --- /dev/null +++ b/gas/testsuite/gas/rx/macros.inc @@ -0,0 +1,49 @@ +macro reg {r0;r15} +macro reg2 {r0;r14} +macro reg7 {r0;r7} +macro regPlo {r1;r7} +macro regPhi {r8;r14} +macro creg {psw;fpsw;usp;isp;intb;bpsw;bpc;fintv;cpen} +macro pswf {U;I;O;S;Z;C} + +macro simm8 {-128;127} +macro simm16 {-32768;32768} +macro simm24 {-8388608;8388607} +macro simm32 {-2147483648;2147483647} + +macro imm {{simm8};{simm16};{simm24};{simm32}} + +macro uimm2 {0;3} +macro uimm3 {0;7} +macro uimm4 {0;15} +macro uimm5 {0;31} +macro uimm8 {0;255} +macro uimm16 {0;65535} +macro uimm24 {0;16777215} +macro uimm32 {0;4294967295} + +macro imm32 {-2147483648;4294967295} + +macro dsp5 {4;28} +macro dsp8 252 +macro dsp16 65532 +macro dsp8L 1020 +macro dsp16L 262140 + +macro dsp {;{dsp8};{dsp16}} +macro dspL {;{dsp8L};{dsp16L}} + +macro memex {.ub;.b;.uw;.w;.l} +macro memx {dsp}[{reg}]{memex} +macro mem {dsp}[{reg}] +macro bwl {.b;.w;.l} +macro bw {.b;.w} + +macro cnd {geu;c;eq;z;gtu;pz;ge;gt;o;ltu;nc;ne;nz;leu;n;lt;le;no} +macro lab_s {.+3;.+10;foo} +macro lab_b {.-128;.+127;foo} +macro lab_w {.-32768;.+32767;foo} +macro lab_a {.-8388608;.+8388607;foo} +macro lab_l {.-2147483648;.+2147483647;foo} + + .text diff --git a/gas/testsuite/gas/rx/make-d b/gas/testsuite/gas/rx/make-d new file mode 100755 index 00000000000..be1958e6026 --- /dev/null +++ b/gas/testsuite/gas/rx/make-d @@ -0,0 +1,31 @@ +#!/usr/bin/perl +# -*- perl -*- + +# Utility to create *.d files from *.lst files. Not normally needed. + +opendir L, "/tmp/lsts"; +for $f (sort readdir L) { + next unless $f =~ /\.lst/; + $f =~ s@\.lst@@; + push (@files, $f); +} +closedir L; + +for $f (@files) { + + open (I, "/tmp/lsts/$f.lst"); + open (O, ">$f.d"); + + print O "#objdump: -dr\n"; + + while (<I>) { + s/$f\.o/dump.o/; + s/\\/\\\\/g; + s/([\[\]\.\*\?\+])/\\$1/g; + s/file format .*/file format \.\*/; + print O; + } + + close I; + close O; +} diff --git a/gas/testsuite/gas/rx/max.d b/gas/testsuite/gas/rx/max.d new file mode 100644 index 00000000000..1389322944d --- /dev/null +++ b/gas/testsuite/gas/rx/max.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 40 80 max #-128, r0 + 4: fd 74 4f 80 max #-128, r15 + 8: fd 74 40 7f max #127, r0 + c: fd 74 4f 7f max #127, r15 + 10: fd 78 40 00 80 max #0xffff8000, r0 + 15: fd 78 4f 00 80 max #0xffff8000, r15 + 1a: fd 7c 40 00 80 00 max #0x8000, r0 + 20: fd 7c 4f 00 80 00 max #0x8000, r15 + 26: fd 7c 40 00 00 80 max #0xff800000, r0 + 2c: fd 7c 4f 00 00 80 max #0xff800000, r15 + 32: fd 7c 40 ff ff 7f max #0x7fffff, r0 + 38: fd 7c 4f ff ff 7f max #0x7fffff, r15 + 3e: fd 70 40 00 00 00 80 max #0x80000000, r0 + 45: fd 70 4f 00 00 00 80 max #0x80000000, r15 + 4c: fd 70 40 ff ff ff 7f max #0x7fffffff, r0 + 53: fd 70 4f ff ff ff 7f max #0x7fffffff, r15 + 5a: fc 13 00 max r0, r0 + 5d: fc 13 0f max r0, r15 + 60: fc 13 f0 max r15, r0 + 63: fc 13 ff max r15, r15 + 66: fc 10 00 max \[r0\]\.ub, r0 + 69: fc 10 0f max \[r0\]\.ub, r15 + 6c: 06 20 04 00 max \[r0\]\.b, r0 + 70: 06 20 04 0f max \[r0\]\.b, r15 + 74: 06 e0 04 00 max \[r0\]\.uw, r0 + 78: 06 e0 04 0f max \[r0\]\.uw, r15 + 7c: 06 60 04 00 max \[r0\]\.w, r0 + 80: 06 60 04 0f max \[r0\]\.w, r15 + 84: 06 a0 04 00 max \[r0\]\.l, r0 + 88: 06 a0 04 0f max \[r0\]\.l, r15 + 8c: fc 10 f0 max \[r15\]\.ub, r0 + 8f: fc 10 ff max \[r15\]\.ub, r15 + 92: 06 20 04 f0 max \[r15\]\.b, r0 + 96: 06 20 04 ff max \[r15\]\.b, r15 + 9a: 06 e0 04 f0 max \[r15\]\.uw, r0 + 9e: 06 e0 04 ff max \[r15\]\.uw, r15 + a2: 06 60 04 f0 max \[r15\]\.w, r0 + a6: 06 60 04 ff max \[r15\]\.w, r15 + aa: 06 a0 04 f0 max \[r15\]\.l, r0 + ae: 06 a0 04 ff max \[r15\]\.l, r15 + b2: fc 11 00 fc max 252\[r0\]\.ub, r0 + b6: fc 11 0f fc max 252\[r0\]\.ub, r15 + ba: 06 21 04 00 fc max 252\[r0\]\.b, r0 + bf: 06 21 04 0f fc max 252\[r0\]\.b, r15 + c4: 06 e1 04 00 7e max 252\[r0\]\.uw, r0 + c9: 06 e1 04 0f 7e max 252\[r0\]\.uw, r15 + ce: 06 61 04 00 7e max 252\[r0\]\.w, r0 + d3: 06 61 04 0f 7e max 252\[r0\]\.w, r15 + d8: 06 a1 04 00 3f max 252\[r0\]\.l, r0 + dd: 06 a1 04 0f 3f max 252\[r0\]\.l, r15 + e2: fc 11 f0 fc max 252\[r15\]\.ub, r0 + e6: fc 11 ff fc max 252\[r15\]\.ub, r15 + ea: 06 21 04 f0 fc max 252\[r15\]\.b, r0 + ef: 06 21 04 ff fc max 252\[r15\]\.b, r15 + f4: 06 e1 04 f0 7e max 252\[r15\]\.uw, r0 + f9: 06 e1 04 ff 7e max 252\[r15\]\.uw, r15 + fe: 06 61 04 f0 7e max 252\[r15\]\.w, r0 + 103: 06 61 04 ff 7e max 252\[r15\]\.w, r15 + 108: 06 a1 04 f0 3f max 252\[r15\]\.l, r0 + 10d: 06 a1 04 ff 3f max 252\[r15\]\.l, r15 + 112: fc 12 00 fc ff max 65532\[r0\]\.ub, r0 + 117: fc 12 0f fc ff max 65532\[r0\]\.ub, r15 + 11c: 06 22 04 00 fc ff max 65532\[r0\]\.b, r0 + 122: 06 22 04 0f fc ff max 65532\[r0\]\.b, r15 + 128: 06 e2 04 00 fe 7f max 65532\[r0\]\.uw, r0 + 12e: 06 e2 04 0f fe 7f max 65532\[r0\]\.uw, r15 + 134: 06 62 04 00 fe 7f max 65532\[r0\]\.w, r0 + 13a: 06 62 04 0f fe 7f max 65532\[r0\]\.w, r15 + 140: 06 a2 04 00 ff 3f max 65532\[r0\]\.l, r0 + 146: 06 a2 04 0f ff 3f max 65532\[r0\]\.l, r15 + 14c: fc 12 f0 fc ff max 65532\[r15\]\.ub, r0 + 151: fc 12 ff fc ff max 65532\[r15\]\.ub, r15 + 156: 06 22 04 f0 fc ff max 65532\[r15\]\.b, r0 + 15c: 06 22 04 ff fc ff max 65532\[r15\]\.b, r15 + 162: 06 e2 04 f0 fe 7f max 65532\[r15\]\.uw, r0 + 168: 06 e2 04 ff fe 7f max 65532\[r15\]\.uw, r15 + 16e: 06 62 04 f0 fe 7f max 65532\[r15\]\.w, r0 + 174: 06 62 04 ff fe 7f max 65532\[r15\]\.w, r15 + 17a: 06 a2 04 f0 ff 3f max 65532\[r15\]\.l, r0 + 180: 06 a2 04 ff ff 3f max 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/max.sm b/gas/testsuite/gas/rx/max.sm new file mode 100644 index 00000000000..eb8b7ac2dcf --- /dev/null +++ b/gas/testsuite/gas/rx/max.sm @@ -0,0 +1,3 @@ + max #{imm},{reg} + max {reg},{reg} + max {memx},{reg} diff --git a/gas/testsuite/gas/rx/min.d b/gas/testsuite/gas/rx/min.d new file mode 100644 index 00000000000..f00a34b9a20 --- /dev/null +++ b/gas/testsuite/gas/rx/min.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 50 80 min #-128, r0 + 4: fd 74 5f 80 min #-128, r15 + 8: fd 74 50 7f min #127, r0 + c: fd 74 5f 7f min #127, r15 + 10: fd 78 50 00 80 min #0xffff8000, r0 + 15: fd 78 5f 00 80 min #0xffff8000, r15 + 1a: fd 7c 50 00 80 00 min #0x8000, r0 + 20: fd 7c 5f 00 80 00 min #0x8000, r15 + 26: fd 7c 50 00 00 80 min #0xff800000, r0 + 2c: fd 7c 5f 00 00 80 min #0xff800000, r15 + 32: fd 7c 50 ff ff 7f min #0x7fffff, r0 + 38: fd 7c 5f ff ff 7f min #0x7fffff, r15 + 3e: fd 70 50 00 00 00 80 min #0x80000000, r0 + 45: fd 70 5f 00 00 00 80 min #0x80000000, r15 + 4c: fd 70 50 ff ff ff 7f min #0x7fffffff, r0 + 53: fd 70 5f ff ff ff 7f min #0x7fffffff, r15 + 5a: fc 17 00 min r0, r0 + 5d: fc 17 0f min r0, r15 + 60: fc 17 f0 min r15, r0 + 63: fc 17 ff min r15, r15 + 66: fc 14 00 min \[r0\]\.ub, r0 + 69: fc 14 0f min \[r0\]\.ub, r15 + 6c: 06 20 05 00 min \[r0\]\.b, r0 + 70: 06 20 05 0f min \[r0\]\.b, r15 + 74: 06 e0 05 00 min \[r0\]\.uw, r0 + 78: 06 e0 05 0f min \[r0\]\.uw, r15 + 7c: 06 60 05 00 min \[r0\]\.w, r0 + 80: 06 60 05 0f min \[r0\]\.w, r15 + 84: 06 a0 05 00 min \[r0\]\.l, r0 + 88: 06 a0 05 0f min \[r0\]\.l, r15 + 8c: fc 14 f0 min \[r15\]\.ub, r0 + 8f: fc 14 ff min \[r15\]\.ub, r15 + 92: 06 20 05 f0 min \[r15\]\.b, r0 + 96: 06 20 05 ff min \[r15\]\.b, r15 + 9a: 06 e0 05 f0 min \[r15\]\.uw, r0 + 9e: 06 e0 05 ff min \[r15\]\.uw, r15 + a2: 06 60 05 f0 min \[r15\]\.w, r0 + a6: 06 60 05 ff min \[r15\]\.w, r15 + aa: 06 a0 05 f0 min \[r15\]\.l, r0 + ae: 06 a0 05 ff min \[r15\]\.l, r15 + b2: fc 15 00 fc min 252\[r0\]\.ub, r0 + b6: fc 15 0f fc min 252\[r0\]\.ub, r15 + ba: 06 21 05 00 fc min 252\[r0\]\.b, r0 + bf: 06 21 05 0f fc min 252\[r0\]\.b, r15 + c4: 06 e1 05 00 7e min 252\[r0\]\.uw, r0 + c9: 06 e1 05 0f 7e min 252\[r0\]\.uw, r15 + ce: 06 61 05 00 7e min 252\[r0\]\.w, r0 + d3: 06 61 05 0f 7e min 252\[r0\]\.w, r15 + d8: 06 a1 05 00 3f min 252\[r0\]\.l, r0 + dd: 06 a1 05 0f 3f min 252\[r0\]\.l, r15 + e2: fc 15 f0 fc min 252\[r15\]\.ub, r0 + e6: fc 15 ff fc min 252\[r15\]\.ub, r15 + ea: 06 21 05 f0 fc min 252\[r15\]\.b, r0 + ef: 06 21 05 ff fc min 252\[r15\]\.b, r15 + f4: 06 e1 05 f0 7e min 252\[r15\]\.uw, r0 + f9: 06 e1 05 ff 7e min 252\[r15\]\.uw, r15 + fe: 06 61 05 f0 7e min 252\[r15\]\.w, r0 + 103: 06 61 05 ff 7e min 252\[r15\]\.w, r15 + 108: 06 a1 05 f0 3f min 252\[r15\]\.l, r0 + 10d: 06 a1 05 ff 3f min 252\[r15\]\.l, r15 + 112: fc 16 00 fc ff min 65532\[r0\]\.ub, r0 + 117: fc 16 0f fc ff min 65532\[r0\]\.ub, r15 + 11c: 06 22 05 00 fc ff min 65532\[r0\]\.b, r0 + 122: 06 22 05 0f fc ff min 65532\[r0\]\.b, r15 + 128: 06 e2 05 00 fe 7f min 65532\[r0\]\.uw, r0 + 12e: 06 e2 05 0f fe 7f min 65532\[r0\]\.uw, r15 + 134: 06 62 05 00 fe 7f min 65532\[r0\]\.w, r0 + 13a: 06 62 05 0f fe 7f min 65532\[r0\]\.w, r15 + 140: 06 a2 05 00 ff 3f min 65532\[r0\]\.l, r0 + 146: 06 a2 05 0f ff 3f min 65532\[r0\]\.l, r15 + 14c: fc 16 f0 fc ff min 65532\[r15\]\.ub, r0 + 151: fc 16 ff fc ff min 65532\[r15\]\.ub, r15 + 156: 06 22 05 f0 fc ff min 65532\[r15\]\.b, r0 + 15c: 06 22 05 ff fc ff min 65532\[r15\]\.b, r15 + 162: 06 e2 05 f0 fe 7f min 65532\[r15\]\.uw, r0 + 168: 06 e2 05 ff fe 7f min 65532\[r15\]\.uw, r15 + 16e: 06 62 05 f0 fe 7f min 65532\[r15\]\.w, r0 + 174: 06 62 05 ff fe 7f min 65532\[r15\]\.w, r15 + 17a: 06 a2 05 f0 ff 3f min 65532\[r15\]\.l, r0 + 180: 06 a2 05 ff ff 3f min 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/min.sm b/gas/testsuite/gas/rx/min.sm new file mode 100644 index 00000000000..e735a64595d --- /dev/null +++ b/gas/testsuite/gas/rx/min.sm @@ -0,0 +1,3 @@ + min #{imm},{reg} + min {reg},{reg} + min {memx},{reg} diff --git a/gas/testsuite/gas/rx/mov.d b/gas/testsuite/gas/rx/mov.d new file mode 100644 index 00000000000..71dfc0acf63 --- /dev/null +++ b/gas/testsuite/gas/rx/mov.d @@ -0,0 +1,476 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 81 00 mov\.b r0, 4\[r0\] + 2: 81 70 mov\.b r0, 4\[r7\] + 4: 87 00 mov\.b r0, 28\[r0\] + 6: 87 70 mov\.b r0, 28\[r7\] + 8: 81 07 mov\.b r7, 4\[r0\] + a: 81 77 mov\.b r7, 4\[r7\] + c: 87 07 mov\.b r7, 28\[r0\] + e: 87 77 mov\.b r7, 28\[r7\] + 10: 90 80 mov\.w r0, 4\[r0\] + 12: 90 f0 mov\.w r0, 4\[r7\] + 14: 93 80 mov\.w r0, 28\[r0\] + 16: 93 f0 mov\.w r0, 28\[r7\] + 18: 90 87 mov\.w r7, 4\[r0\] + 1a: 90 f7 mov\.w r7, 4\[r7\] + 1c: 93 87 mov\.w r7, 28\[r0\] + 1e: 93 f7 mov\.w r7, 28\[r7\] + 20: a0 08 mov\.l r0, 4\[r0\] + 22: a0 78 mov\.l r0, 4\[r7\] + 24: a1 88 mov\.l r0, 28\[r0\] + 26: a1 f8 mov\.l r0, 28\[r7\] + 28: a0 0f mov\.l r7, 4\[r0\] + 2a: a0 7f mov\.l r7, 4\[r7\] + 2c: a1 8f mov\.l r7, 28\[r0\] + 2e: a1 ff mov\.l r7, 28\[r7\] + 30: 89 00 mov\.b 4\[r0\], r0 + 32: 89 07 mov\.b 4\[r0\], r7 + 34: 89 70 mov\.b 4\[r7\], r0 + 36: 89 77 mov\.b 4\[r7\], r7 + 38: 8f 00 mov\.b 28\[r0\], r0 + 3a: 8f 07 mov\.b 28\[r0\], r7 + 3c: 8f 70 mov\.b 28\[r7\], r0 + 3e: 8f 77 mov\.b 28\[r7\], r7 + 40: 98 80 mov\.w 4\[r0\], r0 + 42: 98 87 mov\.w 4\[r0\], r7 + 44: 98 f0 mov\.w 4\[r7\], r0 + 46: 98 f7 mov\.w 4\[r7\], r7 + 48: 9b 80 mov\.w 28\[r0\], r0 + 4a: 9b 87 mov\.w 28\[r0\], r7 + 4c: 9b f0 mov\.w 28\[r7\], r0 + 4e: 9b f7 mov\.w 28\[r7\], r7 + 50: a8 08 mov\.l 4\[r0\], r0 + 52: a8 0f mov\.l 4\[r0\], r7 + 54: a8 78 mov\.l 4\[r7\], r0 + 56: a8 7f mov\.l 4\[r7\], r7 + 58: a9 88 mov\.l 28\[r0\], r0 + 5a: a9 8f mov\.l 28\[r0\], r7 + 5c: a9 f8 mov\.l 28\[r7\], r0 + 5e: a9 ff mov\.l 28\[r7\], r7 + 60: 66 00 mov\.l #0, r0 + 62: 66 0f mov\.l #0, r15 + 64: 66 f0 mov\.l #15, r0 + 66: 66 ff mov\.l #15, r15 + 68: f9 04 04 80 mov\.b #-128, 4\[r0\] + 6c: f9 74 04 80 mov\.b #-128, 4\[r7\] + 70: f9 04 1c 80 mov\.b #-128, 28\[r0\] + 74: f9 74 1c 80 mov\.b #-128, 28\[r7\] + 78: 3c 04 7f mov\.b #127, 4\[r0\] + 7b: 3c 74 7f mov\.b #127, 4\[r7\] + 7e: 3c 8c 7f mov\.b #127, 28\[r0\] + 81: 3c fc 7f mov\.b #127, 28\[r7\] + 84: 3d 02 00 mov\.w #0, 4\[r0\] + 87: 3d 72 00 mov\.w #0, 4\[r7\] + 8a: 3d 0e 00 mov\.w #0, 28\[r0\] + 8d: 3d 7e 00 mov\.w #0, 28\[r7\] + 90: 3d 02 ff mov\.w #255, 4\[r0\] + 93: 3d 72 ff mov\.w #255, 4\[r7\] + 96: 3d 0e ff mov\.w #255, 28\[r0\] + 99: 3d 7e ff mov\.w #255, 28\[r7\] + 9c: 3e 01 00 mov\.l #0, 4\[r0\] + 9f: 3e 71 00 mov\.l #0, 4\[r7\] + a2: 3e 07 00 mov\.l #0, 28\[r0\] + a5: 3e 77 00 mov\.l #0, 28\[r7\] + a8: 3e 01 ff mov\.l #255, 4\[r0\] + ab: 3e 71 ff mov\.l #255, 4\[r7\] + ae: 3e 07 ff mov\.l #255, 28\[r0\] + b1: 3e 77 ff mov\.l #255, 28\[r7\] + b4: 66 00 mov\.l #0, r0 + b6: 66 0f mov\.l #0, r15 + b8: 75 40 ff mov\.l #255, r0 + bb: 75 4f ff mov\.l #255, r15 + be: fb 06 80 mov\.l #-128, r0 + c1: fb f6 80 mov\.l #-128, r15 + c4: 75 40 7f mov\.l #127, r0 + c7: 75 4f 7f mov\.l #127, r15 + ca: fb 0a 00 80 mov\.l #0xffff8000, r0 + ce: fb fa 00 80 mov\.l #0xffff8000, r15 + d2: fb 0e 00 80 00 mov\.l #0x8000, r0 + d7: fb fe 00 80 00 mov\.l #0x8000, r15 + dc: fb 0e 00 00 80 mov\.l #0xff800000, r0 + e1: fb fe 00 00 80 mov\.l #0xff800000, r15 + e6: fb 0e ff ff 7f mov\.l #0x7fffff, r0 + eb: fb fe ff ff 7f mov\.l #0x7fffff, r15 + f0: fb 02 00 00 00 80 mov\.l #0x80000000, r0 + f6: fb f2 00 00 00 80 mov\.l #0x80000000, r15 + fc: fb 02 ff ff ff 7f mov\.l #0x7fffffff, r0 + 102: fb f2 ff ff ff 7f mov\.l #0x7fffffff, r15 + 108: cf 00 mov\.b r0, r0 + 10a: cf 0f mov\.b r0, r15 + 10c: cf f0 mov\.b r15, r0 + 10e: cf ff mov\.b r15, r15 + 110: df 00 mov\.w r0, r0 + 112: df 0f mov\.w r0, r15 + 114: df f0 mov\.w r15, r0 + 116: df ff mov\.w r15, r15 + 118: ef 00 mov\.l r0, r0 + 11a: ef 0f mov\.l r0, r15 + 11c: ef f0 mov\.l r15, r0 + 11e: ef ff mov\.l r15, r15 + 120: 3c 00 00 mov\.b #0, \[r0\] + 123: f8 f4 00 mov\.b #0, \[r15\] + 126: f9 04 fc 00 mov\.b #0, 252\[r0\] + 12a: f9 f4 fc 00 mov\.b #0, 252\[r15\] + 12e: fa 04 fc ff 00 mov\.b #0, 65532\[r0\] + 133: fa f4 fc ff 00 mov\.b #0, 65532\[r15\] + 138: 3c 00 ff mov\.b #255, \[r0\] + 13b: f8 f4 ff mov\.b #-1, \[r15\] + 13e: f9 04 fc ff mov\.b #-1, 252\[r0\] + 142: f9 f4 fc ff mov\.b #-1, 252\[r15\] + 146: fa 04 fc ff ff mov\.b #-1, 65532\[r0\] + 14b: fa f4 fc ff ff mov\.b #-1, 65532\[r15\] + 150: f8 05 80 mov\.w #-128, \[r0\] + 153: f8 f5 80 mov\.w #-128, \[r15\] + 156: f9 05 7e 80 mov\.w #-128, 252\[r0\] + 15a: f9 f5 7e 80 mov\.w #-128, 252\[r15\] + 15e: fa 05 fe 7f 80 mov\.w #-128, 65532\[r0\] + 163: fa f5 fe 7f 80 mov\.w #-128, 65532\[r15\] + 168: 3d 00 7f mov\.w #127, \[r0\] + 16b: f8 f5 7f mov\.w #127, \[r15\] + 16e: f9 05 7e 7f mov\.w #127, 252\[r0\] + 172: f9 f5 7e 7f mov\.w #127, 252\[r15\] + 176: fa 05 fe 7f 7f mov\.w #127, 65532\[r0\] + 17b: fa f5 fe 7f 7f mov\.w #127, 65532\[r15\] + 180: 3d 00 00 mov\.w #0, \[r0\] + 183: f8 f5 00 mov\.w #0, \[r15\] + 186: f9 05 7e 00 mov\.w #0, 252\[r0\] + 18a: f9 f5 7e 00 mov\.w #0, 252\[r15\] + 18e: fa 05 fe 7f 00 mov\.w #0, 65532\[r0\] + 193: fa f5 fe 7f 00 mov\.w #0, 65532\[r15\] + 198: f8 0d ff ff 00 mov\.w #0xffff, \[r0\] + 19d: f8 fd ff ff 00 mov\.w #0xffff, \[r15\] + 1a2: f9 0d 7e ff ff 00 mov\.w #0xffff, 252\[r0\] + 1a8: f9 fd 7e ff ff 00 mov\.w #0xffff, 252\[r15\] + 1ae: fa 0d fe 7f ff ff 00 mov\.w #0xffff, 65532\[r0\] + 1b5: fa fd fe 7f ff ff 00 mov\.w #0xffff, 65532\[r15\] + 1bc: f8 06 80 mov\.l #-128, \[r0\] + 1bf: f8 f6 80 mov\.l #-128, \[r15\] + 1c2: f9 06 3f 80 mov\.l #-128, 252\[r0\] + 1c6: f9 f6 3f 80 mov\.l #-128, 252\[r15\] + 1ca: fa 06 ff 3f 80 mov\.l #-128, 65532\[r0\] + 1cf: fa f6 ff 3f 80 mov\.l #-128, 65532\[r15\] + 1d4: 3e 00 7f mov\.l #127, \[r0\] + 1d7: f8 f6 7f mov\.l #127, \[r15\] + 1da: f9 06 3f 7f mov\.l #127, 252\[r0\] + 1de: f9 f6 3f 7f mov\.l #127, 252\[r15\] + 1e2: fa 06 ff 3f 7f mov\.l #127, 65532\[r0\] + 1e7: fa f6 ff 3f 7f mov\.l #127, 65532\[r15\] + 1ec: f8 0a 00 80 mov\.l #0xffff8000, \[r0\] + 1f0: f8 fa 00 80 mov\.l #0xffff8000, \[r15\] + 1f4: f9 0a 3f 00 80 mov\.l #0xffff8000, 252\[r0\] + 1f9: f9 fa 3f 00 80 mov\.l #0xffff8000, 252\[r15\] + 1fe: fa 0a ff 3f 00 80 mov\.l #0xffff8000, 65532\[r0\] + 204: fa fa ff 3f 00 80 mov\.l #0xffff8000, 65532\[r15\] + 20a: f8 0e 00 80 00 mov\.l #0x8000, \[r0\] + 20f: f8 fe 00 80 00 mov\.l #0x8000, \[r15\] + 214: f9 0e 3f 00 80 00 mov\.l #0x8000, 252\[r0\] + 21a: f9 fe 3f 00 80 00 mov\.l #0x8000, 252\[r15\] + 220: fa 0e ff 3f 00 80 00 mov\.l #0x8000, 65532\[r0\] + 227: fa fe ff 3f 00 80 00 mov\.l #0x8000, 65532\[r15\] + 22e: f8 0e 00 00 80 mov\.l #0xff800000, \[r0\] + 233: f8 fe 00 00 80 mov\.l #0xff800000, \[r15\] + 238: f9 0e 3f 00 00 80 mov\.l #0xff800000, 252\[r0\] + 23e: f9 fe 3f 00 00 80 mov\.l #0xff800000, 252\[r15\] + 244: fa 0e ff 3f 00 00 80 mov\.l #0xff800000, 65532\[r0\] + 24b: fa fe ff 3f 00 00 80 mov\.l #0xff800000, 65532\[r15\] + 252: f8 0e ff ff 7f mov\.l #0x7fffff, \[r0\] + 257: f8 fe ff ff 7f mov\.l #0x7fffff, \[r15\] + 25c: f9 0e 3f ff ff 7f mov\.l #0x7fffff, 252\[r0\] + 262: f9 fe 3f ff ff 7f mov\.l #0x7fffff, 252\[r15\] + 268: fa 0e ff 3f ff ff 7f mov\.l #0x7fffff, 65532\[r0\] + 26f: fa fe ff 3f ff ff 7f mov\.l #0x7fffff, 65532\[r15\] + 276: f8 02 00 00 00 80 mov\.l #0x80000000, \[r0\] + 27c: f8 f2 00 00 00 80 mov\.l #0x80000000, \[r15\] + 282: f9 02 3f 00 00 00 80 mov\.l #0x80000000, 252\[r0\] + 289: f9 f2 3f 00 00 00 80 mov\.l #0x80000000, 252\[r15\] + 290: fa 02 ff 3f 00 00 00 80 mov\.l #0x80000000, 65532\[r0\] + 298: fa f2 ff 3f 00 00 00 80 mov\.l #0x80000000, 65532\[r15\] + 2a0: f8 02 ff ff ff 7f mov\.l #0x7fffffff, \[r0\] + 2a6: f8 f2 ff ff ff 7f mov\.l #0x7fffffff, \[r15\] + 2ac: f9 02 3f ff ff ff 7f mov\.l #0x7fffffff, 252\[r0\] + 2b3: f9 f2 3f ff ff ff 7f mov\.l #0x7fffffff, 252\[r15\] + 2ba: fa 02 ff 3f ff ff ff 7f mov\.l #0x7fffffff, 65532\[r0\] + 2c2: fa f2 ff 3f ff ff ff 7f mov\.l #0x7fffffff, 65532\[r15\] + 2ca: cc 00 mov\.b \[r0\], r0 + 2cc: cc 0f mov\.b \[r0\], r15 + 2ce: cc f0 mov\.b \[r15\], r0 + 2d0: cc ff mov\.b \[r15\], r15 + 2d2: cd 00 fc mov\.b 252\[r0\], r0 + 2d5: cd 0f fc mov\.b 252\[r0\], r15 + 2d8: cd f0 fc mov\.b 252\[r15\], r0 + 2db: cd ff fc mov\.b 252\[r15\], r15 + 2de: ce 00 fc ff mov\.b 65532\[r0\], r0 + 2e2: ce 0f fc ff mov\.b 65532\[r0\], r15 + 2e6: ce f0 fc ff mov\.b 65532\[r15\], r0 + 2ea: ce ff fc ff mov\.b 65532\[r15\], r15 + 2ee: dc 00 mov\.w \[r0\], r0 + 2f0: dc 0f mov\.w \[r0\], r15 + 2f2: dc f0 mov\.w \[r15\], r0 + 2f4: dc ff mov\.w \[r15\], r15 + 2f6: dd 00 7e mov\.w 252\[r0\], r0 + 2f9: dd 0f 7e mov\.w 252\[r0\], r15 + 2fc: dd f0 7e mov\.w 252\[r15\], r0 + 2ff: dd ff 7e mov\.w 252\[r15\], r15 + 302: de 00 fe 7f mov\.w 65532\[r0\], r0 + 306: de 0f fe 7f mov\.w 65532\[r0\], r15 + 30a: de f0 fe 7f mov\.w 65532\[r15\], r0 + 30e: de ff fe 7f mov\.w 65532\[r15\], r15 + 312: ec 00 mov\.l \[r0\], r0 + 314: ec 0f mov\.l \[r0\], r15 + 316: ec f0 mov\.l \[r15\], r0 + 318: ec ff mov\.l \[r15\], r15 + 31a: ed 00 3f mov\.l 252\[r0\], r0 + 31d: ed 0f 3f mov\.l 252\[r0\], r15 + 320: ed f0 3f mov\.l 252\[r15\], r0 + 323: ed ff 3f mov\.l 252\[r15\], r15 + 326: ee 00 ff 3f mov\.l 65532\[r0\], r0 + 32a: ee 0f ff 3f mov\.l 65532\[r0\], r15 + 32e: ee f0 ff 3f mov\.l 65532\[r15\], r0 + 332: ee ff ff 3f mov\.l 65532\[r15\], r15 + 336: fe 40 00 mov\.b \[r0, r0\], r0 + 339: fe 40 0f mov\.b \[r0, r0\], r15 + 33c: fe 40 f0 mov\.b \[r0, r15\], r0 + 33f: fe 40 ff mov\.b \[r0, r15\], r15 + 342: fe 4f 00 mov\.b \[r15, r0\], r0 + 345: fe 4f 0f mov\.b \[r15, r0\], r15 + 348: fe 4f f0 mov\.b \[r15, r15\], r0 + 34b: fe 4f ff mov\.b \[r15, r15\], r15 + 34e: fe 50 00 mov\.w \[r0, r0\], r0 + 351: fe 50 0f mov\.w \[r0, r0\], r15 + 354: fe 50 f0 mov\.w \[r0, r15\], r0 + 357: fe 50 ff mov\.w \[r0, r15\], r15 + 35a: fe 5f 00 mov\.w \[r15, r0\], r0 + 35d: fe 5f 0f mov\.w \[r15, r0\], r15 + 360: fe 5f f0 mov\.w \[r15, r15\], r0 + 363: fe 5f ff mov\.w \[r15, r15\], r15 + 366: fe 60 00 mov\.l \[r0, r0\], r0 + 369: fe 60 0f mov\.l \[r0, r0\], r15 + 36c: fe 60 f0 mov\.l \[r0, r15\], r0 + 36f: fe 60 ff mov\.l \[r0, r15\], r15 + 372: fe 6f 00 mov\.l \[r15, r0\], r0 + 375: fe 6f 0f mov\.l \[r15, r0\], r15 + 378: fe 6f f0 mov\.l \[r15, r15\], r0 + 37b: fe 6f ff mov\.l \[r15, r15\], r15 + 37e: c3 00 mov\.b r0, \[r0\] + 380: c3 f0 mov\.b r0, \[r15\] + 382: c7 00 fc mov\.b r0, 252\[r0\] + 385: c7 f0 fc mov\.b r0, 252\[r15\] + 388: cb 00 fc ff mov\.b r0, 65532\[r0\] + 38c: cb f0 fc ff mov\.b r0, 65532\[r15\] + 390: c3 0f mov\.b r15, \[r0\] + 392: c3 ff mov\.b r15, \[r15\] + 394: c7 0f fc mov\.b r15, 252\[r0\] + 397: c7 ff fc mov\.b r15, 252\[r15\] + 39a: cb 0f fc ff mov\.b r15, 65532\[r0\] + 39e: cb ff fc ff mov\.b r15, 65532\[r15\] + 3a2: d3 00 mov\.w r0, \[r0\] + 3a4: d3 f0 mov\.w r0, \[r15\] + 3a6: d7 00 7e mov\.w r0, 252\[r0\] + 3a9: d7 f0 7e mov\.w r0, 252\[r15\] + 3ac: db 00 fe 7f mov\.w r0, 65532\[r0\] + 3b0: db f0 fe 7f mov\.w r0, 65532\[r15\] + 3b4: d3 0f mov\.w r15, \[r0\] + 3b6: d3 ff mov\.w r15, \[r15\] + 3b8: d7 0f 7e mov\.w r15, 252\[r0\] + 3bb: d7 ff 7e mov\.w r15, 252\[r15\] + 3be: db 0f fe 7f mov\.w r15, 65532\[r0\] + 3c2: db ff fe 7f mov\.w r15, 65532\[r15\] + 3c6: e3 00 mov\.l r0, \[r0\] + 3c8: e3 f0 mov\.l r0, \[r15\] + 3ca: e7 00 3f mov\.l r0, 252\[r0\] + 3cd: e7 f0 3f mov\.l r0, 252\[r15\] + 3d0: eb 00 ff 3f mov\.l r0, 65532\[r0\] + 3d4: eb f0 ff 3f mov\.l r0, 65532\[r15\] + 3d8: e3 0f mov\.l r15, \[r0\] + 3da: e3 ff mov\.l r15, \[r15\] + 3dc: e7 0f 3f mov\.l r15, 252\[r0\] + 3df: e7 ff 3f mov\.l r15, 252\[r15\] + 3e2: eb 0f ff 3f mov\.l r15, 65532\[r0\] + 3e6: eb ff ff 3f mov\.l r15, 65532\[r15\] + 3ea: fe 00 00 mov\.b r0, \[r0, r0\] + 3ed: fe 00 f0 mov\.b r0, \[r0, r15\] + 3f0: fe 0f 00 mov\.b r0, \[r15, r0\] + 3f3: fe 0f f0 mov\.b r0, \[r15, r15\] + 3f6: fe 00 0f mov\.b r15, \[r0, r0\] + 3f9: fe 00 ff mov\.b r15, \[r0, r15\] + 3fc: fe 0f 0f mov\.b r15, \[r15, r0\] + 3ff: fe 0f ff mov\.b r15, \[r15, r15\] + 402: fe 10 00 mov\.w r0, \[r0, r0\] + 405: fe 10 f0 mov\.w r0, \[r0, r15\] + 408: fe 1f 00 mov\.w r0, \[r15, r0\] + 40b: fe 1f f0 mov\.w r0, \[r15, r15\] + 40e: fe 10 0f mov\.w r15, \[r0, r0\] + 411: fe 10 ff mov\.w r15, \[r0, r15\] + 414: fe 1f 0f mov\.w r15, \[r15, r0\] + 417: fe 1f ff mov\.w r15, \[r15, r15\] + 41a: fe 20 00 mov\.l r0, \[r0, r0\] + 41d: fe 20 f0 mov\.l r0, \[r0, r15\] + 420: fe 2f 00 mov\.l r0, \[r15, r0\] + 423: fe 2f f0 mov\.l r0, \[r15, r15\] + 426: fe 20 0f mov\.l r15, \[r0, r0\] + 429: fe 20 ff mov\.l r15, \[r0, r15\] + 42c: fe 2f 0f mov\.l r15, \[r15, r0\] + 42f: fe 2f ff mov\.l r15, \[r15, r15\] + 432: c0 00 mov\.b \[r0\], \[r0\] + 434: c0 0f mov\.b \[r0\], \[r15\] + 436: c4 00 fc mov\.b \[r0\], 252\[r0\] + 439: c4 0f fc mov\.b \[r0\], 252\[r15\] + 43c: c8 00 fc ff mov\.b \[r0\], 65532\[r0\] + 440: c8 0f fc ff mov\.b \[r0\], 65532\[r15\] + 444: c0 f0 mov\.b \[r15\], \[r0\] + 446: c0 ff mov\.b \[r15\], \[r15\] + 448: c4 f0 fc mov\.b \[r15\], 252\[r0\] + 44b: c4 ff fc mov\.b \[r15\], 252\[r15\] + 44e: c8 f0 fc ff mov\.b \[r15\], 65532\[r0\] + 452: c8 ff fc ff mov\.b \[r15\], 65532\[r15\] + 456: c1 00 fc mov\.b 252\[r0\], \[r0\] + 459: c1 0f fc mov\.b 252\[r0\], \[r15\] + 45c: c5 00 fc fc mov\.b 252\[r0\], 252\[r0\] + 460: c5 0f fc fc mov\.b 252\[r0\], 252\[r15\] + 464: c9 00 fc fc ff mov\.b 252\[r0\], 65532\[r0\] + 469: c9 0f fc fc ff mov\.b 252\[r0\], 65532\[r15\] + 46e: c1 f0 fc mov\.b 252\[r15\], \[r0\] + 471: c1 ff fc mov\.b 252\[r15\], \[r15\] + 474: c5 f0 fc fc mov\.b 252\[r15\], 252\[r0\] + 478: c5 ff fc fc mov\.b 252\[r15\], 252\[r15\] + 47c: c9 f0 fc fc ff mov\.b 252\[r15\], 65532\[r0\] + 481: c9 ff fc fc ff mov\.b 252\[r15\], 65532\[r15\] + 486: c2 00 fc ff mov\.b 65532\[r0\], \[r0\] + 48a: c2 0f fc ff mov\.b 65532\[r0\], \[r15\] + 48e: c6 00 fc ff fc mov\.b 65532\[r0\], 252\[r0\] + 493: c6 0f fc ff fc mov\.b 65532\[r0\], 252\[r15\] + 498: ca 00 fc ff fc ff mov\.b 65532\[r0\], 65532\[r0\] + 49e: ca 0f fc ff fc ff mov\.b 65532\[r0\], 65532\[r15\] + 4a4: c2 f0 fc ff mov\.b 65532\[r15\], \[r0\] + 4a8: c2 ff fc ff mov\.b 65532\[r15\], \[r15\] + 4ac: c6 f0 fc ff fc mov\.b 65532\[r15\], 252\[r0\] + 4b1: c6 ff fc ff fc mov\.b 65532\[r15\], 252\[r15\] + 4b6: ca f0 fc ff fc ff mov\.b 65532\[r15\], 65532\[r0\] + 4bc: ca ff fc ff fc ff mov\.b 65532\[r15\], 65532\[r15\] + 4c2: d0 00 mov\.w \[r0\], \[r0\] + 4c4: d0 0f mov\.w \[r0\], \[r15\] + 4c6: d4 00 7e mov\.w \[r0\], 252\[r0\] + 4c9: d4 0f 7e mov\.w \[r0\], 252\[r15\] + 4cc: d8 00 fe 7f mov\.w \[r0\], 65532\[r0\] + 4d0: d8 0f fe 7f mov\.w \[r0\], 65532\[r15\] + 4d4: d0 f0 mov\.w \[r15\], \[r0\] + 4d6: d0 ff mov\.w \[r15\], \[r15\] + 4d8: d4 f0 7e mov\.w \[r15\], 252\[r0\] + 4db: d4 ff 7e mov\.w \[r15\], 252\[r15\] + 4de: d8 f0 fe 7f mov\.w \[r15\], 65532\[r0\] + 4e2: d8 ff fe 7f mov\.w \[r15\], 65532\[r15\] + 4e6: d1 00 7e mov\.w 252\[r0\], \[r0\] + 4e9: d1 0f 7e mov\.w 252\[r0\], \[r15\] + 4ec: d5 00 7e 7e mov\.w 252\[r0\], 252\[r0\] + 4f0: d5 0f 7e 7e mov\.w 252\[r0\], 252\[r15\] + 4f4: d9 00 7e fe 7f mov\.w 252\[r0\], 65532\[r0\] + 4f9: d9 0f 7e fe 7f mov\.w 252\[r0\], 65532\[r15\] + 4fe: d1 f0 7e mov\.w 252\[r15\], \[r0\] + 501: d1 ff 7e mov\.w 252\[r15\], \[r15\] + 504: d5 f0 7e 7e mov\.w 252\[r15\], 252\[r0\] + 508: d5 ff 7e 7e mov\.w 252\[r15\], 252\[r15\] + 50c: d9 f0 7e fe 7f mov\.w 252\[r15\], 65532\[r0\] + 511: d9 ff 7e fe 7f mov\.w 252\[r15\], 65532\[r15\] + 516: d2 00 fe 7f mov\.w 65532\[r0\], \[r0\] + 51a: d2 0f fe 7f mov\.w 65532\[r0\], \[r15\] + 51e: d6 00 fe 7f 7e mov\.w 65532\[r0\], 252\[r0\] + 523: d6 0f fe 7f 7e mov\.w 65532\[r0\], 252\[r15\] + 528: da 00 fe 7f fe 7f mov\.w 65532\[r0\], 65532\[r0\] + 52e: da 0f fe 7f fe 7f mov\.w 65532\[r0\], 65532\[r15\] + 534: d2 f0 fe 7f mov\.w 65532\[r15\], \[r0\] + 538: d2 ff fe 7f mov\.w 65532\[r15\], \[r15\] + 53c: d6 f0 fe 7f 7e mov\.w 65532\[r15\], 252\[r0\] + 541: d6 ff fe 7f 7e mov\.w 65532\[r15\], 252\[r15\] + 546: da f0 fe 7f fe 7f mov\.w 65532\[r15\], 65532\[r0\] + 54c: da ff fe 7f fe 7f mov\.w 65532\[r15\], 65532\[r15\] + 552: e0 00 mov\.l \[r0\], \[r0\] + 554: e0 0f mov\.l \[r0\], \[r15\] + 556: e4 00 3f mov\.l \[r0\], 252\[r0\] + 559: e4 0f 3f mov\.l \[r0\], 252\[r15\] + 55c: e8 00 ff 3f mov\.l \[r0\], 65532\[r0\] + 560: e8 0f ff 3f mov\.l \[r0\], 65532\[r15\] + 564: e0 f0 mov\.l \[r15\], \[r0\] + 566: e0 ff mov\.l \[r15\], \[r15\] + 568: e4 f0 3f mov\.l \[r15\], 252\[r0\] + 56b: e4 ff 3f mov\.l \[r15\], 252\[r15\] + 56e: e8 f0 ff 3f mov\.l \[r15\], 65532\[r0\] + 572: e8 ff ff 3f mov\.l \[r15\], 65532\[r15\] + 576: e1 00 3f mov\.l 252\[r0\], \[r0\] + 579: e1 0f 3f mov\.l 252\[r0\], \[r15\] + 57c: e5 00 3f 3f mov\.l 252\[r0\], 252\[r0\] + 580: e5 0f 3f 3f mov\.l 252\[r0\], 252\[r15\] + 584: e9 00 3f ff 3f mov\.l 252\[r0\], 65532\[r0\] + 589: e9 0f 3f ff 3f mov\.l 252\[r0\], 65532\[r15\] + 58e: e1 f0 3f mov\.l 252\[r15\], \[r0\] + 591: e1 ff 3f mov\.l 252\[r15\], \[r15\] + 594: e5 f0 3f 3f mov\.l 252\[r15\], 252\[r0\] + 598: e5 ff 3f 3f mov\.l 252\[r15\], 252\[r15\] + 59c: e9 f0 3f ff 3f mov\.l 252\[r15\], 65532\[r0\] + 5a1: e9 ff 3f ff 3f mov\.l 252\[r15\], 65532\[r15\] + 5a6: e2 00 ff 3f mov\.l 65532\[r0\], \[r0\] + 5aa: e2 0f ff 3f mov\.l 65532\[r0\], \[r15\] + 5ae: e6 00 ff 3f 3f mov\.l 65532\[r0\], 252\[r0\] + 5b3: e6 0f ff 3f 3f mov\.l 65532\[r0\], 252\[r15\] + 5b8: ea 00 ff 3f ff 3f mov\.l 65532\[r0\], 65532\[r0\] + 5be: ea 0f ff 3f ff 3f mov\.l 65532\[r0\], 65532\[r15\] + 5c4: e2 f0 ff 3f mov\.l 65532\[r15\], \[r0\] + 5c8: e2 ff ff 3f mov\.l 65532\[r15\], \[r15\] + 5cc: e6 f0 ff 3f 3f mov\.l 65532\[r15\], 252\[r0\] + 5d1: e6 ff ff 3f 3f mov\.l 65532\[r15\], 252\[r15\] + 5d6: ea f0 ff 3f ff 3f mov\.l 65532\[r15\], 65532\[r0\] + 5dc: ea ff ff 3f ff 3f mov\.l 65532\[r15\], 65532\[r15\] + 5e2: fd 20 00 mov\.b r0, \[r0\+\] + 5e5: fd 20 f0 mov\.b r0, \[r15\+\] + 5e8: fd 20 0f mov\.b r15, \[r0\+\] + 5eb: fd 20 ff mov\.b r15, \[r15\+\] + 5ee: fd 21 00 mov\.w r0, \[r0\+\] + 5f1: fd 21 f0 mov\.w r0, \[r15\+\] + 5f4: fd 21 0f mov\.w r15, \[r0\+\] + 5f7: fd 21 ff mov\.w r15, \[r15\+\] + 5fa: fd 22 00 mov\.l r0, \[r0\+\] + 5fd: fd 22 f0 mov\.l r0, \[r15\+\] + 600: fd 22 0f mov\.l r15, \[r0\+\] + 603: fd 22 ff mov\.l r15, \[r15\+\] + 606: fd 28 00 mov\.b \[r0\+\], r0 + 609: fd 28 0f mov\.b \[r0\+\], r15 + 60c: fd 28 f0 mov\.b \[r15\+\], r0 + 60f: fd 28 ff mov\.b \[r15\+\], r15 + 612: fd 29 00 mov\.w \[r0\+\], r0 + 615: fd 29 0f mov\.w \[r0\+\], r15 + 618: fd 29 f0 mov\.w \[r15\+\], r0 + 61b: fd 29 ff mov\.w \[r15\+\], r15 + 61e: fd 2a 00 mov\.l \[r0\+\], r0 + 621: fd 2a 0f mov\.l \[r0\+\], r15 + 624: fd 2a f0 mov\.l \[r15\+\], r0 + 627: fd 2a ff mov\.l \[r15\+\], r15 + 62a: fd 24 00 mov\.b r0, \[-r0\] + 62d: fd 24 f0 mov\.b r0, \[-r15\] + 630: fd 24 0f mov\.b r15, \[-r0\] + 633: fd 24 ff mov\.b r15, \[-r15\] + 636: fd 25 00 mov\.w r0, \[-r0\] + 639: fd 25 f0 mov\.w r0, \[-r15\] + 63c: fd 25 0f mov\.w r15, \[-r0\] + 63f: fd 25 ff mov\.w r15, \[-r15\] + 642: fd 26 00 mov\.l r0, \[-r0\] + 645: fd 26 f0 mov\.l r0, \[-r15\] + 648: fd 26 0f mov\.l r15, \[-r0\] + 64b: fd 26 ff mov\.l r15, \[-r15\] + 64e: fd 2c 00 mov\.b \[-r0\], r0 + 651: fd 2c 0f mov\.b \[-r0\], r15 + 654: fd 2c f0 mov\.b \[-r15\], r0 + 657: fd 2c ff mov\.b \[-r15\], r15 + 65a: fd 2d 00 mov\.w \[-r0\], r0 + 65d: fd 2d 0f mov\.w \[-r0\], r15 + 660: fd 2d f0 mov\.w \[-r15\], r0 + 663: fd 2d ff mov\.w \[-r15\], r15 + 666: fd 2e 00 mov\.l \[-r0\], r0 + 669: fd 2e 0f mov\.l \[-r0\], r15 + 66c: fd 2e f0 mov\.l \[-r15\], r0 + 66f: fd 2e ff mov\.l \[-r15\], r15 diff --git a/gas/testsuite/gas/rx/mov.sm b/gas/testsuite/gas/rx/mov.sm new file mode 100644 index 00000000000..8914ac72d71 --- /dev/null +++ b/gas/testsuite/gas/rx/mov.sm @@ -0,0 +1,27 @@ + mov{bwl} {reg7},{dsp5}[{reg7}] + mov{bwl} {dsp5}[{reg7}],{reg7} + mov.L #{uimm4},{reg} + mov.B #{simm8},{dsp5}[{reg7}] + mov.{W;L} #{uimm8},{dsp5}[{reg7}] + + mov.L #{uimm8},{reg} + mov.L #{imm},{reg} + mov{bwl} {reg},{reg} + + mov.B #{uimm8},{mem} + mov.W #{simm8},{mem} + mov.W #{uimm16},{mem} + mov.L #{imm},{mem} + + mov{bwl} {mem},{reg} + mov{bwl} [{reg},{reg}],{reg} + + mov{bwl} {reg},{mem} + mov{bwl} {reg},[{reg},{reg}] + + mov{bwl} {mem},{mem} + + mov{bwl} {reg},[{reg}+] + mov{bwl} [{reg}+],{reg} + mov{bwl} {reg},[-{reg}] + mov{bwl} [-{reg}],{reg} diff --git a/gas/testsuite/gas/rx/movu.d b/gas/testsuite/gas/rx/movu.d new file mode 100644 index 00000000000..5ae622f6963 --- /dev/null +++ b/gas/testsuite/gas/rx/movu.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: b1 00 movu\.b 4\[r0\], r0 + 2: b1 07 movu\.b 4\[r0\], r7 + 4: b1 70 movu\.b 4\[r7\], r0 + 6: b1 77 movu\.b 4\[r7\], r7 + 8: b7 00 movu\.b 28\[r0\], r0 + a: b7 07 movu\.b 28\[r0\], r7 + c: b7 70 movu\.b 28\[r7\], r0 + e: b7 77 movu\.b 28\[r7\], r7 + 10: b8 80 movu\.w 4\[r0\], r0 + 12: b8 87 movu\.w 4\[r0\], r7 + 14: b8 f0 movu\.w 4\[r7\], r0 + 16: b8 f7 movu\.w 4\[r7\], r7 + 18: bb 80 movu\.w 28\[r0\], r0 + 1a: bb 87 movu\.w 28\[r0\], r7 + 1c: bb f0 movu\.w 28\[r7\], r0 + 1e: bb f7 movu\.w 28\[r7\], r7 + 20: 5b 00 movu\.b r0, r0 + 22: 5b 0f movu\.b r0, r15 + 24: 5b f0 movu\.b r15, r0 + 26: 5b ff movu\.b r15, r15 + 28: 5f 00 movu\.w r0, r0 + 2a: 5f 0f movu\.w r0, r15 + 2c: 5f f0 movu\.w r15, r0 + 2e: 5f ff movu\.w r15, r15 + 30: 58 00 movu\.b \[r0\], r0 + 32: 58 0f movu\.b \[r0\], r15 + 34: 58 f0 movu\.b \[r15\], r0 + 36: 58 ff movu\.b \[r15\], r15 + 38: 59 00 fc movu\.b 252\[r0\], r0 + 3b: 59 0f fc movu\.b 252\[r0\], r15 + 3e: 59 f0 fc movu\.b 252\[r15\], r0 + 41: 59 ff fc movu\.b 252\[r15\], r15 + 44: 5a 00 fc ff movu\.b 65532\[r0\], r0 + 48: 5a 0f fc ff movu\.b 65532\[r0\], r15 + 4c: 5a f0 fc ff movu\.b 65532\[r15\], r0 + 50: 5a ff fc ff movu\.b 65532\[r15\], r15 + 54: 5c 00 movu\.w \[r0\], r0 + 56: 5c 0f movu\.w \[r0\], r15 + 58: 5c f0 movu\.w \[r15\], r0 + 5a: 5c ff movu\.w \[r15\], r15 + 5c: 5d 00 7e movu\.w 252\[r0\], r0 + 5f: 5d 0f 7e movu\.w 252\[r0\], r15 + 62: 5d f0 7e movu\.w 252\[r15\], r0 + 65: 5d ff 7e movu\.w 252\[r15\], r15 + 68: 5e 00 fe 7f movu\.w 65532\[r0\], r0 + 6c: 5e 0f fe 7f movu\.w 65532\[r0\], r15 + 70: 5e f0 fe 7f movu\.w 65532\[r15\], r0 + 74: 5e ff fe 7f movu\.w 65532\[r15\], r15 + 78: fe c0 00 movu\.b \[r0, r0\], r0 + 7b: fe c0 0f movu\.b \[r0, r0\], r15 + 7e: fe c0 f0 movu\.b \[r0, r15\], r0 + 81: fe c0 ff movu\.b \[r0, r15\], r15 + 84: fe cf 00 movu\.b \[r15, r0\], r0 + 87: fe cf 0f movu\.b \[r15, r0\], r15 + 8a: fe cf f0 movu\.b \[r15, r15\], r0 + 8d: fe cf ff movu\.b \[r15, r15\], r15 + 90: fe d0 00 movu\.w \[r0, r0\], r0 + 93: fe d0 0f movu\.w \[r0, r0\], r15 + 96: fe d0 f0 movu\.w \[r0, r15\], r0 + 99: fe d0 ff movu\.w \[r0, r15\], r15 + 9c: fe df 00 movu\.w \[r15, r0\], r0 + 9f: fe df 0f movu\.w \[r15, r0\], r15 + a2: fe df f0 movu\.w \[r15, r15\], r0 + a5: fe df ff movu\.w \[r15, r15\], r15 + a8: fd 38 00 movu\.b \[r0\+\], r0 + ab: fd 38 0f movu\.b \[r0\+\], r15 + ae: fd 38 f0 movu\.b \[r15\+\], r0 + b1: fd 38 ff movu\.b \[r15\+\], r15 + b4: fd 39 00 movu\.w \[r0\+\], r0 + b7: fd 39 0f movu\.w \[r0\+\], r15 + ba: fd 39 f0 movu\.w \[r15\+\], r0 + bd: fd 39 ff movu\.w \[r15\+\], r15 + c0: fd 3c 00 movu\.b \[-r0\], r0 + c3: fd 3c 0f movu\.b \[-r0\], r15 + c6: fd 3c f0 movu\.b \[-r15\], r0 + c9: fd 3c ff movu\.b \[-r15\], r15 + cc: fd 3d 00 movu\.w \[-r0\], r0 + cf: fd 3d 0f movu\.w \[-r0\], r15 + d2: fd 3d f0 movu\.w \[-r15\], r0 + d5: fd 3d ff movu\.w \[-r15\], r15 diff --git a/gas/testsuite/gas/rx/movu.sm b/gas/testsuite/gas/rx/movu.sm new file mode 100644 index 00000000000..b1a83bdd5f7 --- /dev/null +++ b/gas/testsuite/gas/rx/movu.sm @@ -0,0 +1,9 @@ + movu{bw} {dsp5}[{reg7}],{reg7} + + movu{bw} {reg},{reg} + + movu{bw} {mem},{reg} + movu{bw} [{reg},{reg}],{reg} + + movu{bw} [{reg}+],{reg} + movu{bw} [-{reg}],{reg} diff --git a/gas/testsuite/gas/rx/mul.d b/gas/testsuite/gas/rx/mul.d new file mode 100644 index 00000000000..55d907903c0 --- /dev/null +++ b/gas/testsuite/gas/rx/mul.d @@ -0,0 +1,100 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 63 00 mul #0, r0 + 2: 63 0f mul #0, r15 + 4: 63 f0 mul #15, r0 + 6: 63 ff mul #15, r15 + 8: 75 10 80 mul #-128, r0 + b: 75 1f 80 mul #-128, r15 + e: 75 10 7f mul #127, r0 + 11: 75 1f 7f mul #127, r15 + 14: 76 10 00 80 mul #0xffff8000, r0 + 18: 76 1f 00 80 mul #0xffff8000, r15 + 1c: 77 10 00 80 00 mul #0x8000, r0 + 21: 77 1f 00 80 00 mul #0x8000, r15 + 26: 77 10 00 00 80 mul #0xff800000, r0 + 2b: 77 1f 00 00 80 mul #0xff800000, r15 + 30: 77 10 ff ff 7f mul #0x7fffff, r0 + 35: 77 1f ff ff 7f mul #0x7fffff, r15 + 3a: 74 10 00 00 00 80 mul #0x80000000, r0 + 40: 74 1f 00 00 00 80 mul #0x80000000, r15 + 46: 74 10 ff ff ff 7f mul #0x7fffffff, r0 + 4c: 74 1f ff ff ff 7f mul #0x7fffffff, r15 + 52: 4f 00 mul r0, r0 + 54: 4f 0f mul r0, r15 + 56: 4f f0 mul r15, r0 + 58: 4f ff mul r15, r15 + 5a: 4c 00 mul \[r0\]\.ub, r0 + 5c: 4c 0f mul \[r0\]\.ub, r15 + 5e: 06 0c 00 mul \[r0\]\.b, r0 + 61: 06 0c 0f mul \[r0\]\.b, r15 + 64: 06 cc 00 mul \[r0\]\.uw, r0 + 67: 06 cc 0f mul \[r0\]\.uw, r15 + 6a: 06 4c 00 mul \[r0\]\.w, r0 + 6d: 06 4c 0f mul \[r0\]\.w, r15 + 70: 06 8c 00 mul \[r0\]\.l, r0 + 73: 06 8c 0f mul \[r0\]\.l, r15 + 76: 4c f0 mul \[r15\]\.ub, r0 + 78: 4c ff mul \[r15\]\.ub, r15 + 7a: 06 0c f0 mul \[r15\]\.b, r0 + 7d: 06 0c ff mul \[r15\]\.b, r15 + 80: 06 cc f0 mul \[r15\]\.uw, r0 + 83: 06 cc ff mul \[r15\]\.uw, r15 + 86: 06 4c f0 mul \[r15\]\.w, r0 + 89: 06 4c ff mul \[r15\]\.w, r15 + 8c: 06 8c f0 mul \[r15\]\.l, r0 + 8f: 06 8c ff mul \[r15\]\.l, r15 + 92: 4d 00 fc mul 252\[r0\]\.ub, r0 + 95: 4d 0f fc mul 252\[r0\]\.ub, r15 + 98: 06 0d 00 fc mul 252\[r0\]\.b, r0 + 9c: 06 0d 0f fc mul 252\[r0\]\.b, r15 + a0: 06 cd 00 7e mul 252\[r0\]\.uw, r0 + a4: 06 cd 0f 7e mul 252\[r0\]\.uw, r15 + a8: 06 4d 00 7e mul 252\[r0\]\.w, r0 + ac: 06 4d 0f 7e mul 252\[r0\]\.w, r15 + b0: 06 8d 00 3f mul 252\[r0\]\.l, r0 + b4: 06 8d 0f 3f mul 252\[r0\]\.l, r15 + b8: 4d f0 fc mul 252\[r15\]\.ub, r0 + bb: 4d ff fc mul 252\[r15\]\.ub, r15 + be: 06 0d f0 fc mul 252\[r15\]\.b, r0 + c2: 06 0d ff fc mul 252\[r15\]\.b, r15 + c6: 06 cd f0 7e mul 252\[r15\]\.uw, r0 + ca: 06 cd ff 7e mul 252\[r15\]\.uw, r15 + ce: 06 4d f0 7e mul 252\[r15\]\.w, r0 + d2: 06 4d ff 7e mul 252\[r15\]\.w, r15 + d6: 06 8d f0 3f mul 252\[r15\]\.l, r0 + da: 06 8d ff 3f mul 252\[r15\]\.l, r15 + de: 4e 00 fc ff mul 65532\[r0\]\.ub, r0 + e2: 4e 0f fc ff mul 65532\[r0\]\.ub, r15 + e6: 06 0e 00 fc ff mul 65532\[r0\]\.b, r0 + eb: 06 0e 0f fc ff mul 65532\[r0\]\.b, r15 + f0: 06 ce 00 fe 7f mul 65532\[r0\]\.uw, r0 + f5: 06 ce 0f fe 7f mul 65532\[r0\]\.uw, r15 + fa: 06 4e 00 fe 7f mul 65532\[r0\]\.w, r0 + ff: 06 4e 0f fe 7f mul 65532\[r0\]\.w, r15 + 104: 06 8e 00 ff 3f mul 65532\[r0\]\.l, r0 + 109: 06 8e 0f ff 3f mul 65532\[r0\]\.l, r15 + 10e: 4e f0 fc ff mul 65532\[r15\]\.ub, r0 + 112: 4e ff fc ff mul 65532\[r15\]\.ub, r15 + 116: 06 0e f0 fc ff mul 65532\[r15\]\.b, r0 + 11b: 06 0e ff fc ff mul 65532\[r15\]\.b, r15 + 120: 06 ce f0 fe 7f mul 65532\[r15\]\.uw, r0 + 125: 06 ce ff fe 7f mul 65532\[r15\]\.uw, r15 + 12a: 06 4e f0 fe 7f mul 65532\[r15\]\.w, r0 + 12f: 06 4e ff fe 7f mul 65532\[r15\]\.w, r15 + 134: 06 8e f0 ff 3f mul 65532\[r15\]\.l, r0 + 139: 06 8e ff ff 3f mul 65532\[r15\]\.l, r15 + 13e: ff 30 00 mul r0, r0, r0 + 141: ff 3f 00 mul r0, r0, r15 + 144: ff 30 0f mul r0, r15, r0 + 147: ff 3f 0f mul r0, r15, r15 + 14a: ff 30 f0 mul r15, r0, r0 + 14d: ff 3f f0 mul r15, r0, r15 + 150: ff 30 ff mul r15, r15, r0 + 153: ff 3f ff mul r15, r15, r15 diff --git a/gas/testsuite/gas/rx/mul.sm b/gas/testsuite/gas/rx/mul.sm new file mode 100644 index 00000000000..cd1202ab559 --- /dev/null +++ b/gas/testsuite/gas/rx/mul.sm @@ -0,0 +1,6 @@ + mul #{uimm4},{reg} + mul #{imm},{reg} + mul {reg},{reg} + mul {memx},{reg} + mul {reg},{reg},{reg} + diff --git a/gas/testsuite/gas/rx/mulhi.d b/gas/testsuite/gas/rx/mulhi.d new file mode 100644 index 00000000000..0653bb4a922 --- /dev/null +++ b/gas/testsuite/gas/rx/mulhi.d @@ -0,0 +1,12 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 00 00 mulhi r0, r0 + 3: fd 00 0f mulhi r0, r15 + 6: fd 00 f0 mulhi r15, r0 + 9: fd 00 ff mulhi r15, r15 diff --git a/gas/testsuite/gas/rx/mulhi.sm b/gas/testsuite/gas/rx/mulhi.sm new file mode 100644 index 00000000000..a9765a4ccd2 --- /dev/null +++ b/gas/testsuite/gas/rx/mulhi.sm @@ -0,0 +1 @@ + mulhi {reg},{reg} diff --git a/gas/testsuite/gas/rx/mullo.d b/gas/testsuite/gas/rx/mullo.d new file mode 100644 index 00000000000..fbf014fcb92 --- /dev/null +++ b/gas/testsuite/gas/rx/mullo.d @@ -0,0 +1,12 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 01 00 mullo r0, r0 + 3: fd 01 0f mullo r0, r15 + 6: fd 01 f0 mullo r15, r0 + 9: fd 01 ff mullo r15, r15 diff --git a/gas/testsuite/gas/rx/mullo.sm b/gas/testsuite/gas/rx/mullo.sm new file mode 100644 index 00000000000..56d6b8b1756 --- /dev/null +++ b/gas/testsuite/gas/rx/mullo.sm @@ -0,0 +1 @@ + mullo {reg},{reg} diff --git a/gas/testsuite/gas/rx/mvfachi.d b/gas/testsuite/gas/rx/mvfachi.d new file mode 100644 index 00000000000..de0abf14b87 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfachi.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 1f 00 mvfachi r0 + 3: fd 1f 0f mvfachi r15 diff --git a/gas/testsuite/gas/rx/mvfachi.sm b/gas/testsuite/gas/rx/mvfachi.sm new file mode 100644 index 00000000000..e8755d6f248 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfachi.sm @@ -0,0 +1 @@ + mvfachi {reg} diff --git a/gas/testsuite/gas/rx/mvfaclo.d b/gas/testsuite/gas/rx/mvfaclo.d new file mode 100644 index 00000000000..33df9b0d366 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfaclo.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 1f 10 mvfaclo r0 + 3: fd 1f 1f mvfaclo r15 diff --git a/gas/testsuite/gas/rx/mvfaclo.sm b/gas/testsuite/gas/rx/mvfaclo.sm new file mode 100644 index 00000000000..b9080e41227 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfaclo.sm @@ -0,0 +1 @@ + mvfaclo {reg} diff --git a/gas/testsuite/gas/rx/mvfacmi.d b/gas/testsuite/gas/rx/mvfacmi.d new file mode 100644 index 00000000000..c24479a3dc9 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfacmi.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 1f 20 mvfacmi r0 + 3: fd 1f 2f mvfacmi r15 diff --git a/gas/testsuite/gas/rx/mvfacmi.sm b/gas/testsuite/gas/rx/mvfacmi.sm new file mode 100644 index 00000000000..400f125f30a --- /dev/null +++ b/gas/testsuite/gas/rx/mvfacmi.sm @@ -0,0 +1 @@ + mvfacmi {reg} diff --git a/gas/testsuite/gas/rx/mvfc.d b/gas/testsuite/gas/rx/mvfc.d new file mode 100644 index 00000000000..d402015ed48 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfc.d @@ -0,0 +1,26 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 6a 00 mvfc psw, r0 + 3: fd 6a 0f mvfc psw, r15 + 6: fd 6a 30 mvfc fpsw, r0 + 9: fd 6a 3f mvfc fpsw, r15 + c: fd 6a 20 mvfc usp, r0 + f: fd 6a 2f mvfc usp, r15 + 12: fd 6a a0 mvfc isp, r0 + 15: fd 6a af mvfc isp, r15 + 18: fd 6a c0 mvfc intb, r0 + 1b: fd 6a cf mvfc intb, r15 + 1e: fd 6a 80 mvfc bpsw, r0 + 21: fd 6a 8f mvfc bpsw, r15 + 24: fd 6a 90 mvfc bpc, r0 + 27: fd 6a 9f mvfc bpc, r15 + 2a: fd 6a b0 mvfc fintv, r0 + 2d: fd 6a bf mvfc fintv, r15 + 30: fd 6a 40 mvfc cpen, r0 + 33: fd 6a 4f mvfc cpen, r15 diff --git a/gas/testsuite/gas/rx/mvfc.sm b/gas/testsuite/gas/rx/mvfc.sm new file mode 100644 index 00000000000..3e23cdbd086 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfc.sm @@ -0,0 +1 @@ + mvfc {creg},{reg} diff --git a/gas/testsuite/gas/rx/mvfcp.d b/gas/testsuite/gas/rx/mvfcp.d new file mode 100644 index 00000000000..ec475202872 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfcp.d @@ -0,0 +1,4 @@ +#objdump: -dr + +dump\.o: file format .* + diff --git a/gas/testsuite/gas/rx/mvfcp.sm b/gas/testsuite/gas/rx/mvfcp.sm new file mode 100644 index 00000000000..e30b8b2f254 --- /dev/null +++ b/gas/testsuite/gas/rx/mvfcp.sm @@ -0,0 +1 @@ +# mvfcp #{uimm2},{reg},{uimm16} diff --git a/gas/testsuite/gas/rx/mvtachi.d b/gas/testsuite/gas/rx/mvtachi.d new file mode 100644 index 00000000000..c9f02ee1813 --- /dev/null +++ b/gas/testsuite/gas/rx/mvtachi.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 17 00 mvtachi r0 + 3: fd 17 0f mvtachi r15 diff --git a/gas/testsuite/gas/rx/mvtachi.sm b/gas/testsuite/gas/rx/mvtachi.sm new file mode 100644 index 00000000000..53dad056cda --- /dev/null +++ b/gas/testsuite/gas/rx/mvtachi.sm @@ -0,0 +1 @@ + mvtachi {reg} diff --git a/gas/testsuite/gas/rx/mvtaclo.d b/gas/testsuite/gas/rx/mvtaclo.d new file mode 100644 index 00000000000..09c7ca62f41 --- /dev/null +++ b/gas/testsuite/gas/rx/mvtaclo.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 17 10 mvtaclo r0 + 3: fd 17 1f mvtaclo r15 diff --git a/gas/testsuite/gas/rx/mvtaclo.sm b/gas/testsuite/gas/rx/mvtaclo.sm new file mode 100644 index 00000000000..840bd88aa30 --- /dev/null +++ b/gas/testsuite/gas/rx/mvtaclo.sm @@ -0,0 +1 @@ + mvtaclo {reg} diff --git a/gas/testsuite/gas/rx/mvtc.d b/gas/testsuite/gas/rx/mvtc.d new file mode 100644 index 00000000000..851ba278e0e --- /dev/null +++ b/gas/testsuite/gas/rx/mvtc.d @@ -0,0 +1,98 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 77 00 80 mvtc #-128, psw + 4: fd 77 03 80 mvtc #-128, fpsw + 8: fd 77 02 80 mvtc #-128, usp + c: fd 77 0a 80 mvtc #-128, isp + 10: fd 77 0c 80 mvtc #-128, intb + 14: fd 77 08 80 mvtc #-128, bpsw + 18: fd 77 09 80 mvtc #-128, bpc + 1c: fd 77 0b 80 mvtc #-128, fintv + 20: fd 77 04 80 mvtc #-128, cpen + 24: fd 77 00 7f mvtc #127, psw + 28: fd 77 03 7f mvtc #127, fpsw + 2c: fd 77 02 7f mvtc #127, usp + 30: fd 77 0a 7f mvtc #127, isp + 34: fd 77 0c 7f mvtc #127, intb + 38: fd 77 08 7f mvtc #127, bpsw + 3c: fd 77 09 7f mvtc #127, bpc + 40: fd 77 0b 7f mvtc #127, fintv + 44: fd 77 04 7f mvtc #127, cpen + 48: fd 7b 00 00 80 mvtc #0xffff8000, psw + 4d: fd 7b 03 00 80 mvtc #0xffff8000, fpsw + 52: fd 7b 02 00 80 mvtc #0xffff8000, usp + 57: fd 7b 0a 00 80 mvtc #0xffff8000, isp + 5c: fd 7b 0c 00 80 mvtc #0xffff8000, intb + 61: fd 7b 08 00 80 mvtc #0xffff8000, bpsw + 66: fd 7b 09 00 80 mvtc #0xffff8000, bpc + 6b: fd 7b 0b 00 80 mvtc #0xffff8000, fintv + 70: fd 7b 04 00 80 mvtc #0xffff8000, cpen + 75: fd 7f 00 00 80 00 mvtc #0x8000, psw + 7b: fd 7f 03 00 80 00 mvtc #0x8000, fpsw + 81: fd 7f 02 00 80 00 mvtc #0x8000, usp + 87: fd 7f 0a 00 80 00 mvtc #0x8000, isp + 8d: fd 7f 0c 00 80 00 mvtc #0x8000, intb + 93: fd 7f 08 00 80 00 mvtc #0x8000, bpsw + 99: fd 7f 09 00 80 00 mvtc #0x8000, bpc + 9f: fd 7f 0b 00 80 00 mvtc #0x8000, fintv + a5: fd 7f 04 00 80 00 mvtc #0x8000, cpen + ab: fd 7f 00 00 00 80 mvtc #0xff800000, psw + b1: fd 7f 03 00 00 80 mvtc #0xff800000, fpsw + b7: fd 7f 02 00 00 80 mvtc #0xff800000, usp + bd: fd 7f 0a 00 00 80 mvtc #0xff800000, isp + c3: fd 7f 0c 00 00 80 mvtc #0xff800000, intb + c9: fd 7f 08 00 00 80 mvtc #0xff800000, bpsw + cf: fd 7f 09 00 00 80 mvtc #0xff800000, bpc + d5: fd 7f 0b 00 00 80 mvtc #0xff800000, fintv + db: fd 7f 04 00 00 80 mvtc #0xff800000, cpen + e1: fd 7f 00 ff ff 7f mvtc #0x7fffff, psw + e7: fd 7f 03 ff ff 7f mvtc #0x7fffff, fpsw + ed: fd 7f 02 ff ff 7f mvtc #0x7fffff, usp + f3: fd 7f 0a ff ff 7f mvtc #0x7fffff, isp + f9: fd 7f 0c ff ff 7f mvtc #0x7fffff, intb + ff: fd 7f 08 ff ff 7f mvtc #0x7fffff, bpsw + 105: fd 7f 09 ff ff 7f mvtc #0x7fffff, bpc + 10b: fd 7f 0b ff ff 7f mvtc #0x7fffff, fintv + 111: fd 7f 04 ff ff 7f mvtc #0x7fffff, cpen + 117: fd 73 00 00 00 00 80 mvtc #0x80000000, psw + 11e: fd 73 03 00 00 00 80 mvtc #0x80000000, fpsw + 125: fd 73 02 00 00 00 80 mvtc #0x80000000, usp + 12c: fd 73 0a 00 00 00 80 mvtc #0x80000000, isp + 133: fd 73 0c 00 00 00 80 mvtc #0x80000000, intb + 13a: fd 73 08 00 00 00 80 mvtc #0x80000000, bpsw + 141: fd 73 09 00 00 00 80 mvtc #0x80000000, bpc + 148: fd 73 0b 00 00 00 80 mvtc #0x80000000, fintv + 14f: fd 73 04 00 00 00 80 mvtc #0x80000000, cpen + 156: fd 73 00 ff ff ff 7f mvtc #0x7fffffff, psw + 15d: fd 73 03 ff ff ff 7f mvtc #0x7fffffff, fpsw + 164: fd 73 02 ff ff ff 7f mvtc #0x7fffffff, usp + 16b: fd 73 0a ff ff ff 7f mvtc #0x7fffffff, isp + 172: fd 73 0c ff ff ff 7f mvtc #0x7fffffff, intb + 179: fd 73 08 ff ff ff 7f mvtc #0x7fffffff, bpsw + 180: fd 73 09 ff ff ff 7f mvtc #0x7fffffff, bpc + 187: fd 73 0b ff ff ff 7f mvtc #0x7fffffff, fintv + 18e: fd 73 04 ff ff ff 7f mvtc #0x7fffffff, cpen + 195: fd 68 00 mvtc r0, psw + 198: fd 68 03 mvtc r0, fpsw + 19b: fd 68 02 mvtc r0, usp + 19e: fd 68 0a mvtc r0, isp + 1a1: fd 68 0c mvtc r0, intb + 1a4: fd 68 08 mvtc r0, bpsw + 1a7: fd 68 09 mvtc r0, bpc + 1aa: fd 68 0b mvtc r0, fintv + 1ad: fd 68 04 mvtc r0, cpen + 1b0: fd 68 f0 mvtc r15, psw + 1b3: fd 68 f3 mvtc r15, fpsw + 1b6: fd 68 f2 mvtc r15, usp + 1b9: fd 68 fa mvtc r15, isp + 1bc: fd 68 fc mvtc r15, intb + 1bf: fd 68 f8 mvtc r15, bpsw + 1c2: fd 68 f9 mvtc r15, bpc + 1c5: fd 68 fb mvtc r15, fintv + 1c8: fd 68 f4 mvtc r15, cpen diff --git a/gas/testsuite/gas/rx/mvtc.sm b/gas/testsuite/gas/rx/mvtc.sm new file mode 100644 index 00000000000..2e16c724465 --- /dev/null +++ b/gas/testsuite/gas/rx/mvtc.sm @@ -0,0 +1,2 @@ + mvtc #{imm},{creg} + mvtc {reg},{creg} diff --git a/gas/testsuite/gas/rx/mvtcp.d b/gas/testsuite/gas/rx/mvtcp.d new file mode 100644 index 00000000000..ec475202872 --- /dev/null +++ b/gas/testsuite/gas/rx/mvtcp.d @@ -0,0 +1,4 @@ +#objdump: -dr + +dump\.o: file format .* + diff --git a/gas/testsuite/gas/rx/mvtcp.sm b/gas/testsuite/gas/rx/mvtcp.sm new file mode 100644 index 00000000000..12ef6444daa --- /dev/null +++ b/gas/testsuite/gas/rx/mvtcp.sm @@ -0,0 +1,2 @@ +# mvtcp #{uimm2},#{simm16},${uimm16} +# mvtcp #{uimm2},{reg},${uimm16} diff --git a/gas/testsuite/gas/rx/neg.d b/gas/testsuite/gas/rx/neg.d new file mode 100644 index 00000000000..593649c1d1d --- /dev/null +++ b/gas/testsuite/gas/rx/neg.d @@ -0,0 +1,14 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e 10 neg r0 + 2: 7e 1f neg r15 + 4: fc 07 00 neg r0, r0 + 7: fc 07 0f neg r0, r15 + a: fc 07 f0 neg r15, r0 + d: fc 07 ff neg r15, r15 diff --git a/gas/testsuite/gas/rx/neg.sm b/gas/testsuite/gas/rx/neg.sm new file mode 100644 index 00000000000..3eeb43c9921 --- /dev/null +++ b/gas/testsuite/gas/rx/neg.sm @@ -0,0 +1,2 @@ + neg {reg} + neg {reg},{reg} diff --git a/gas/testsuite/gas/rx/nop.d b/gas/testsuite/gas/rx/nop.d new file mode 100644 index 00000000000..ca00f428975 --- /dev/null +++ b/gas/testsuite/gas/rx/nop.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 03 nop diff --git a/gas/testsuite/gas/rx/nop.sm b/gas/testsuite/gas/rx/nop.sm new file mode 100644 index 00000000000..4e7fe2f0a49 --- /dev/null +++ b/gas/testsuite/gas/rx/nop.sm @@ -0,0 +1 @@ + nop diff --git a/gas/testsuite/gas/rx/not.d b/gas/testsuite/gas/rx/not.d new file mode 100644 index 00000000000..59fe54bd49c --- /dev/null +++ b/gas/testsuite/gas/rx/not.d @@ -0,0 +1,14 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e 00 not r0 + 2: 7e 0f not r15 + 4: fc 3b 00 not r0, r0 + 7: fc 3b 0f not r0, r15 + a: fc 3b f0 not r15, r0 + d: fc 3b ff not r15, r15 diff --git a/gas/testsuite/gas/rx/not.sm b/gas/testsuite/gas/rx/not.sm new file mode 100644 index 00000000000..9e7a32d2b6b --- /dev/null +++ b/gas/testsuite/gas/rx/not.sm @@ -0,0 +1,2 @@ + not {reg} + not {reg},{reg} diff --git a/gas/testsuite/gas/rx/opecp.d b/gas/testsuite/gas/rx/opecp.d new file mode 100644 index 00000000000..ec475202872 --- /dev/null +++ b/gas/testsuite/gas/rx/opecp.d @@ -0,0 +1,4 @@ +#objdump: -dr + +dump\.o: file format .* + diff --git a/gas/testsuite/gas/rx/opecp.sm b/gas/testsuite/gas/rx/opecp.sm new file mode 100644 index 00000000000..78ecd53e47a --- /dev/null +++ b/gas/testsuite/gas/rx/opecp.sm @@ -0,0 +1 @@ +# opecp #{uimm2},#{uimm16} diff --git a/gas/testsuite/gas/rx/or.d b/gas/testsuite/gas/rx/or.d new file mode 100644 index 00000000000..d3da5cf8999 --- /dev/null +++ b/gas/testsuite/gas/rx/or.d @@ -0,0 +1,100 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 65 00 or #0, r0 + 2: 65 0f or #0, r15 + 4: 65 f0 or #15, r0 + 6: 65 ff or #15, r15 + 8: 75 30 80 or #-128, r0 + b: 75 3f 80 or #-128, r15 + e: 75 30 7f or #127, r0 + 11: 75 3f 7f or #127, r15 + 14: 76 30 00 80 or #0xffff8000, r0 + 18: 76 3f 00 80 or #0xffff8000, r15 + 1c: 77 30 00 80 00 or #0x8000, r0 + 21: 77 3f 00 80 00 or #0x8000, r15 + 26: 77 30 00 00 80 or #0xff800000, r0 + 2b: 77 3f 00 00 80 or #0xff800000, r15 + 30: 77 30 ff ff 7f or #0x7fffff, r0 + 35: 77 3f ff ff 7f or #0x7fffff, r15 + 3a: 74 30 00 00 00 80 or #0x80000000, r0 + 40: 74 3f 00 00 00 80 or #0x80000000, r15 + 46: 74 30 ff ff ff 7f or #0x7fffffff, r0 + 4c: 74 3f ff ff ff 7f or #0x7fffffff, r15 + 52: 57 00 or r0, r0 + 54: 57 0f or r0, r15 + 56: 57 f0 or r15, r0 + 58: 57 ff or r15, r15 + 5a: 54 00 or \[r0\]\.ub, r0 + 5c: 54 0f or \[r0\]\.ub, r15 + 5e: 06 14 00 or \[r0\]\.b, r0 + 61: 06 14 0f or \[r0\]\.b, r15 + 64: 06 d4 00 or \[r0\]\.uw, r0 + 67: 06 d4 0f or \[r0\]\.uw, r15 + 6a: 06 54 00 or \[r0\]\.w, r0 + 6d: 06 54 0f or \[r0\]\.w, r15 + 70: 06 94 00 or \[r0\]\.l, r0 + 73: 06 94 0f or \[r0\]\.l, r15 + 76: 54 f0 or \[r15\]\.ub, r0 + 78: 54 ff or \[r15\]\.ub, r15 + 7a: 06 14 f0 or \[r15\]\.b, r0 + 7d: 06 14 ff or \[r15\]\.b, r15 + 80: 06 d4 f0 or \[r15\]\.uw, r0 + 83: 06 d4 ff or \[r15\]\.uw, r15 + 86: 06 54 f0 or \[r15\]\.w, r0 + 89: 06 54 ff or \[r15\]\.w, r15 + 8c: 06 94 f0 or \[r15\]\.l, r0 + 8f: 06 94 ff or \[r15\]\.l, r15 + 92: 55 00 fc or 252\[r0\]\.ub, r0 + 95: 55 0f fc or 252\[r0\]\.ub, r15 + 98: 06 15 00 fc or 252\[r0\]\.b, r0 + 9c: 06 15 0f fc or 252\[r0\]\.b, r15 + a0: 06 d5 00 7e or 252\[r0\]\.uw, r0 + a4: 06 d5 0f 7e or 252\[r0\]\.uw, r15 + a8: 06 55 00 7e or 252\[r0\]\.w, r0 + ac: 06 55 0f 7e or 252\[r0\]\.w, r15 + b0: 06 95 00 3f or 252\[r0\]\.l, r0 + b4: 06 95 0f 3f or 252\[r0\]\.l, r15 + b8: 55 f0 fc or 252\[r15\]\.ub, r0 + bb: 55 ff fc or 252\[r15\]\.ub, r15 + be: 06 15 f0 fc or 252\[r15\]\.b, r0 + c2: 06 15 ff fc or 252\[r15\]\.b, r15 + c6: 06 d5 f0 7e or 252\[r15\]\.uw, r0 + ca: 06 d5 ff 7e or 252\[r15\]\.uw, r15 + ce: 06 55 f0 7e or 252\[r15\]\.w, r0 + d2: 06 55 ff 7e or 252\[r15\]\.w, r15 + d6: 06 95 f0 3f or 252\[r15\]\.l, r0 + da: 06 95 ff 3f or 252\[r15\]\.l, r15 + de: 56 00 fc ff or 65532\[r0\]\.ub, r0 + e2: 56 0f fc ff or 65532\[r0\]\.ub, r15 + e6: 06 16 00 fc ff or 65532\[r0\]\.b, r0 + eb: 06 16 0f fc ff or 65532\[r0\]\.b, r15 + f0: 06 d6 00 fe 7f or 65532\[r0\]\.uw, r0 + f5: 06 d6 0f fe 7f or 65532\[r0\]\.uw, r15 + fa: 06 56 00 fe 7f or 65532\[r0\]\.w, r0 + ff: 06 56 0f fe 7f or 65532\[r0\]\.w, r15 + 104: 06 96 00 ff 3f or 65532\[r0\]\.l, r0 + 109: 06 96 0f ff 3f or 65532\[r0\]\.l, r15 + 10e: 56 f0 fc ff or 65532\[r15\]\.ub, r0 + 112: 56 ff fc ff or 65532\[r15\]\.ub, r15 + 116: 06 16 f0 fc ff or 65532\[r15\]\.b, r0 + 11b: 06 16 ff fc ff or 65532\[r15\]\.b, r15 + 120: 06 d6 f0 fe 7f or 65532\[r15\]\.uw, r0 + 125: 06 d6 ff fe 7f or 65532\[r15\]\.uw, r15 + 12a: 06 56 f0 fe 7f or 65532\[r15\]\.w, r0 + 12f: 06 56 ff fe 7f or 65532\[r15\]\.w, r15 + 134: 06 96 f0 ff 3f or 65532\[r15\]\.l, r0 + 139: 06 96 ff ff 3f or 65532\[r15\]\.l, r15 + 13e: ff 50 00 or r0, r0, r0 + 141: ff 5f 00 or r0, r0, r15 + 144: ff 50 0f or r0, r15, r0 + 147: ff 5f 0f or r0, r15, r15 + 14a: ff 50 f0 or r15, r0, r0 + 14d: ff 5f f0 or r15, r0, r15 + 150: ff 50 ff or r15, r15, r0 + 153: ff 5f ff or r15, r15, r15 diff --git a/gas/testsuite/gas/rx/or.sm b/gas/testsuite/gas/rx/or.sm new file mode 100644 index 00000000000..2df6556caf4 --- /dev/null +++ b/gas/testsuite/gas/rx/or.sm @@ -0,0 +1,7 @@ + or #{uimm4},{reg} + or #{imm},{reg} + + or {reg},{reg} + or {memx},{reg} + + or {reg},{reg},{reg} diff --git a/gas/testsuite/gas/rx/pop.d b/gas/testsuite/gas/rx/pop.d new file mode 100644 index 00000000000..febeeb2991c --- /dev/null +++ b/gas/testsuite/gas/rx/pop.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e b0 pop r0 + 2: 7e bf pop r15 diff --git a/gas/testsuite/gas/rx/pop.sm b/gas/testsuite/gas/rx/pop.sm new file mode 100644 index 00000000000..a5050979675 --- /dev/null +++ b/gas/testsuite/gas/rx/pop.sm @@ -0,0 +1 @@ + pop {reg} diff --git a/gas/testsuite/gas/rx/popc.d b/gas/testsuite/gas/rx/popc.d new file mode 100644 index 00000000000..e5eea804fc4 --- /dev/null +++ b/gas/testsuite/gas/rx/popc.d @@ -0,0 +1,17 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e e0 popc psw + 2: 7e e3 popc fpsw + 4: 7e e2 popc usp + 6: 7e ea popc isp + 8: 7e ec popc intb + a: 7e e8 popc bpsw + c: 7e e9 popc bpc + e: 7e eb popc fintv + 10: 7e e4 popc cpen diff --git a/gas/testsuite/gas/rx/popc.sm b/gas/testsuite/gas/rx/popc.sm new file mode 100644 index 00000000000..c273f52cfc5 --- /dev/null +++ b/gas/testsuite/gas/rx/popc.sm @@ -0,0 +1 @@ + popc {creg} diff --git a/gas/testsuite/gas/rx/popm.d b/gas/testsuite/gas/rx/popm.d new file mode 100644 index 00000000000..e06d8e4a75c --- /dev/null +++ b/gas/testsuite/gas/rx/popm.d @@ -0,0 +1,13 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 6f 18 popm r1-r8 + 2: 6f 1e popm r1-r14 + 4: 6f 78 popm r7-r8 + 6: 6f 7e popm r7-r14 + 8: 7e b4 pop r4 diff --git a/gas/testsuite/gas/rx/popm.sm b/gas/testsuite/gas/rx/popm.sm new file mode 100644 index 00000000000..e63e60264a7 --- /dev/null +++ b/gas/testsuite/gas/rx/popm.sm @@ -0,0 +1,2 @@ + popm {regPlo}-{regPhi} + popm r4-r4 diff --git a/gas/testsuite/gas/rx/push.d b/gas/testsuite/gas/rx/push.d new file mode 100644 index 00000000000..cc799c76dca --- /dev/null +++ b/gas/testsuite/gas/rx/push.d @@ -0,0 +1,32 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e 80 push\.b r0 + 2: 7e 8f push\.b r15 + 4: 7e 90 push\.w r0 + 6: 7e 9f push\.w r15 + 8: 7e a0 push\.l r0 + a: 7e af push\.l r15 + c: f4 08 push\.b \[r0\] + e: f4 f8 push\.b \[r15\] + 10: f5 08 fc push\.b 252\[r0\] + 13: f5 f8 fc push\.b 252\[r15\] + 16: f6 08 fc ff push\.b 65532\[r0\] + 1a: f6 f8 fc ff push\.b 65532\[r15\] + 1e: f4 09 push\.w \[r0\] + 20: f4 f9 push\.w \[r15\] + 22: f5 09 7e push\.w 252\[r0\] + 25: f5 f9 7e push\.w 252\[r15\] + 28: f6 09 fe 7f push\.w 65532\[r0\] + 2c: f6 f9 fe 7f push\.w 65532\[r15\] + 30: f4 0a push\.l \[r0\] + 32: f4 fa push\.l \[r15\] + 34: f5 0a 3f push\.l 252\[r0\] + 37: f5 fa 3f push\.l 252\[r15\] + 3a: f6 0a ff 3f push\.l 65532\[r0\] + 3e: f6 fa ff 3f push\.l 65532\[r15\] diff --git a/gas/testsuite/gas/rx/push.sm b/gas/testsuite/gas/rx/push.sm new file mode 100644 index 00000000000..8532d361fda --- /dev/null +++ b/gas/testsuite/gas/rx/push.sm @@ -0,0 +1,2 @@ + push{bwl} {reg} + push{bwl} {mem} diff --git a/gas/testsuite/gas/rx/pushc.d b/gas/testsuite/gas/rx/pushc.d new file mode 100644 index 00000000000..f97a06a6a41 --- /dev/null +++ b/gas/testsuite/gas/rx/pushc.d @@ -0,0 +1,17 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e c0 pushc psw + 2: 7e c3 pushc fpsw + 4: 7e c2 pushc usp + 6: 7e ca pushc isp + 8: 7e cc pushc intb + a: 7e c8 pushc bpsw + c: 7e c9 pushc bpc + e: 7e cb pushc fintv + 10: 7e c4 pushc cpen diff --git a/gas/testsuite/gas/rx/pushc.sm b/gas/testsuite/gas/rx/pushc.sm new file mode 100644 index 00000000000..fcdb118ff38 --- /dev/null +++ b/gas/testsuite/gas/rx/pushc.sm @@ -0,0 +1 @@ + pushc {creg} diff --git a/gas/testsuite/gas/rx/pushm.d b/gas/testsuite/gas/rx/pushm.d new file mode 100644 index 00000000000..fd2ffa6530d --- /dev/null +++ b/gas/testsuite/gas/rx/pushm.d @@ -0,0 +1,13 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 6e 18 pushm r1-r8 + 2: 6e 1e pushm r1-r14 + 4: 6e 78 pushm r7-r8 + 6: 6e 7e pushm r7-r14 + 8: 7e a4 push.l r4 diff --git a/gas/testsuite/gas/rx/pushm.sm b/gas/testsuite/gas/rx/pushm.sm new file mode 100644 index 00000000000..6df443f18f9 --- /dev/null +++ b/gas/testsuite/gas/rx/pushm.sm @@ -0,0 +1,2 @@ + pushm {regPlo}-{regPhi} + pushm r4-r4 diff --git a/gas/testsuite/gas/rx/r-bcc.d b/gas/testsuite/gas/rx/r-bcc.d new file mode 100644 index 00000000000..672a52a1892 --- /dev/null +++ b/gas/testsuite/gas/rx/r-bcc.d @@ -0,0 +1,43 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <beq>: + 0: 20 32 beq\.b 32 <dsp8> + 2: 3a 86 13 beq\.w 1388 <dsp16> + 5: 1e bne\.s b <bne\+0x1> + 6: 04 1a a1 07 bra\.a 7a120 <dsp24> + +0000000a <bne>: + a: 21 28 bne\.b 32 <dsp8> + c: 3b 7c 13 bne\.w 1388 <dsp16> + f: 15 beq\.s 14 <bgt> + 10: 04 10 a1 07 bra\.a 7a120 <dsp24> + +00000014 <bgt>: + 14: 2a 1e bgt\.b 32 <dsp8> + 16: 2b 05 ble\.b 1b <bgt\+0x7> + 18: 38 70 13 bra\.w 1388 <dsp16> + 1b: 2b 06 ble\.b 21 <bltu> + 1d: 04 03 a1 07 bra\.a 7a120 <dsp24> + +00000021 <bltu>: + 21: 23 11 bnc\.b 32 <dsp8> + 23: 22 05 bc\.b 28 <bltu\+0x7> + 25: 38 63 13 bra\.w 1388 <dsp16> + 28: 22 06 bc\.b 2e <done> + 2a: 04 f6 a0 07 bra\.a 7a120 <dsp24> + +0000002e <done>: + 2e: 03 nop + 2f: 00 brk + \.\.\. + +00000032 <dsp8>: + \.\.\. + +00001388 <dsp16>: + \.\.\. diff --git a/gas/testsuite/gas/rx/r-bcc.sm b/gas/testsuite/gas/rx/r-bcc.sm new file mode 100644 index 00000000000..9cfece0d3e0 --- /dev/null +++ b/gas/testsuite/gas/rx/r-bcc.sm @@ -0,0 +1,29 @@ +beq: + beq dsp8 + beq dsp16 + beq dsp24 + +bne: + bne dsp8 + bne dsp16 + bne dsp24 + +bgt: + bgt dsp8 + bgt dsp16 + bgt dsp24 + +bltu: + bltu dsp8 + bltu dsp16 + bltu dsp24 + +done: + nop + + .space 3 +dsp8: + .space 4950 +dsp16: + .space 495000 +dsp24: diff --git a/gas/testsuite/gas/rx/r-bra.d b/gas/testsuite/gas/rx/r-bra.d new file mode 100644 index 00000000000..9bdef5202eb --- /dev/null +++ b/gas/testsuite/gas/rx/r-bra.d @@ -0,0 +1,34 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <bar-0x1>: + 0: 03 nop + +00000001 <bar>: + 1: 03 nop + 2: 03 nop + 3: 04 .. .. .. bra\.a .* + 4: R_RX_DIR24S_PCREL fred + 7: 04 7b 81 00 bra\.a 8182 <barney> + b: 38 8e 00 bra\.w 99 <grill> + e: 2e f3 bra\.b 1 <bar> + 10: 0e bra\.s 16 <foo> + 11: 03 nop + 12: 2e ef bra\.b 1 <bar> + 14: 03 nop + 15: 03 nop + +00000016 <foo>: + 16: 03 nop + \.\.\. + +00000099 <grill>: + 99: 03 nop + \.\.\. + +00008182 <barney>: + 8182: 03 nop diff --git a/gas/testsuite/gas/rx/r-bra.sm b/gas/testsuite/gas/rx/r-bra.sm new file mode 100644 index 00000000000..0800b94ccc8 --- /dev/null +++ b/gas/testsuite/gas/rx/r-bra.sm @@ -0,0 +1,22 @@ + nop +bar: + nop + nop + bra fred + bra barney + bra grill + bra bar + bra foo + nop + bra bar + nop + nop +foo: + nop + + .space 130 +grill: + nop + .space 33000 +barney: + nop diff --git a/gas/testsuite/gas/rx/racw.d b/gas/testsuite/gas/rx/racw.d new file mode 100644 index 00000000000..6735254bf71 --- /dev/null +++ b/gas/testsuite/gas/rx/racw.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 18 00 racw #1 + 3: fd 18 10 racw #2 diff --git a/gas/testsuite/gas/rx/racw.sm b/gas/testsuite/gas/rx/racw.sm new file mode 100644 index 00000000000..f7dfd5b3895 --- /dev/null +++ b/gas/testsuite/gas/rx/racw.sm @@ -0,0 +1,2 @@ + racw #1 + racw #2 diff --git a/gas/testsuite/gas/rx/revl.d b/gas/testsuite/gas/rx/revl.d new file mode 100644 index 00000000000..0b4de61c3b5 --- /dev/null +++ b/gas/testsuite/gas/rx/revl.d @@ -0,0 +1,12 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 67 00 revl r0, r0 + 3: fd 67 0f revl r0, r15 + 6: fd 67 f0 revl r15, r0 + 9: fd 67 ff revl r15, r15 diff --git a/gas/testsuite/gas/rx/revl.sm b/gas/testsuite/gas/rx/revl.sm new file mode 100644 index 00000000000..516f039f125 --- /dev/null +++ b/gas/testsuite/gas/rx/revl.sm @@ -0,0 +1 @@ + revl {reg},{reg} diff --git a/gas/testsuite/gas/rx/revw.d b/gas/testsuite/gas/rx/revw.d new file mode 100644 index 00000000000..429b113a49b --- /dev/null +++ b/gas/testsuite/gas/rx/revw.d @@ -0,0 +1,12 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 65 00 revw r0, r0 + 3: fd 65 0f revw r0, r15 + 6: fd 65 f0 revw r15, r0 + 9: fd 65 ff revw r15, r15 diff --git a/gas/testsuite/gas/rx/revw.sm b/gas/testsuite/gas/rx/revw.sm new file mode 100644 index 00000000000..bcff808d0c1 --- /dev/null +++ b/gas/testsuite/gas/rx/revw.sm @@ -0,0 +1 @@ + revw {reg},{reg} diff --git a/gas/testsuite/gas/rx/rmpa.d b/gas/testsuite/gas/rx/rmpa.d new file mode 100644 index 00000000000..0a325fc2711 --- /dev/null +++ b/gas/testsuite/gas/rx/rmpa.d @@ -0,0 +1,11 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 8c rmpa\.b + 2: 7f 8d rmpa\.w + 4: 7f 8e rmpa\.l diff --git a/gas/testsuite/gas/rx/rmpa.sm b/gas/testsuite/gas/rx/rmpa.sm new file mode 100644 index 00000000000..38710e0306b --- /dev/null +++ b/gas/testsuite/gas/rx/rmpa.sm @@ -0,0 +1 @@ + rmpa{bwl} diff --git a/gas/testsuite/gas/rx/rolc.d b/gas/testsuite/gas/rx/rolc.d new file mode 100644 index 00000000000..d7b678f8448 --- /dev/null +++ b/gas/testsuite/gas/rx/rolc.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e 50 rolc r0 + 2: 7e 5f rolc r15 diff --git a/gas/testsuite/gas/rx/rolc.sm b/gas/testsuite/gas/rx/rolc.sm new file mode 100644 index 00000000000..edc041d59e5 --- /dev/null +++ b/gas/testsuite/gas/rx/rolc.sm @@ -0,0 +1 @@ + rolc {reg} diff --git a/gas/testsuite/gas/rx/rorc.d b/gas/testsuite/gas/rx/rorc.d new file mode 100644 index 00000000000..3f10658820f --- /dev/null +++ b/gas/testsuite/gas/rx/rorc.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e 40 rorc r0 + 2: 7e 4f rorc r15 diff --git a/gas/testsuite/gas/rx/rorc.sm b/gas/testsuite/gas/rx/rorc.sm new file mode 100644 index 00000000000..ffd9a44d108 --- /dev/null +++ b/gas/testsuite/gas/rx/rorc.sm @@ -0,0 +1 @@ + rorc {reg} diff --git a/gas/testsuite/gas/rx/rotl.d b/gas/testsuite/gas/rx/rotl.d new file mode 100644 index 00000000000..f1cdd05c047 --- /dev/null +++ b/gas/testsuite/gas/rx/rotl.d @@ -0,0 +1,16 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 6e 00 rotl #0, r0 + 3: fd 6e 0f rotl #0, r15 + 6: fd 6f f0 rotl #31, r0 + 9: fd 6f ff rotl #31, r15 + c: fd 66 00 rotl r0, r0 + f: fd 66 0f rotl r0, r15 + 12: fd 66 f0 rotl r15, r0 + 15: fd 66 ff rotl r15, r15 diff --git a/gas/testsuite/gas/rx/rotl.sm b/gas/testsuite/gas/rx/rotl.sm new file mode 100644 index 00000000000..27744550b0d --- /dev/null +++ b/gas/testsuite/gas/rx/rotl.sm @@ -0,0 +1,2 @@ + rotl #{uimm5},{reg} + rotl {reg},{reg} diff --git a/gas/testsuite/gas/rx/rotr.d b/gas/testsuite/gas/rx/rotr.d new file mode 100644 index 00000000000..dfde640f68e --- /dev/null +++ b/gas/testsuite/gas/rx/rotr.d @@ -0,0 +1,16 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 6c 00 rotr #0, r0 + 3: fd 6c 0f rotr #0, r15 + 6: fd 6d f0 rotr #31, r0 + 9: fd 6d ff rotr #31, r15 + c: fd 64 00 rotr r0, r0 + f: fd 64 0f rotr r0, r15 + 12: fd 64 f0 rotr r15, r0 + 15: fd 64 ff rotr r15, r15 diff --git a/gas/testsuite/gas/rx/rotr.sm b/gas/testsuite/gas/rx/rotr.sm new file mode 100644 index 00000000000..a67d41d9b15 --- /dev/null +++ b/gas/testsuite/gas/rx/rotr.sm @@ -0,0 +1,2 @@ + rotr #{uimm5},{reg} + rotr {reg},{reg} diff --git a/gas/testsuite/gas/rx/round.d b/gas/testsuite/gas/rx/round.d new file mode 100644 index 00000000000..6927f1c2e1b --- /dev/null +++ b/gas/testsuite/gas/rx/round.d @@ -0,0 +1,24 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc 9b 00 round r0, r0 + 3: fc 9b 0f round r0, r15 + 6: fc 9b f0 round r15, r0 + 9: fc 9b ff round r15, r15 + c: fc 98 00 round \[r0\]\.l, r0 + f: fc 98 0f round \[r0\]\.l, r15 + 12: fc 98 f0 round \[r15\]\.l, r0 + 15: fc 98 ff round \[r15\]\.l, r15 + 18: fc 99 00 3f round 252\[r0\]\.l, r0 + 1c: fc 99 0f 3f round 252\[r0\]\.l, r15 + 20: fc 99 f0 3f round 252\[r15\]\.l, r0 + 24: fc 99 ff 3f round 252\[r15\]\.l, r15 + 28: fc 9a 00 ff 3f round 65532\[r0\]\.l, r0 + 2d: fc 9a 0f ff 3f round 65532\[r0\]\.l, r15 + 32: fc 9a f0 ff 3f round 65532\[r15\]\.l, r0 + 37: fc 9a ff ff 3f round 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/round.sm b/gas/testsuite/gas/rx/round.sm new file mode 100644 index 00000000000..4d2f197930b --- /dev/null +++ b/gas/testsuite/gas/rx/round.sm @@ -0,0 +1,2 @@ + round {reg},{reg} + round {mem}.L,{reg} diff --git a/gas/testsuite/gas/rx/rte.d b/gas/testsuite/gas/rx/rte.d new file mode 100644 index 00000000000..aab166ef73f --- /dev/null +++ b/gas/testsuite/gas/rx/rte.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 95 rte diff --git a/gas/testsuite/gas/rx/rte.sm b/gas/testsuite/gas/rx/rte.sm new file mode 100644 index 00000000000..1c16e678cee --- /dev/null +++ b/gas/testsuite/gas/rx/rte.sm @@ -0,0 +1 @@ + rte diff --git a/gas/testsuite/gas/rx/rtfi.d b/gas/testsuite/gas/rx/rtfi.d new file mode 100644 index 00000000000..39a36de7d96 --- /dev/null +++ b/gas/testsuite/gas/rx/rtfi.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 94 rtfi diff --git a/gas/testsuite/gas/rx/rtfi.sm b/gas/testsuite/gas/rx/rtfi.sm new file mode 100644 index 00000000000..433c9cbdee0 --- /dev/null +++ b/gas/testsuite/gas/rx/rtfi.sm @@ -0,0 +1 @@ + rtfi diff --git a/gas/testsuite/gas/rx/rts.d b/gas/testsuite/gas/rx/rts.d new file mode 100644 index 00000000000..23ae0beae24 --- /dev/null +++ b/gas/testsuite/gas/rx/rts.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 02 rts diff --git a/gas/testsuite/gas/rx/rts.sm b/gas/testsuite/gas/rx/rts.sm new file mode 100644 index 00000000000..ee4894265f2 --- /dev/null +++ b/gas/testsuite/gas/rx/rts.sm @@ -0,0 +1 @@ + rts diff --git a/gas/testsuite/gas/rx/rtsd.d b/gas/testsuite/gas/rx/rtsd.d new file mode 100644 index 00000000000..864f30c611c --- /dev/null +++ b/gas/testsuite/gas/rx/rtsd.d @@ -0,0 +1,18 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 67 00 rtsd #0 + 2: 67 ff rtsd #0x3fc + 4: 3f 18 00 rtsd #0, r1-r8 + 7: 3f 1e 00 rtsd #0, r1-r14 + a: 3f 78 00 rtsd #0, r7-r8 + d: 3f 7e 00 rtsd #0, r7-r14 + 10: 3f 18 ff rtsd #0x3fc, r1-r8 + 13: 3f 1e ff rtsd #0x3fc, r1-r14 + 16: 3f 78 ff rtsd #0x3fc, r7-r8 + 19: 3f 7e ff rtsd #0x3fc, r7-r14 diff --git a/gas/testsuite/gas/rx/rtsd.sm b/gas/testsuite/gas/rx/rtsd.sm new file mode 100644 index 00000000000..d24bb61c2e4 --- /dev/null +++ b/gas/testsuite/gas/rx/rtsd.sm @@ -0,0 +1,2 @@ + rtsd #{0;1020} + rtsd #{0;1020},{regPlo}-{regPhi} diff --git a/gas/testsuite/gas/rx/rx-asm-bad.l b/gas/testsuite/gas/rx/rx-asm-bad.l new file mode 100644 index 00000000000..cd589221dc9 --- /dev/null +++ b/gas/testsuite/gas/rx/rx-asm-bad.l @@ -0,0 +1 @@ +jim diff --git a/gas/testsuite/gas/rx/rx-asm-bad.s b/gas/testsuite/gas/rx/rx-asm-bad.s new file mode 100644 index 00000000000..8a78e048f93 --- /dev/null +++ b/gas/testsuite/gas/rx/rx-asm-bad.s @@ -0,0 +1,58 @@ + .text + + .ID "id-is-jane" + + .INITSCT a_section,data, align + .OPTJ OFF,JMPW,JSRW + .INSF glbfunc, G, 0 + .CALL glbsub, G + .CALL localsub, S + .EINSF + .FB 80H + ldc #80H,FB + .FBSYM george + + .LBBA 1000h + ldr #1000h,LBBA + lda 1000h,0,1200h,1 + + .SB 80H + ldc #80,SB + + .SBBIT lance + bclr lance + + .SBSYM sym + mov.B #0, sym + + .SBSYM16 sym2 + mov.B #0.sym2 + + .RVECTOR 12,timer + + .BTGLB bit1 + + fred .DEFINE "#01H,mem" + + bit1 .BTEQU 1,dmem + + three .equ .INSTR {"albert","bert",1} + seven .equ .LEN {"albert"} + .byte .SUBSTR {"albert",3,3} + + .ASSERT "assertion message" + + .FORM 20,80 + + .LIST ON + + nop + + .PAGE "new page" + + .VER "ver" + + + .END + + This text should just be emitted and not assembled
\ No newline at end of file diff --git a/gas/testsuite/gas/rx/rx-asm-good.d b/gas/testsuite/gas/rx/rx-asm-good.d new file mode 100644 index 00000000000..d515f24f753 --- /dev/null +++ b/gas/testsuite/gas/rx/rx-asm-good.d @@ -0,0 +1,41 @@ +# name: Compatibility with Renesas's own assembler +# objdump: -D --prefix-addresses --show-raw-insn + +.*: +file format elf32-rx-.* + + +Disassembly of section .text: +.* +.* +0+0108 <mem\+0x8> 66 20[ ]+mov.l[ ]+#2, r0 +0+010a <mem\+0xa> 66 10[ ]+mov.l[ ]+#1, r0 +0+010c <mem\+0xc> 66 00[ ]+mov.l[ ]+#0, r0 +0+010e <mem\+0xe> 05 f2 fe ff[ ]+bsr.a[ ]+0+0000 <mem-0x100> +0+0112 <mem\+0x12> 05 ee fe ff[ ]+bsr.a[ ]+0+0000 <mem-0x100> +0+0116 <mem\+0x16> 62 65[ ]+add[ ]+#6, r5 +0+0118 <mem\+0x18> 72 74 0b 2e[ ]+add[ ]+#0x2e0b, r7, r4 +0+011c <mem\+0x1c> ff 2e 00[ ]+add[ ]+r0, r0, r14 +.* + +Disassembly of section .data: +0+0000 <dmem> 01.* +0+0001 <dmem\+0x1> 00.* +0+0002 <dmem\+0x2> 00.* +0+0003 <dmem\+0x3> 64 61.* +0+0005 <dmem\+0x5> 74 00 00 00 00 00.* +.* +0+004f <dmem\+0x4f> 01.* +0+0050 <dmem\+0x50> 64 61.* +0+0052 <dmem\+0x52> 74 61.* +0+0054 <dmem\+0x54> 00.* +0+0055 <dmem\+0x55> 00.* +0+0056 <dmem\+0x56> 00.* +0+0057 <dmem\+0x57> fa 43 b6 f3 9d 3f 00 00.* +0+005f <dmem\+0x5f> fa 43 01 00 00 00 74 77.* +0+0067 <dmem\+0x67> 6f 07.* +0+0069 <dmem\+0x69> 00.* +0+006a <dmem\+0x6a> 00.* +0+006b <dmem\+0x6b> 00.* +0+006c <dmem\+0x6c> 03.* +0+006d <dmem\+0x6d> 00.* +.* diff --git a/gas/testsuite/gas/rx/rx-asm-good.inc b/gas/testsuite/gas/rx/rx-asm-good.inc new file mode 100644 index 00000000000..a3529053c59 --- /dev/null +++ b/gas/testsuite/gas/rx/rx-asm-good.inc @@ -0,0 +1,20 @@ + ; mac1 .MACRO f1,f2 + ; .IF ..MACPARA == 2 + ; add f1,f2 + ; .ELSE + ; add r0,f1 + ; .EXITM + ; .ENDIF + ; .ENDM + ; + ; mac2 .MACRO + ; .LOCAL f1 + ; f1: + ; nop + ; bra f1 + ; .ENDM + ; + ; + ; mac3 .MACRO p1,src,p2,dest + ; MOV@p1@p2 src, dest + ; .ENDM diff --git a/gas/testsuite/gas/rx/rx-asm-good.s b/gas/testsuite/gas/rx/rx-asm-good.s new file mode 100644 index 00000000000..c9567c3359d --- /dev/null +++ b/gas/testsuite/gas/rx/rx-asm-good.s @@ -0,0 +1,86 @@ + + .INCLUDE ..FILE@.inc + + .SECTION .text,CODE,ALIGN + + .ORG 100H + + .GLB mem +mem: + .word three, seven + + ; mac1 r2 + ; mac1 r3,r4 + ; + ; mac2 + ; + ; mac3 L,r0,H,[a0] + + .MREPEAT 3 + mov.l #..MACREP,r0 + .ENDR + + .ALIGN + + .STK 2 + bsr glbsub + bsr localsub + .STK -2 + + .IF TYPE==0 + .byte "harry" + .ELIF TYPE>0 + .byte "jim" + .ELSE + .byte "bert" + .ENDIF + +?: + bra ?+ + bra ?- +?: + bra ?- + + + .SECTION .data,DATA + .GLB dmem +dmem: + size .EQU 2 + + .ADDR 1 + .ADDR "dat" + .ADDR dmem+1 + + .BLKA 1 + .BLKA size + + .BLKB 1 + .BLKB size + + .BLKD 1 + .BLKD size + + .BLKF 1 + .BLKF size + + .BLKL 1 + .BLKL size+1 + + .BLKW 1 + .BLKW size + + .BYTE 1 + .BYTE "data" + .BYTE dmem+1 + + .DOUBLE 5e2 + .FIXED 1.234 + .FLOAT 5e2 + + .LWORD 1 + .LWORD "two" + .LWORD 3+4 + + .WORD 3 + +
\ No newline at end of file diff --git a/gas/testsuite/gas/rx/rx.exp b/gas/testsuite/gas/rx/rx.exp new file mode 100644 index 00000000000..1809af4c3dd --- /dev/null +++ b/gas/testsuite/gas/rx/rx.exp @@ -0,0 +1,17 @@ +# RX assembler testsuite +# -*- tcl -*- + +if { ! [istarget rx-*-*] } { + return +} + +foreach test [lsort [glob $srcdir/$subdir/*.sm]] { + regexp ".*/(.*)\.sm" $test rxjunk rxbase + exec "$srcdir/$subdir/explode" "-I" "$srcdir/$subdir" "$test" "$srcdir/$subdir/$rxbase.s" + run_dump_test "$rxbase" + # Commment out the next line if you want to retain the generated assembler source files. + remote_file host delete "$srcdir/$subdir/$rxbase.s" +} + +run_dump_test "rx-asm-good" +# run_list_test "rx-asm-bad" "" "Generation of error messages with bogus Renesas assembler directives" diff --git a/gas/testsuite/gas/rx/sat.d b/gas/testsuite/gas/rx/sat.d new file mode 100644 index 00000000000..568b83b2353 --- /dev/null +++ b/gas/testsuite/gas/rx/sat.d @@ -0,0 +1,10 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7e 30 sat r0 + 2: 7e 3f sat r15 diff --git a/gas/testsuite/gas/rx/sat.sm b/gas/testsuite/gas/rx/sat.sm new file mode 100644 index 00000000000..be2cda7838c --- /dev/null +++ b/gas/testsuite/gas/rx/sat.sm @@ -0,0 +1 @@ + sat {reg} diff --git a/gas/testsuite/gas/rx/satr.d b/gas/testsuite/gas/rx/satr.d new file mode 100644 index 00000000000..1444265fd37 --- /dev/null +++ b/gas/testsuite/gas/rx/satr.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 93 satr diff --git a/gas/testsuite/gas/rx/satr.sm b/gas/testsuite/gas/rx/satr.sm new file mode 100644 index 00000000000..3f63ddfa0b5 --- /dev/null +++ b/gas/testsuite/gas/rx/satr.sm @@ -0,0 +1 @@ + satr diff --git a/gas/testsuite/gas/rx/sbb.d b/gas/testsuite/gas/rx/sbb.d new file mode 100644 index 00000000000..2fe71e18660 --- /dev/null +++ b/gas/testsuite/gas/rx/sbb.d @@ -0,0 +1,40 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc 03 00 sbb r0, r0 + 3: fc 03 0f sbb r0, r15 + 6: fc 03 f0 sbb r15, r0 + 9: fc 03 ff sbb r15, r15 + c: 06 a0 00 00 sbb \[r0\]\.l, r0 + 10: 06 a0 00 0f sbb \[r0\]\.l, r15 + 14: 06 a0 00 f0 sbb \[r15\]\.l, r0 + 18: 06 a0 00 ff sbb \[r15\]\.l, r15 + 1c: 06 a1 00 00 3f sbb 252\[r0\]\.l, r0 + 21: 06 a1 00 0f 3f sbb 252\[r0\]\.l, r15 + 26: 06 a1 00 f0 3f sbb 252\[r15\]\.l, r0 + 2b: 06 a1 00 ff 3f sbb 252\[r15\]\.l, r15 + 30: 06 a2 00 00 ff 3f sbb 65532\[r0\]\.l, r0 + 36: 06 a2 00 0f ff 3f sbb 65532\[r0\]\.l, r15 + 3c: 06 a2 00 f0 ff 3f sbb 65532\[r15\]\.l, r0 + 42: 06 a2 00 ff ff 3f sbb 65532\[r15\]\.l, r15 + 48: fd 74 20 7f adc #127, r0 + 4c: fd 74 2f 7f adc #127, r15 + 50: fd 74 20 80 adc #-128, r0 + 54: fd 74 2f 80 adc #-128, r15 + 58: fd 78 20 ff 7f adc #0x7fff, r0 + 5d: fd 78 2f ff 7f adc #0x7fff, r15 + 62: fd 7c 20 ff 7f ff adc #0xffff7fff, r0 + 68: fd 7c 2f ff 7f ff adc #0xffff7fff, r15 + 6e: fd 7c 20 ff ff 7f adc #0x7fffff, r0 + 74: fd 7c 2f ff ff 7f adc #0x7fffff, r15 + 7a: fd 7c 20 00 00 80 adc #0xff800000, r0 + 80: fd 7c 2f 00 00 80 adc #0xff800000, r15 + 86: fd 70 20 ff ff ff 7f adc #0x7fffffff, r0 + 8d: fd 70 2f ff ff ff 7f adc #0x7fffffff, r15 + 94: fd 70 20 00 00 00 80 adc #0x80000000, r0 + 9b: fd 70 2f 00 00 00 80 adc #0x80000000, r15 diff --git a/gas/testsuite/gas/rx/sbb.sm b/gas/testsuite/gas/rx/sbb.sm new file mode 100644 index 00000000000..b4939d9e416 --- /dev/null +++ b/gas/testsuite/gas/rx/sbb.sm @@ -0,0 +1,5 @@ + sbb {reg},{reg} + sbb {dsp}[{reg}].L,{reg} + + sbb #{imm},{reg} +# gas-specific macro for adc diff --git a/gas/testsuite/gas/rx/sccnd.d b/gas/testsuite/gas/rx/sccnd.d new file mode 100644 index 00000000000..a7485881160 --- /dev/null +++ b/gas/testsuite/gas/rx/sccnd.d @@ -0,0 +1,368 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc db 02 scc\.l r0 + 3: fc db f2 scc\.l r15 + 6: fc db 02 scc\.l r0 + 9: fc db f2 scc\.l r15 + c: fc db 00 sceq\.l r0 + f: fc db f0 sceq\.l r15 + 12: fc db 00 sceq\.l r0 + 15: fc db f0 sceq\.l r15 + 18: fc db 04 scgtu\.l r0 + 1b: fc db f4 scgtu\.l r15 + 1e: fc db 06 scpz\.l r0 + 21: fc db f6 scpz\.l r15 + 24: fc db 08 scge\.l r0 + 27: fc db f8 scge\.l r15 + 2a: fc db 0a scgt\.l r0 + 2d: fc db fa scgt\.l r15 + 30: fc db 0c sco\.l r0 + 33: fc db fc sco\.l r15 + 36: fc db 03 scnc\.l r0 + 39: fc db f3 scnc\.l r15 + 3c: fc db 03 scnc\.l r0 + 3f: fc db f3 scnc\.l r15 + 42: fc db 01 scne\.l r0 + 45: fc db f1 scne\.l r15 + 48: fc db 01 scne\.l r0 + 4b: fc db f1 scne\.l r15 + 4e: fc db 05 scleu\.l r0 + 51: fc db f5 scleu\.l r15 + 54: fc db 07 scn\.l r0 + 57: fc db f7 scn\.l r15 + 5a: fc db 09 sclt\.l r0 + 5d: fc db f9 sclt\.l r15 + 60: fc db 0b scle\.l r0 + 63: fc db fb scle\.l r15 + 66: fc db 0d scno\.l r0 + 69: fc db fd scno\.l r15 + 6c: fc d0 02 scc\.b \[r0\] + 6f: fc d0 f2 scc\.b \[r15\] + 72: fc d1 02 fc scc\.b 252\[r0\] + 76: fc d1 f2 fc scc\.b 252\[r15\] + 7a: fc d2 02 fc ff scc\.b 65532\[r0\] + 7f: fc d2 f2 fc ff scc\.b 65532\[r15\] + 84: fc d4 02 scc\.w \[r0\] + 87: fc d4 f2 scc\.w \[r15\] + 8a: fc d5 02 7e scc\.w 252\[r0\] + 8e: fc d5 f2 7e scc\.w 252\[r15\] + 92: fc d6 02 fe 7f scc\.w 65532\[r0\] + 97: fc d6 f2 fe 7f scc\.w 65532\[r15\] + 9c: fc d8 02 scc\.l \[r0\] + 9f: fc d8 f2 scc\.l \[r15\] + a2: fc d9 02 3f scc\.l 252\[r0\] + a6: fc d9 f2 3f scc\.l 252\[r15\] + aa: fc da 02 ff 3f scc\.l 65532\[r0\] + af: fc da f2 ff 3f scc\.l 65532\[r15\] + b4: fc d0 02 scc\.b \[r0\] + b7: fc d0 f2 scc\.b \[r15\] + ba: fc d1 02 fc scc\.b 252\[r0\] + be: fc d1 f2 fc scc\.b 252\[r15\] + c2: fc d2 02 fc ff scc\.b 65532\[r0\] + c7: fc d2 f2 fc ff scc\.b 65532\[r15\] + cc: fc d4 02 scc\.w \[r0\] + cf: fc d4 f2 scc\.w \[r15\] + d2: fc d5 02 7e scc\.w 252\[r0\] + d6: fc d5 f2 7e scc\.w 252\[r15\] + da: fc d6 02 fe 7f scc\.w 65532\[r0\] + df: fc d6 f2 fe 7f scc\.w 65532\[r15\] + e4: fc d8 02 scc\.l \[r0\] + e7: fc d8 f2 scc\.l \[r15\] + ea: fc d9 02 3f scc\.l 252\[r0\] + ee: fc d9 f2 3f scc\.l 252\[r15\] + f2: fc da 02 ff 3f scc\.l 65532\[r0\] + f7: fc da f2 ff 3f scc\.l 65532\[r15\] + fc: fc d0 00 sceq\.b \[r0\] + ff: fc d0 f0 sceq\.b \[r15\] + 102: fc d1 00 fc sceq\.b 252\[r0\] + 106: fc d1 f0 fc sceq\.b 252\[r15\] + 10a: fc d2 00 fc ff sceq\.b 65532\[r0\] + 10f: fc d2 f0 fc ff sceq\.b 65532\[r15\] + 114: fc d4 00 sceq\.w \[r0\] + 117: fc d4 f0 sceq\.w \[r15\] + 11a: fc d5 00 7e sceq\.w 252\[r0\] + 11e: fc d5 f0 7e sceq\.w 252\[r15\] + 122: fc d6 00 fe 7f sceq\.w 65532\[r0\] + 127: fc d6 f0 fe 7f sceq\.w 65532\[r15\] + 12c: fc d8 00 sceq\.l \[r0\] + 12f: fc d8 f0 sceq\.l \[r15\] + 132: fc d9 00 3f sceq\.l 252\[r0\] + 136: fc d9 f0 3f sceq\.l 252\[r15\] + 13a: fc da 00 ff 3f sceq\.l 65532\[r0\] + 13f: fc da f0 ff 3f sceq\.l 65532\[r15\] + 144: fc d0 00 sceq\.b \[r0\] + 147: fc d0 f0 sceq\.b \[r15\] + 14a: fc d1 00 fc sceq\.b 252\[r0\] + 14e: fc d1 f0 fc sceq\.b 252\[r15\] + 152: fc d2 00 fc ff sceq\.b 65532\[r0\] + 157: fc d2 f0 fc ff sceq\.b 65532\[r15\] + 15c: fc d4 00 sceq\.w \[r0\] + 15f: fc d4 f0 sceq\.w \[r15\] + 162: fc d5 00 7e sceq\.w 252\[r0\] + 166: fc d5 f0 7e sceq\.w 252\[r15\] + 16a: fc d6 00 fe 7f sceq\.w 65532\[r0\] + 16f: fc d6 f0 fe 7f sceq\.w 65532\[r15\] + 174: fc d8 00 sceq\.l \[r0\] + 177: fc d8 f0 sceq\.l \[r15\] + 17a: fc d9 00 3f sceq\.l 252\[r0\] + 17e: fc d9 f0 3f sceq\.l 252\[r15\] + 182: fc da 00 ff 3f sceq\.l 65532\[r0\] + 187: fc da f0 ff 3f sceq\.l 65532\[r15\] + 18c: fc d0 04 scgtu\.b \[r0\] + 18f: fc d0 f4 scgtu\.b \[r15\] + 192: fc d1 04 fc scgtu\.b 252\[r0\] + 196: fc d1 f4 fc scgtu\.b 252\[r15\] + 19a: fc d2 04 fc ff scgtu\.b 65532\[r0\] + 19f: fc d2 f4 fc ff scgtu\.b 65532\[r15\] + 1a4: fc d4 04 scgtu\.w \[r0\] + 1a7: fc d4 f4 scgtu\.w \[r15\] + 1aa: fc d5 04 7e scgtu\.w 252\[r0\] + 1ae: fc d5 f4 7e scgtu\.w 252\[r15\] + 1b2: fc d6 04 fe 7f scgtu\.w 65532\[r0\] + 1b7: fc d6 f4 fe 7f scgtu\.w 65532\[r15\] + 1bc: fc d8 04 scgtu\.l \[r0\] + 1bf: fc d8 f4 scgtu\.l \[r15\] + 1c2: fc d9 04 3f scgtu\.l 252\[r0\] + 1c6: fc d9 f4 3f scgtu\.l 252\[r15\] + 1ca: fc da 04 ff 3f scgtu\.l 65532\[r0\] + 1cf: fc da f4 ff 3f scgtu\.l 65532\[r15\] + 1d4: fc d0 06 scpz\.b \[r0\] + 1d7: fc d0 f6 scpz\.b \[r15\] + 1da: fc d1 06 fc scpz\.b 252\[r0\] + 1de: fc d1 f6 fc scpz\.b 252\[r15\] + 1e2: fc d2 06 fc ff scpz\.b 65532\[r0\] + 1e7: fc d2 f6 fc ff scpz\.b 65532\[r15\] + 1ec: fc d4 06 scpz\.w \[r0\] + 1ef: fc d4 f6 scpz\.w \[r15\] + 1f2: fc d5 06 7e scpz\.w 252\[r0\] + 1f6: fc d5 f6 7e scpz\.w 252\[r15\] + 1fa: fc d6 06 fe 7f scpz\.w 65532\[r0\] + 1ff: fc d6 f6 fe 7f scpz\.w 65532\[r15\] + 204: fc d8 06 scpz\.l \[r0\] + 207: fc d8 f6 scpz\.l \[r15\] + 20a: fc d9 06 3f scpz\.l 252\[r0\] + 20e: fc d9 f6 3f scpz\.l 252\[r15\] + 212: fc da 06 ff 3f scpz\.l 65532\[r0\] + 217: fc da f6 ff 3f scpz\.l 65532\[r15\] + 21c: fc d0 08 scge\.b \[r0\] + 21f: fc d0 f8 scge\.b \[r15\] + 222: fc d1 08 fc scge\.b 252\[r0\] + 226: fc d1 f8 fc scge\.b 252\[r15\] + 22a: fc d2 08 fc ff scge\.b 65532\[r0\] + 22f: fc d2 f8 fc ff scge\.b 65532\[r15\] + 234: fc d4 08 scge\.w \[r0\] + 237: fc d4 f8 scge\.w \[r15\] + 23a: fc d5 08 7e scge\.w 252\[r0\] + 23e: fc d5 f8 7e scge\.w 252\[r15\] + 242: fc d6 08 fe 7f scge\.w 65532\[r0\] + 247: fc d6 f8 fe 7f scge\.w 65532\[r15\] + 24c: fc d8 08 scge\.l \[r0\] + 24f: fc d8 f8 scge\.l \[r15\] + 252: fc d9 08 3f scge\.l 252\[r0\] + 256: fc d9 f8 3f scge\.l 252\[r15\] + 25a: fc da 08 ff 3f scge\.l 65532\[r0\] + 25f: fc da f8 ff 3f scge\.l 65532\[r15\] + 264: fc d0 0a scgt\.b \[r0\] + 267: fc d0 fa scgt\.b \[r15\] + 26a: fc d1 0a fc scgt\.b 252\[r0\] + 26e: fc d1 fa fc scgt\.b 252\[r15\] + 272: fc d2 0a fc ff scgt\.b 65532\[r0\] + 277: fc d2 fa fc ff scgt\.b 65532\[r15\] + 27c: fc d4 0a scgt\.w \[r0\] + 27f: fc d4 fa scgt\.w \[r15\] + 282: fc d5 0a 7e scgt\.w 252\[r0\] + 286: fc d5 fa 7e scgt\.w 252\[r15\] + 28a: fc d6 0a fe 7f scgt\.w 65532\[r0\] + 28f: fc d6 fa fe 7f scgt\.w 65532\[r15\] + 294: fc d8 0a scgt\.l \[r0\] + 297: fc d8 fa scgt\.l \[r15\] + 29a: fc d9 0a 3f scgt\.l 252\[r0\] + 29e: fc d9 fa 3f scgt\.l 252\[r15\] + 2a2: fc da 0a ff 3f scgt\.l 65532\[r0\] + 2a7: fc da fa ff 3f scgt\.l 65532\[r15\] + 2ac: fc d0 0c sco\.b \[r0\] + 2af: fc d0 fc sco\.b \[r15\] + 2b2: fc d1 0c fc sco\.b 252\[r0\] + 2b6: fc d1 fc fc sco\.b 252\[r15\] + 2ba: fc d2 0c fc ff sco\.b 65532\[r0\] + 2bf: fc d2 fc fc ff sco\.b 65532\[r15\] + 2c4: fc d4 0c sco\.w \[r0\] + 2c7: fc d4 fc sco\.w \[r15\] + 2ca: fc d5 0c 7e sco\.w 252\[r0\] + 2ce: fc d5 fc 7e sco\.w 252\[r15\] + 2d2: fc d6 0c fe 7f sco\.w 65532\[r0\] + 2d7: fc d6 fc fe 7f sco\.w 65532\[r15\] + 2dc: fc d8 0c sco\.l \[r0\] + 2df: fc d8 fc sco\.l \[r15\] + 2e2: fc d9 0c 3f sco\.l 252\[r0\] + 2e6: fc d9 fc 3f sco\.l 252\[r15\] + 2ea: fc da 0c ff 3f sco\.l 65532\[r0\] + 2ef: fc da fc ff 3f sco\.l 65532\[r15\] + 2f4: fc d0 03 scnc\.b \[r0\] + 2f7: fc d0 f3 scnc\.b \[r15\] + 2fa: fc d1 03 fc scnc\.b 252\[r0\] + 2fe: fc d1 f3 fc scnc\.b 252\[r15\] + 302: fc d2 03 fc ff scnc\.b 65532\[r0\] + 307: fc d2 f3 fc ff scnc\.b 65532\[r15\] + 30c: fc d4 03 scnc\.w \[r0\] + 30f: fc d4 f3 scnc\.w \[r15\] + 312: fc d5 03 7e scnc\.w 252\[r0\] + 316: fc d5 f3 7e scnc\.w 252\[r15\] + 31a: fc d6 03 fe 7f scnc\.w 65532\[r0\] + 31f: fc d6 f3 fe 7f scnc\.w 65532\[r15\] + 324: fc d8 03 scnc\.l \[r0\] + 327: fc d8 f3 scnc\.l \[r15\] + 32a: fc d9 03 3f scnc\.l 252\[r0\] + 32e: fc d9 f3 3f scnc\.l 252\[r15\] + 332: fc da 03 ff 3f scnc\.l 65532\[r0\] + 337: fc da f3 ff 3f scnc\.l 65532\[r15\] + 33c: fc d0 03 scnc\.b \[r0\] + 33f: fc d0 f3 scnc\.b \[r15\] + 342: fc d1 03 fc scnc\.b 252\[r0\] + 346: fc d1 f3 fc scnc\.b 252\[r15\] + 34a: fc d2 03 fc ff scnc\.b 65532\[r0\] + 34f: fc d2 f3 fc ff scnc\.b 65532\[r15\] + 354: fc d4 03 scnc\.w \[r0\] + 357: fc d4 f3 scnc\.w \[r15\] + 35a: fc d5 03 7e scnc\.w 252\[r0\] + 35e: fc d5 f3 7e scnc\.w 252\[r15\] + 362: fc d6 03 fe 7f scnc\.w 65532\[r0\] + 367: fc d6 f3 fe 7f scnc\.w 65532\[r15\] + 36c: fc d8 03 scnc\.l \[r0\] + 36f: fc d8 f3 scnc\.l \[r15\] + 372: fc d9 03 3f scnc\.l 252\[r0\] + 376: fc d9 f3 3f scnc\.l 252\[r15\] + 37a: fc da 03 ff 3f scnc\.l 65532\[r0\] + 37f: fc da f3 ff 3f scnc\.l 65532\[r15\] + 384: fc d0 01 scne\.b \[r0\] + 387: fc d0 f1 scne\.b \[r15\] + 38a: fc d1 01 fc scne\.b 252\[r0\] + 38e: fc d1 f1 fc scne\.b 252\[r15\] + 392: fc d2 01 fc ff scne\.b 65532\[r0\] + 397: fc d2 f1 fc ff scne\.b 65532\[r15\] + 39c: fc d4 01 scne\.w \[r0\] + 39f: fc d4 f1 scne\.w \[r15\] + 3a2: fc d5 01 7e scne\.w 252\[r0\] + 3a6: fc d5 f1 7e scne\.w 252\[r15\] + 3aa: fc d6 01 fe 7f scne\.w 65532\[r0\] + 3af: fc d6 f1 fe 7f scne\.w 65532\[r15\] + 3b4: fc d8 01 scne\.l \[r0\] + 3b7: fc d8 f1 scne\.l \[r15\] + 3ba: fc d9 01 3f scne\.l 252\[r0\] + 3be: fc d9 f1 3f scne\.l 252\[r15\] + 3c2: fc da 01 ff 3f scne\.l 65532\[r0\] + 3c7: fc da f1 ff 3f scne\.l 65532\[r15\] + 3cc: fc d0 01 scne\.b \[r0\] + 3cf: fc d0 f1 scne\.b \[r15\] + 3d2: fc d1 01 fc scne\.b 252\[r0\] + 3d6: fc d1 f1 fc scne\.b 252\[r15\] + 3da: fc d2 01 fc ff scne\.b 65532\[r0\] + 3df: fc d2 f1 fc ff scne\.b 65532\[r15\] + 3e4: fc d4 01 scne\.w \[r0\] + 3e7: fc d4 f1 scne\.w \[r15\] + 3ea: fc d5 01 7e scne\.w 252\[r0\] + 3ee: fc d5 f1 7e scne\.w 252\[r15\] + 3f2: fc d6 01 fe 7f scne\.w 65532\[r0\] + 3f7: fc d6 f1 fe 7f scne\.w 65532\[r15\] + 3fc: fc d8 01 scne\.l \[r0\] + 3ff: fc d8 f1 scne\.l \[r15\] + 402: fc d9 01 3f scne\.l 252\[r0\] + 406: fc d9 f1 3f scne\.l 252\[r15\] + 40a: fc da 01 ff 3f scne\.l 65532\[r0\] + 40f: fc da f1 ff 3f scne\.l 65532\[r15\] + 414: fc d0 05 scleu\.b \[r0\] + 417: fc d0 f5 scleu\.b \[r15\] + 41a: fc d1 05 fc scleu\.b 252\[r0\] + 41e: fc d1 f5 fc scleu\.b 252\[r15\] + 422: fc d2 05 fc ff scleu\.b 65532\[r0\] + 427: fc d2 f5 fc ff scleu\.b 65532\[r15\] + 42c: fc d4 05 scleu\.w \[r0\] + 42f: fc d4 f5 scleu\.w \[r15\] + 432: fc d5 05 7e scleu\.w 252\[r0\] + 436: fc d5 f5 7e scleu\.w 252\[r15\] + 43a: fc d6 05 fe 7f scleu\.w 65532\[r0\] + 43f: fc d6 f5 fe 7f scleu\.w 65532\[r15\] + 444: fc d8 05 scleu\.l \[r0\] + 447: fc d8 f5 scleu\.l \[r15\] + 44a: fc d9 05 3f scleu\.l 252\[r0\] + 44e: fc d9 f5 3f scleu\.l 252\[r15\] + 452: fc da 05 ff 3f scleu\.l 65532\[r0\] + 457: fc da f5 ff 3f scleu\.l 65532\[r15\] + 45c: fc d0 07 scn\.b \[r0\] + 45f: fc d0 f7 scn\.b \[r15\] + 462: fc d1 07 fc scn\.b 252\[r0\] + 466: fc d1 f7 fc scn\.b 252\[r15\] + 46a: fc d2 07 fc ff scn\.b 65532\[r0\] + 46f: fc d2 f7 fc ff scn\.b 65532\[r15\] + 474: fc d4 07 scn\.w \[r0\] + 477: fc d4 f7 scn\.w \[r15\] + 47a: fc d5 07 7e scn\.w 252\[r0\] + 47e: fc d5 f7 7e scn\.w 252\[r15\] + 482: fc d6 07 fe 7f scn\.w 65532\[r0\] + 487: fc d6 f7 fe 7f scn\.w 65532\[r15\] + 48c: fc d8 07 scn\.l \[r0\] + 48f: fc d8 f7 scn\.l \[r15\] + 492: fc d9 07 3f scn\.l 252\[r0\] + 496: fc d9 f7 3f scn\.l 252\[r15\] + 49a: fc da 07 ff 3f scn\.l 65532\[r0\] + 49f: fc da f7 ff 3f scn\.l 65532\[r15\] + 4a4: fc d0 09 sclt\.b \[r0\] + 4a7: fc d0 f9 sclt\.b \[r15\] + 4aa: fc d1 09 fc sclt\.b 252\[r0\] + 4ae: fc d1 f9 fc sclt\.b 252\[r15\] + 4b2: fc d2 09 fc ff sclt\.b 65532\[r0\] + 4b7: fc d2 f9 fc ff sclt\.b 65532\[r15\] + 4bc: fc d4 09 sclt\.w \[r0\] + 4bf: fc d4 f9 sclt\.w \[r15\] + 4c2: fc d5 09 7e sclt\.w 252\[r0\] + 4c6: fc d5 f9 7e sclt\.w 252\[r15\] + 4ca: fc d6 09 fe 7f sclt\.w 65532\[r0\] + 4cf: fc d6 f9 fe 7f sclt\.w 65532\[r15\] + 4d4: fc d8 09 sclt\.l \[r0\] + 4d7: fc d8 f9 sclt\.l \[r15\] + 4da: fc d9 09 3f sclt\.l 252\[r0\] + 4de: fc d9 f9 3f sclt\.l 252\[r15\] + 4e2: fc da 09 ff 3f sclt\.l 65532\[r0\] + 4e7: fc da f9 ff 3f sclt\.l 65532\[r15\] + 4ec: fc d0 0b scle\.b \[r0\] + 4ef: fc d0 fb scle\.b \[r15\] + 4f2: fc d1 0b fc scle\.b 252\[r0\] + 4f6: fc d1 fb fc scle\.b 252\[r15\] + 4fa: fc d2 0b fc ff scle\.b 65532\[r0\] + 4ff: fc d2 fb fc ff scle\.b 65532\[r15\] + 504: fc d4 0b scle\.w \[r0\] + 507: fc d4 fb scle\.w \[r15\] + 50a: fc d5 0b 7e scle\.w 252\[r0\] + 50e: fc d5 fb 7e scle\.w 252\[r15\] + 512: fc d6 0b fe 7f scle\.w 65532\[r0\] + 517: fc d6 fb fe 7f scle\.w 65532\[r15\] + 51c: fc d8 0b scle\.l \[r0\] + 51f: fc d8 fb scle\.l \[r15\] + 522: fc d9 0b 3f scle\.l 252\[r0\] + 526: fc d9 fb 3f scle\.l 252\[r15\] + 52a: fc da 0b ff 3f scle\.l 65532\[r0\] + 52f: fc da fb ff 3f scle\.l 65532\[r15\] + 534: fc d0 0d scno\.b \[r0\] + 537: fc d0 fd scno\.b \[r15\] + 53a: fc d1 0d fc scno\.b 252\[r0\] + 53e: fc d1 fd fc scno\.b 252\[r15\] + 542: fc d2 0d fc ff scno\.b 65532\[r0\] + 547: fc d2 fd fc ff scno\.b 65532\[r15\] + 54c: fc d4 0d scno\.w \[r0\] + 54f: fc d4 fd scno\.w \[r15\] + 552: fc d5 0d 7e scno\.w 252\[r0\] + 556: fc d5 fd 7e scno\.w 252\[r15\] + 55a: fc d6 0d fe 7f scno\.w 65532\[r0\] + 55f: fc d6 fd fe 7f scno\.w 65532\[r15\] + 564: fc d8 0d scno\.l \[r0\] + 567: fc d8 fd scno\.l \[r15\] + 56a: fc d9 0d 3f scno\.l 252\[r0\] + 56e: fc d9 fd 3f scno\.l 252\[r15\] + 572: fc da 0d ff 3f scno\.l 65532\[r0\] + 577: fc da fd ff 3f scno\.l 65532\[r15\] diff --git a/gas/testsuite/gas/rx/sccnd.sm b/gas/testsuite/gas/rx/sccnd.sm new file mode 100644 index 00000000000..7ad08f9e7d6 --- /dev/null +++ b/gas/testsuite/gas/rx/sccnd.sm @@ -0,0 +1,3 @@ + sc{cnd}.L {reg} + sc{cnd}{bwl} {mem} + diff --git a/gas/testsuite/gas/rx/scmpu.d b/gas/testsuite/gas/rx/scmpu.d new file mode 100644 index 00000000000..b309e67b5f8 --- /dev/null +++ b/gas/testsuite/gas/rx/scmpu.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 83 scmpu diff --git a/gas/testsuite/gas/rx/scmpu.sm b/gas/testsuite/gas/rx/scmpu.sm new file mode 100644 index 00000000000..b00d177e3b8 --- /dev/null +++ b/gas/testsuite/gas/rx/scmpu.sm @@ -0,0 +1 @@ + scmpu diff --git a/gas/testsuite/gas/rx/setpsw.d b/gas/testsuite/gas/rx/setpsw.d new file mode 100644 index 00000000000..a666758468f --- /dev/null +++ b/gas/testsuite/gas/rx/setpsw.d @@ -0,0 +1,14 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f a9 setpsw u + 2: 7f a8 setpsw i + 4: 7f a3 setpsw o + 6: 7f a2 setpsw s + 8: 7f a1 setpsw z + a: 7f a0 setpsw c diff --git a/gas/testsuite/gas/rx/setpsw.sm b/gas/testsuite/gas/rx/setpsw.sm new file mode 100644 index 00000000000..9c5445b2dbc --- /dev/null +++ b/gas/testsuite/gas/rx/setpsw.sm @@ -0,0 +1 @@ + setpsw {pswf} diff --git a/gas/testsuite/gas/rx/shar.d b/gas/testsuite/gas/rx/shar.d new file mode 100644 index 00000000000..8398cc789bf --- /dev/null +++ b/gas/testsuite/gas/rx/shar.d @@ -0,0 +1,24 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 6a 00 shar #0, r0 + 2: 6a 0f shar #0, r15 + 4: 6b f0 shar #31, r0 + 6: 6b ff shar #31, r15 + 8: fd 61 00 shar r0, r0 + b: fd 61 0f shar r0, r15 + e: fd 61 f0 shar r15, r0 + 11: fd 61 ff shar r15, r15 + 14: fd a0 00 shar #0, r0, r0 + 17: fd a0 0f shar #0, r0, r15 + 1a: fd a0 f0 shar #0, r15, r0 + 1d: fd a0 ff shar #0, r15, r15 + 20: fd bf 00 shar #31, r0, r0 + 23: fd bf 0f shar #31, r0, r15 + 26: fd bf f0 shar #31, r15, r0 + 29: fd bf ff shar #31, r15, r15 diff --git a/gas/testsuite/gas/rx/shar.sm b/gas/testsuite/gas/rx/shar.sm new file mode 100644 index 00000000000..e2d21895ec8 --- /dev/null +++ b/gas/testsuite/gas/rx/shar.sm @@ -0,0 +1,3 @@ + shar #{uimm5},{reg} + shar {reg},{reg} + shar #{uimm5},{reg},{reg} diff --git a/gas/testsuite/gas/rx/shll.d b/gas/testsuite/gas/rx/shll.d new file mode 100644 index 00000000000..642c6fd95cb --- /dev/null +++ b/gas/testsuite/gas/rx/shll.d @@ -0,0 +1,24 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 6c 00 shll #0, r0 + 2: 6c 0f shll #0, r15 + 4: 6d f0 shll #31, r0 + 6: 6d ff shll #31, r15 + 8: fd 62 00 shll r0, r0 + b: fd 62 0f shll r0, r15 + e: fd 62 f0 shll r15, r0 + 11: fd 62 ff shll r15, r15 + 14: fd c0 00 shll #0, r0, r0 + 17: fd c0 0f shll #0, r0, r15 + 1a: fd c0 f0 shll #0, r15, r0 + 1d: fd c0 ff shll #0, r15, r15 + 20: fd df 00 shll #31, r0, r0 + 23: fd df 0f shll #31, r0, r15 + 26: fd df f0 shll #31, r15, r0 + 29: fd df ff shll #31, r15, r15 diff --git a/gas/testsuite/gas/rx/shll.sm b/gas/testsuite/gas/rx/shll.sm new file mode 100644 index 00000000000..e4544b1e33e --- /dev/null +++ b/gas/testsuite/gas/rx/shll.sm @@ -0,0 +1,3 @@ + shll #{uimm5},{reg} + shll {reg},{reg} + shll #{uimm5},{reg},{reg} diff --git a/gas/testsuite/gas/rx/shlr.d b/gas/testsuite/gas/rx/shlr.d new file mode 100644 index 00000000000..1f4628c8eb0 --- /dev/null +++ b/gas/testsuite/gas/rx/shlr.d @@ -0,0 +1,24 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 68 00 shlr #0, r0 + 2: 68 0f shlr #0, r15 + 4: 69 f0 shlr #31, r0 + 6: 69 ff shlr #31, r15 + 8: fd 60 00 shlr r0, r0 + b: fd 60 0f shlr r0, r15 + e: fd 60 f0 shlr r15, r0 + 11: fd 60 ff shlr r15, r15 + 14: fd 80 00 shlr #0, r0, r0 + 17: fd 80 0f shlr #0, r0, r15 + 1a: fd 80 f0 shlr #0, r15, r0 + 1d: fd 80 ff shlr #0, r15, r15 + 20: fd 9f 00 shlr #31, r0, r0 + 23: fd 9f 0f shlr #31, r0, r15 + 26: fd 9f f0 shlr #31, r15, r0 + 29: fd 9f ff shlr #31, r15, r15 diff --git a/gas/testsuite/gas/rx/shlr.sm b/gas/testsuite/gas/rx/shlr.sm new file mode 100644 index 00000000000..1ce434fb6c3 --- /dev/null +++ b/gas/testsuite/gas/rx/shlr.sm @@ -0,0 +1,3 @@ + shlr #{uimm5},{reg} + shlr {reg},{reg} + shlr #{uimm5},{reg},{reg} diff --git a/gas/testsuite/gas/rx/smovb.d b/gas/testsuite/gas/rx/smovb.d new file mode 100644 index 00000000000..1a1d6f7bc99 --- /dev/null +++ b/gas/testsuite/gas/rx/smovb.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 8b smovb diff --git a/gas/testsuite/gas/rx/smovb.sm b/gas/testsuite/gas/rx/smovb.sm new file mode 100644 index 00000000000..5197e8d7e8e --- /dev/null +++ b/gas/testsuite/gas/rx/smovb.sm @@ -0,0 +1 @@ + smovb diff --git a/gas/testsuite/gas/rx/smovf.d b/gas/testsuite/gas/rx/smovf.d new file mode 100644 index 00000000000..160d7c2cbc9 --- /dev/null +++ b/gas/testsuite/gas/rx/smovf.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 8f smovf diff --git a/gas/testsuite/gas/rx/smovf.sm b/gas/testsuite/gas/rx/smovf.sm new file mode 100644 index 00000000000..0f36b840ca0 --- /dev/null +++ b/gas/testsuite/gas/rx/smovf.sm @@ -0,0 +1 @@ + smovf diff --git a/gas/testsuite/gas/rx/smovu.d b/gas/testsuite/gas/rx/smovu.d new file mode 100644 index 00000000000..029aeb97203 --- /dev/null +++ b/gas/testsuite/gas/rx/smovu.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 87 smovu diff --git a/gas/testsuite/gas/rx/smovu.sm b/gas/testsuite/gas/rx/smovu.sm new file mode 100644 index 00000000000..a0c53e7f281 --- /dev/null +++ b/gas/testsuite/gas/rx/smovu.sm @@ -0,0 +1 @@ + smovu diff --git a/gas/testsuite/gas/rx/sstr.d b/gas/testsuite/gas/rx/sstr.d new file mode 100644 index 00000000000..c6994b5e799 --- /dev/null +++ b/gas/testsuite/gas/rx/sstr.d @@ -0,0 +1,11 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 88 sstr\.b + 2: 7f 89 sstr\.w + 4: 7f 8a sstr\.l diff --git a/gas/testsuite/gas/rx/sstr.sm b/gas/testsuite/gas/rx/sstr.sm new file mode 100644 index 00000000000..e6873950a9e --- /dev/null +++ b/gas/testsuite/gas/rx/sstr.sm @@ -0,0 +1 @@ + sstr{bwl} diff --git a/gas/testsuite/gas/rx/stnz.d b/gas/testsuite/gas/rx/stnz.d new file mode 100644 index 00000000000..8dfb0c3c377 --- /dev/null +++ b/gas/testsuite/gas/rx/stnz.d @@ -0,0 +1,24 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 f0 80 stnz #-128, r0 + 4: fd 74 ff 80 stnz #-128, r15 + 8: fd 74 f0 7f stnz #127, r0 + c: fd 74 ff 7f stnz #127, r15 + 10: fd 78 f0 00 80 stnz #0xffff8000, r0 + 15: fd 78 ff 00 80 stnz #0xffff8000, r15 + 1a: fd 7c f0 00 80 00 stnz #0x8000, r0 + 20: fd 7c ff 00 80 00 stnz #0x8000, r15 + 26: fd 7c f0 00 00 80 stnz #0xff800000, r0 + 2c: fd 7c ff 00 00 80 stnz #0xff800000, r15 + 32: fd 7c f0 ff ff 7f stnz #0x7fffff, r0 + 38: fd 7c ff ff ff 7f stnz #0x7fffff, r15 + 3e: fd 70 f0 00 00 00 80 stnz #0x80000000, r0 + 45: fd 70 ff 00 00 00 80 stnz #0x80000000, r15 + 4c: fd 70 f0 ff ff ff 7f stnz #0x7fffffff, r0 + 53: fd 70 ff ff ff ff 7f stnz #0x7fffffff, r15 diff --git a/gas/testsuite/gas/rx/stnz.sm b/gas/testsuite/gas/rx/stnz.sm new file mode 100644 index 00000000000..853f1ce96ed --- /dev/null +++ b/gas/testsuite/gas/rx/stnz.sm @@ -0,0 +1 @@ + stnz #{imm},{reg} diff --git a/gas/testsuite/gas/rx/stz.d b/gas/testsuite/gas/rx/stz.d new file mode 100644 index 00000000000..f9c6b77cb8f --- /dev/null +++ b/gas/testsuite/gas/rx/stz.d @@ -0,0 +1,24 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 e0 80 stz #-128, r0 + 4: fd 74 ef 80 stz #-128, r15 + 8: fd 74 e0 7f stz #127, r0 + c: fd 74 ef 7f stz #127, r15 + 10: fd 78 e0 00 80 stz #0xffff8000, r0 + 15: fd 78 ef 00 80 stz #0xffff8000, r15 + 1a: fd 7c e0 00 80 00 stz #0x8000, r0 + 20: fd 7c ef 00 80 00 stz #0x8000, r15 + 26: fd 7c e0 00 00 80 stz #0xff800000, r0 + 2c: fd 7c ef 00 00 80 stz #0xff800000, r15 + 32: fd 7c e0 ff ff 7f stz #0x7fffff, r0 + 38: fd 7c ef ff ff 7f stz #0x7fffff, r15 + 3e: fd 70 e0 00 00 00 80 stz #0x80000000, r0 + 45: fd 70 ef 00 00 00 80 stz #0x80000000, r15 + 4c: fd 70 e0 ff ff ff 7f stz #0x7fffffff, r0 + 53: fd 70 ef ff ff ff 7f stz #0x7fffffff, r15 diff --git a/gas/testsuite/gas/rx/stz.sm b/gas/testsuite/gas/rx/stz.sm new file mode 100644 index 00000000000..e366213c268 --- /dev/null +++ b/gas/testsuite/gas/rx/stz.sm @@ -0,0 +1 @@ + stz #{imm},{reg} diff --git a/gas/testsuite/gas/rx/sub.d b/gas/testsuite/gas/rx/sub.d new file mode 100644 index 00000000000..af9ad295f59 --- /dev/null +++ b/gas/testsuite/gas/rx/sub.d @@ -0,0 +1,84 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 60 00 sub #0, r0 + 2: 60 0f sub #0, r15 + 4: 60 f0 sub #15, r0 + 6: 60 ff sub #15, r15 + 8: 43 00 sub r0, r0 + a: 43 0f sub r0, r15 + c: 43 f0 sub r15, r0 + e: 43 ff sub r15, r15 + 10: 40 00 sub \[r0\]\.ub, r0 + 12: 40 0f sub \[r0\]\.ub, r15 + 14: 06 00 00 sub \[r0\]\.b, r0 + 17: 06 00 0f sub \[r0\]\.b, r15 + 1a: 06 c0 00 sub \[r0\]\.uw, r0 + 1d: 06 c0 0f sub \[r0\]\.uw, r15 + 20: 06 40 00 sub \[r0\]\.w, r0 + 23: 06 40 0f sub \[r0\]\.w, r15 + 26: 06 80 00 sub \[r0\]\.l, r0 + 29: 06 80 0f sub \[r0\]\.l, r15 + 2c: 40 f0 sub \[r15\]\.ub, r0 + 2e: 40 ff sub \[r15\]\.ub, r15 + 30: 06 00 f0 sub \[r15\]\.b, r0 + 33: 06 00 ff sub \[r15\]\.b, r15 + 36: 06 c0 f0 sub \[r15\]\.uw, r0 + 39: 06 c0 ff sub \[r15\]\.uw, r15 + 3c: 06 40 f0 sub \[r15\]\.w, r0 + 3f: 06 40 ff sub \[r15\]\.w, r15 + 42: 06 80 f0 sub \[r15\]\.l, r0 + 45: 06 80 ff sub \[r15\]\.l, r15 + 48: 41 00 fc sub 252\[r0\]\.ub, r0 + 4b: 41 0f fc sub 252\[r0\]\.ub, r15 + 4e: 06 01 00 fc sub 252\[r0\]\.b, r0 + 52: 06 01 0f fc sub 252\[r0\]\.b, r15 + 56: 06 c1 00 7e sub 252\[r0\]\.uw, r0 + 5a: 06 c1 0f 7e sub 252\[r0\]\.uw, r15 + 5e: 06 41 00 7e sub 252\[r0\]\.w, r0 + 62: 06 41 0f 7e sub 252\[r0\]\.w, r15 + 66: 06 81 00 3f sub 252\[r0\]\.l, r0 + 6a: 06 81 0f 3f sub 252\[r0\]\.l, r15 + 6e: 41 f0 fc sub 252\[r15\]\.ub, r0 + 71: 41 ff fc sub 252\[r15\]\.ub, r15 + 74: 06 01 f0 fc sub 252\[r15\]\.b, r0 + 78: 06 01 ff fc sub 252\[r15\]\.b, r15 + 7c: 06 c1 f0 7e sub 252\[r15\]\.uw, r0 + 80: 06 c1 ff 7e sub 252\[r15\]\.uw, r15 + 84: 06 41 f0 7e sub 252\[r15\]\.w, r0 + 88: 06 41 ff 7e sub 252\[r15\]\.w, r15 + 8c: 06 81 f0 3f sub 252\[r15\]\.l, r0 + 90: 06 81 ff 3f sub 252\[r15\]\.l, r15 + 94: 42 00 fc ff sub 65532\[r0\]\.ub, r0 + 98: 42 0f fc ff sub 65532\[r0\]\.ub, r15 + 9c: 06 02 00 fc ff sub 65532\[r0\]\.b, r0 + a1: 06 02 0f fc ff sub 65532\[r0\]\.b, r15 + a6: 06 c2 00 fe 7f sub 65532\[r0\]\.uw, r0 + ab: 06 c2 0f fe 7f sub 65532\[r0\]\.uw, r15 + b0: 06 42 00 fe 7f sub 65532\[r0\]\.w, r0 + b5: 06 42 0f fe 7f sub 65532\[r0\]\.w, r15 + ba: 06 82 00 ff 3f sub 65532\[r0\]\.l, r0 + bf: 06 82 0f ff 3f sub 65532\[r0\]\.l, r15 + c4: 42 f0 fc ff sub 65532\[r15\]\.ub, r0 + c8: 42 ff fc ff sub 65532\[r15\]\.ub, r15 + cc: 06 02 f0 fc ff sub 65532\[r15\]\.b, r0 + d1: 06 02 ff fc ff sub 65532\[r15\]\.b, r15 + d6: 06 c2 f0 fe 7f sub 65532\[r15\]\.uw, r0 + db: 06 c2 ff fe 7f sub 65532\[r15\]\.uw, r15 + e0: 06 42 f0 fe 7f sub 65532\[r15\]\.w, r0 + e5: 06 42 ff fe 7f sub 65532\[r15\]\.w, r15 + ea: 06 82 f0 ff 3f sub 65532\[r15\]\.l, r0 + ef: 06 82 ff ff 3f sub 65532\[r15\]\.l, r15 + f4: ff 00 00 sub r0, r0, r0 + f7: ff 0f 00 sub r0, r0, r15 + fa: ff 00 0f sub r0, r15, r0 + fd: ff 0f 0f sub r0, r15, r15 + 100: ff 00 f0 sub r15, r0, r0 + 103: ff 0f f0 sub r15, r0, r15 + 106: ff 00 ff sub r15, r15, r0 + 109: ff 0f ff sub r15, r15, r15 diff --git a/gas/testsuite/gas/rx/sub.sm b/gas/testsuite/gas/rx/sub.sm new file mode 100644 index 00000000000..f21d9d5726f --- /dev/null +++ b/gas/testsuite/gas/rx/sub.sm @@ -0,0 +1,6 @@ + sub #{uimm4},{reg} + + sub {reg},{reg} + sub {memx},{reg} + + sub {reg},{reg},{reg} diff --git a/gas/testsuite/gas/rx/suntil.d b/gas/testsuite/gas/rx/suntil.d new file mode 100644 index 00000000000..c7f4538666a --- /dev/null +++ b/gas/testsuite/gas/rx/suntil.d @@ -0,0 +1,11 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 80 suntil\.b + 2: 7f 81 suntil\.w + 4: 7f 82 suntil\.l diff --git a/gas/testsuite/gas/rx/suntil.sm b/gas/testsuite/gas/rx/suntil.sm new file mode 100644 index 00000000000..5d849eae7bf --- /dev/null +++ b/gas/testsuite/gas/rx/suntil.sm @@ -0,0 +1 @@ + suntil{bwl} diff --git a/gas/testsuite/gas/rx/swhile.d b/gas/testsuite/gas/rx/swhile.d new file mode 100644 index 00000000000..2c3ea0dada6 --- /dev/null +++ b/gas/testsuite/gas/rx/swhile.d @@ -0,0 +1,11 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 84 swhile\.b + 2: 7f 85 swhile\.w + 4: 7f 86 swhile\.l diff --git a/gas/testsuite/gas/rx/swhile.sm b/gas/testsuite/gas/rx/swhile.sm new file mode 100644 index 00000000000..bb5c7428847 --- /dev/null +++ b/gas/testsuite/gas/rx/swhile.sm @@ -0,0 +1 @@ + swhile{bwl} diff --git a/gas/testsuite/gas/rx/tst.d b/gas/testsuite/gas/rx/tst.d new file mode 100644 index 00000000000..1aca36320d7 --- /dev/null +++ b/gas/testsuite/gas/rx/tst.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 c0 80 tst #-128, r0 + 4: fd 74 cf 80 tst #-128, r15 + 8: fd 74 c0 7f tst #127, r0 + c: fd 74 cf 7f tst #127, r15 + 10: fd 78 c0 00 80 tst #0xffff8000, r0 + 15: fd 78 cf 00 80 tst #0xffff8000, r15 + 1a: fd 7c c0 00 80 00 tst #0x8000, r0 + 20: fd 7c cf 00 80 00 tst #0x8000, r15 + 26: fd 7c c0 00 00 80 tst #0xff800000, r0 + 2c: fd 7c cf 00 00 80 tst #0xff800000, r15 + 32: fd 7c c0 ff ff 7f tst #0x7fffff, r0 + 38: fd 7c cf ff ff 7f tst #0x7fffff, r15 + 3e: fd 70 c0 00 00 00 80 tst #0x80000000, r0 + 45: fd 70 cf 00 00 00 80 tst #0x80000000, r15 + 4c: fd 70 c0 ff ff ff 7f tst #0x7fffffff, r0 + 53: fd 70 cf ff ff ff 7f tst #0x7fffffff, r15 + 5a: fc 33 00 tst r0, r0 + 5d: fc 33 0f tst r0, r15 + 60: fc 33 f0 tst r15, r0 + 63: fc 33 ff tst r15, r15 + 66: fc 30 00 tst \[r0\]\.ub, r0 + 69: fc 30 0f tst \[r0\]\.ub, r15 + 6c: 06 20 0c 00 tst \[r0\]\.b, r0 + 70: 06 20 0c 0f tst \[r0\]\.b, r15 + 74: 06 e0 0c 00 tst \[r0\]\.uw, r0 + 78: 06 e0 0c 0f tst \[r0\]\.uw, r15 + 7c: 06 60 0c 00 tst \[r0\]\.w, r0 + 80: 06 60 0c 0f tst \[r0\]\.w, r15 + 84: 06 a0 0c 00 tst \[r0\]\.l, r0 + 88: 06 a0 0c 0f tst \[r0\]\.l, r15 + 8c: fc 30 f0 tst \[r15\]\.ub, r0 + 8f: fc 30 ff tst \[r15\]\.ub, r15 + 92: 06 20 0c f0 tst \[r15\]\.b, r0 + 96: 06 20 0c ff tst \[r15\]\.b, r15 + 9a: 06 e0 0c f0 tst \[r15\]\.uw, r0 + 9e: 06 e0 0c ff tst \[r15\]\.uw, r15 + a2: 06 60 0c f0 tst \[r15\]\.w, r0 + a6: 06 60 0c ff tst \[r15\]\.w, r15 + aa: 06 a0 0c f0 tst \[r15\]\.l, r0 + ae: 06 a0 0c ff tst \[r15\]\.l, r15 + b2: fc 31 00 fc tst 252\[r0\]\.ub, r0 + b6: fc 31 0f fc tst 252\[r0\]\.ub, r15 + ba: 06 21 0c 00 fc tst 252\[r0\]\.b, r0 + bf: 06 21 0c 0f fc tst 252\[r0\]\.b, r15 + c4: 06 e1 0c 00 7e tst 252\[r0\]\.uw, r0 + c9: 06 e1 0c 0f 7e tst 252\[r0\]\.uw, r15 + ce: 06 61 0c 00 7e tst 252\[r0\]\.w, r0 + d3: 06 61 0c 0f 7e tst 252\[r0\]\.w, r15 + d8: 06 a1 0c 00 3f tst 252\[r0\]\.l, r0 + dd: 06 a1 0c 0f 3f tst 252\[r0\]\.l, r15 + e2: fc 31 f0 fc tst 252\[r15\]\.ub, r0 + e6: fc 31 ff fc tst 252\[r15\]\.ub, r15 + ea: 06 21 0c f0 fc tst 252\[r15\]\.b, r0 + ef: 06 21 0c ff fc tst 252\[r15\]\.b, r15 + f4: 06 e1 0c f0 7e tst 252\[r15\]\.uw, r0 + f9: 06 e1 0c ff 7e tst 252\[r15\]\.uw, r15 + fe: 06 61 0c f0 7e tst 252\[r15\]\.w, r0 + 103: 06 61 0c ff 7e tst 252\[r15\]\.w, r15 + 108: 06 a1 0c f0 3f tst 252\[r15\]\.l, r0 + 10d: 06 a1 0c ff 3f tst 252\[r15\]\.l, r15 + 112: fc 32 00 fc ff tst 65532\[r0\]\.ub, r0 + 117: fc 32 0f fc ff tst 65532\[r0\]\.ub, r15 + 11c: 06 22 0c 00 fc ff tst 65532\[r0\]\.b, r0 + 122: 06 22 0c 0f fc ff tst 65532\[r0\]\.b, r15 + 128: 06 e2 0c 00 fe 7f tst 65532\[r0\]\.uw, r0 + 12e: 06 e2 0c 0f fe 7f tst 65532\[r0\]\.uw, r15 + 134: 06 62 0c 00 fe 7f tst 65532\[r0\]\.w, r0 + 13a: 06 62 0c 0f fe 7f tst 65532\[r0\]\.w, r15 + 140: 06 a2 0c 00 ff 3f tst 65532\[r0\]\.l, r0 + 146: 06 a2 0c 0f ff 3f tst 65532\[r0\]\.l, r15 + 14c: fc 32 f0 fc ff tst 65532\[r15\]\.ub, r0 + 151: fc 32 ff fc ff tst 65532\[r15\]\.ub, r15 + 156: 06 22 0c f0 fc ff tst 65532\[r15\]\.b, r0 + 15c: 06 22 0c ff fc ff tst 65532\[r15\]\.b, r15 + 162: 06 e2 0c f0 fe 7f tst 65532\[r15\]\.uw, r0 + 168: 06 e2 0c ff fe 7f tst 65532\[r15\]\.uw, r15 + 16e: 06 62 0c f0 fe 7f tst 65532\[r15\]\.w, r0 + 174: 06 62 0c ff fe 7f tst 65532\[r15\]\.w, r15 + 17a: 06 a2 0c f0 ff 3f tst 65532\[r15\]\.l, r0 + 180: 06 a2 0c ff ff 3f tst 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/tst.sm b/gas/testsuite/gas/rx/tst.sm new file mode 100644 index 00000000000..ab194fdfc1a --- /dev/null +++ b/gas/testsuite/gas/rx/tst.sm @@ -0,0 +1,4 @@ + tst #{imm},{reg} + + tst {reg},{reg} + tst {memx},{reg} diff --git a/gas/testsuite/gas/rx/wait.d b/gas/testsuite/gas/rx/wait.d new file mode 100644 index 00000000000..7dc82542f62 --- /dev/null +++ b/gas/testsuite/gas/rx/wait.d @@ -0,0 +1,9 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 7f 96 wait diff --git a/gas/testsuite/gas/rx/wait.sm b/gas/testsuite/gas/rx/wait.sm new file mode 100644 index 00000000000..4795deebade --- /dev/null +++ b/gas/testsuite/gas/rx/wait.sm @@ -0,0 +1 @@ + wait diff --git a/gas/testsuite/gas/rx/xchg.d b/gas/testsuite/gas/rx/xchg.d new file mode 100644 index 00000000000..5364078d4ad --- /dev/null +++ b/gas/testsuite/gas/rx/xchg.d @@ -0,0 +1,72 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fc 43 00 xchg r0, r0 + 3: fc 43 0f xchg r0, r15 + 6: fc 43 f0 xchg r15, r0 + 9: fc 43 ff xchg r15, r15 + c: fc 40 00 xchg \[r0\]\.ub, r0 + f: fc 40 0f xchg \[r0\]\.ub, r15 + 12: 06 20 10 00 xchg \[r0\]\.b, r0 + 16: 06 20 10 0f xchg \[r0\]\.b, r15 + 1a: 06 e0 10 00 xchg \[r0\]\.uw, r0 + 1e: 06 e0 10 0f xchg \[r0\]\.uw, r15 + 22: 06 60 10 00 xchg \[r0\]\.w, r0 + 26: 06 60 10 0f xchg \[r0\]\.w, r15 + 2a: 06 a0 10 00 xchg \[r0\]\.l, r0 + 2e: 06 a0 10 0f xchg \[r0\]\.l, r15 + 32: fc 40 f0 xchg \[r15\]\.ub, r0 + 35: fc 40 ff xchg \[r15\]\.ub, r15 + 38: 06 20 10 f0 xchg \[r15\]\.b, r0 + 3c: 06 20 10 ff xchg \[r15\]\.b, r15 + 40: 06 e0 10 f0 xchg \[r15\]\.uw, r0 + 44: 06 e0 10 ff xchg \[r15\]\.uw, r15 + 48: 06 60 10 f0 xchg \[r15\]\.w, r0 + 4c: 06 60 10 ff xchg \[r15\]\.w, r15 + 50: 06 a0 10 f0 xchg \[r15\]\.l, r0 + 54: 06 a0 10 ff xchg \[r15\]\.l, r15 + 58: fc 41 00 fc xchg 252\[r0\]\.ub, r0 + 5c: fc 41 0f fc xchg 252\[r0\]\.ub, r15 + 60: 06 21 10 00 fc xchg 252\[r0\]\.b, r0 + 65: 06 21 10 0f fc xchg 252\[r0\]\.b, r15 + 6a: 06 e1 10 00 7e xchg 252\[r0\]\.uw, r0 + 6f: 06 e1 10 0f 7e xchg 252\[r0\]\.uw, r15 + 74: 06 61 10 00 7e xchg 252\[r0\]\.w, r0 + 79: 06 61 10 0f 7e xchg 252\[r0\]\.w, r15 + 7e: 06 a1 10 00 3f xchg 252\[r0\]\.l, r0 + 83: 06 a1 10 0f 3f xchg 252\[r0\]\.l, r15 + 88: fc 41 f0 fc xchg 252\[r15\]\.ub, r0 + 8c: fc 41 ff fc xchg 252\[r15\]\.ub, r15 + 90: 06 21 10 f0 fc xchg 252\[r15\]\.b, r0 + 95: 06 21 10 ff fc xchg 252\[r15\]\.b, r15 + 9a: 06 e1 10 f0 7e xchg 252\[r15\]\.uw, r0 + 9f: 06 e1 10 ff 7e xchg 252\[r15\]\.uw, r15 + a4: 06 61 10 f0 7e xchg 252\[r15\]\.w, r0 + a9: 06 61 10 ff 7e xchg 252\[r15\]\.w, r15 + ae: 06 a1 10 f0 3f xchg 252\[r15\]\.l, r0 + b3: 06 a1 10 ff 3f xchg 252\[r15\]\.l, r15 + b8: fc 42 00 fc ff xchg 65532\[r0\]\.ub, r0 + bd: fc 42 0f fc ff xchg 65532\[r0\]\.ub, r15 + c2: 06 22 10 00 fc ff xchg 65532\[r0\]\.b, r0 + c8: 06 22 10 0f fc ff xchg 65532\[r0\]\.b, r15 + ce: 06 e2 10 00 fe 7f xchg 65532\[r0\]\.uw, r0 + d4: 06 e2 10 0f fe 7f xchg 65532\[r0\]\.uw, r15 + da: 06 62 10 00 fe 7f xchg 65532\[r0\]\.w, r0 + e0: 06 62 10 0f fe 7f xchg 65532\[r0\]\.w, r15 + e6: 06 a2 10 00 ff 3f xchg 65532\[r0\]\.l, r0 + ec: 06 a2 10 0f ff 3f xchg 65532\[r0\]\.l, r15 + f2: fc 42 f0 fc ff xchg 65532\[r15\]\.ub, r0 + f7: fc 42 ff fc ff xchg 65532\[r15\]\.ub, r15 + fc: 06 22 10 f0 fc ff xchg 65532\[r15\]\.b, r0 + 102: 06 22 10 ff fc ff xchg 65532\[r15\]\.b, r15 + 108: 06 e2 10 f0 fe 7f xchg 65532\[r15\]\.uw, r0 + 10e: 06 e2 10 ff fe 7f xchg 65532\[r15\]\.uw, r15 + 114: 06 62 10 f0 fe 7f xchg 65532\[r15\]\.w, r0 + 11a: 06 62 10 ff fe 7f xchg 65532\[r15\]\.w, r15 + 120: 06 a2 10 f0 ff 3f xchg 65532\[r15\]\.l, r0 + 126: 06 a2 10 ff ff 3f xchg 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/xchg.sm b/gas/testsuite/gas/rx/xchg.sm new file mode 100644 index 00000000000..8eb12b2e635 --- /dev/null +++ b/gas/testsuite/gas/rx/xchg.sm @@ -0,0 +1,2 @@ + xchg {reg},{reg} + xchg {memx},{reg} diff --git a/gas/testsuite/gas/rx/xor.d b/gas/testsuite/gas/rx/xor.d new file mode 100644 index 00000000000..fb99bcec371 --- /dev/null +++ b/gas/testsuite/gas/rx/xor.d @@ -0,0 +1,88 @@ +#objdump: -dr + +dump\.o: file format .* + + +Disassembly of section \.text: + +00000000 <\.text>: + 0: fd 74 d0 80 xor #-128, r0 + 4: fd 74 df 80 xor #-128, r15 + 8: fd 74 d0 7f xor #127, r0 + c: fd 74 df 7f xor #127, r15 + 10: fd 78 d0 00 80 xor #0xffff8000, r0 + 15: fd 78 df 00 80 xor #0xffff8000, r15 + 1a: fd 7c d0 00 80 00 xor #0x8000, r0 + 20: fd 7c df 00 80 00 xor #0x8000, r15 + 26: fd 7c d0 00 00 80 xor #0xff800000, r0 + 2c: fd 7c df 00 00 80 xor #0xff800000, r15 + 32: fd 7c d0 ff ff 7f xor #0x7fffff, r0 + 38: fd 7c df ff ff 7f xor #0x7fffff, r15 + 3e: fd 70 d0 00 00 00 80 xor #0x80000000, r0 + 45: fd 70 df 00 00 00 80 xor #0x80000000, r15 + 4c: fd 70 d0 ff ff ff 7f xor #0x7fffffff, r0 + 53: fd 70 df ff ff ff 7f xor #0x7fffffff, r15 + 5a: fc 37 00 xor r0, r0 + 5d: fc 37 0f xor r0, r15 + 60: fc 37 f0 xor r15, r0 + 63: fc 37 ff xor r15, r15 + 66: fc 34 00 xor \[r0\]\.ub, r0 + 69: fc 34 0f xor \[r0\]\.ub, r15 + 6c: 06 20 0d 00 xor \[r0\]\.b, r0 + 70: 06 20 0d 0f xor \[r0\]\.b, r15 + 74: 06 e0 0d 00 xor \[r0\]\.uw, r0 + 78: 06 e0 0d 0f xor \[r0\]\.uw, r15 + 7c: 06 60 0d 00 xor \[r0\]\.w, r0 + 80: 06 60 0d 0f xor \[r0\]\.w, r15 + 84: 06 a0 0d 00 xor \[r0\]\.l, r0 + 88: 06 a0 0d 0f xor \[r0\]\.l, r15 + 8c: fc 34 f0 xor \[r15\]\.ub, r0 + 8f: fc 34 ff xor \[r15\]\.ub, r15 + 92: 06 20 0d f0 xor \[r15\]\.b, r0 + 96: 06 20 0d ff xor \[r15\]\.b, r15 + 9a: 06 e0 0d f0 xor \[r15\]\.uw, r0 + 9e: 06 e0 0d ff xor \[r15\]\.uw, r15 + a2: 06 60 0d f0 xor \[r15\]\.w, r0 + a6: 06 60 0d ff xor \[r15\]\.w, r15 + aa: 06 a0 0d f0 xor \[r15\]\.l, r0 + ae: 06 a0 0d ff xor \[r15\]\.l, r15 + b2: fc 35 00 fc xor 252\[r0\]\.ub, r0 + b6: fc 35 0f fc xor 252\[r0\]\.ub, r15 + ba: 06 21 0d 00 fc xor 252\[r0\]\.b, r0 + bf: 06 21 0d 0f fc xor 252\[r0\]\.b, r15 + c4: 06 e1 0d 00 7e xor 252\[r0\]\.uw, r0 + c9: 06 e1 0d 0f 7e xor 252\[r0\]\.uw, r15 + ce: 06 61 0d 00 7e xor 252\[r0\]\.w, r0 + d3: 06 61 0d 0f 7e xor 252\[r0\]\.w, r15 + d8: 06 a1 0d 00 3f xor 252\[r0\]\.l, r0 + dd: 06 a1 0d 0f 3f xor 252\[r0\]\.l, r15 + e2: fc 35 f0 fc xor 252\[r15\]\.ub, r0 + e6: fc 35 ff fc xor 252\[r15\]\.ub, r15 + ea: 06 21 0d f0 fc xor 252\[r15\]\.b, r0 + ef: 06 21 0d ff fc xor 252\[r15\]\.b, r15 + f4: 06 e1 0d f0 7e xor 252\[r15\]\.uw, r0 + f9: 06 e1 0d ff 7e xor 252\[r15\]\.uw, r15 + fe: 06 61 0d f0 7e xor 252\[r15\]\.w, r0 + 103: 06 61 0d ff 7e xor 252\[r15\]\.w, r15 + 108: 06 a1 0d f0 3f xor 252\[r15\]\.l, r0 + 10d: 06 a1 0d ff 3f xor 252\[r15\]\.l, r15 + 112: fc 36 00 fc ff xor 65532\[r0\]\.ub, r0 + 117: fc 36 0f fc ff xor 65532\[r0\]\.ub, r15 + 11c: 06 22 0d 00 fc ff xor 65532\[r0\]\.b, r0 + 122: 06 22 0d 0f fc ff xor 65532\[r0\]\.b, r15 + 128: 06 e2 0d 00 fe 7f xor 65532\[r0\]\.uw, r0 + 12e: 06 e2 0d 0f fe 7f xor 65532\[r0\]\.uw, r15 + 134: 06 62 0d 00 fe 7f xor 65532\[r0\]\.w, r0 + 13a: 06 62 0d 0f fe 7f xor 65532\[r0\]\.w, r15 + 140: 06 a2 0d 00 ff 3f xor 65532\[r0\]\.l, r0 + 146: 06 a2 0d 0f ff 3f xor 65532\[r0\]\.l, r15 + 14c: fc 36 f0 fc ff xor 65532\[r15\]\.ub, r0 + 151: fc 36 ff fc ff xor 65532\[r15\]\.ub, r15 + 156: 06 22 0d f0 fc ff xor 65532\[r15\]\.b, r0 + 15c: 06 22 0d ff fc ff xor 65532\[r15\]\.b, r15 + 162: 06 e2 0d f0 fe 7f xor 65532\[r15\]\.uw, r0 + 168: 06 e2 0d ff fe 7f xor 65532\[r15\]\.uw, r15 + 16e: 06 62 0d f0 fe 7f xor 65532\[r15\]\.w, r0 + 174: 06 62 0d ff fe 7f xor 65532\[r15\]\.w, r15 + 17a: 06 a2 0d f0 ff 3f xor 65532\[r15\]\.l, r0 + 180: 06 a2 0d ff ff 3f xor 65532\[r15\]\.l, r15 diff --git a/gas/testsuite/gas/rx/xor.sm b/gas/testsuite/gas/rx/xor.sm new file mode 100644 index 00000000000..591d352efa1 --- /dev/null +++ b/gas/testsuite/gas/rx/xor.sm @@ -0,0 +1,4 @@ + xor #{imm},{reg} + + xor {reg},{reg} + xor {memx},{reg} diff --git a/include/ChangeLog b/include/ChangeLog index db95d46314a..7e8f3450551 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * dis-asm.h: Add prototype for print_insn_rx. + 2009-09-25 Dodji Seketeli <dodji@redhat.com> * dwarf2.h (enum dwarf_tag): Rename DW_TAG_template_parameter_pack and diff --git a/include/dis-asm.h b/include/dis-asm.h index 47236a0d0d3..3d126be902c 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -296,6 +296,7 @@ extern int print_insn_xtensa (bfd_vma, disassemble_info *); extern int print_insn_z80 (bfd_vma, disassemble_info *); extern int print_insn_z8001 (bfd_vma, disassemble_info *); extern int print_insn_z8002 (bfd_vma, disassemble_info *); +extern int print_insn_rx (bfd_vma, disassemble_info *); extern disassembler_ftype arc_get_disassembler (void *); extern disassembler_ftype cris_get_disassembler (bfd *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index a33fb843bf2..3841f35a588 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * rx.h: New file. + 2009-09-21 Alan Modra <amodra@bigpond.net.au> * ppc.h (DT_PPC_TLSOPT): Define. diff --git a/include/elf/rx.h b/include/elf/rx.h new file mode 100644 index 00000000000..1e04f3f8c8d --- /dev/null +++ b/include/elf/rx.h @@ -0,0 +1,134 @@ +/* RX ELF support for BFD. + Copyright (C) 2008, 2009 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_RX_H +#define _ELF_RX_H + +#include "elf/reloc-macros.h" + +/* Note that there are a few internal relocation types used by the + linker to do link-time relaxation. If you update this file, please + check elf32-rx.c to see if any of the internal relocations need to + be, er, relocated. */ + +/* Preliminary relocations. */ +START_RELOC_NUMBERS (elf_rx_reloc_type) + + RELOC_NUMBER (R_RX_NONE, 0x00) + /* These are for data, and are bi-endian. */ + RELOC_NUMBER (R_RX_DIR32, 0x01) /* Was: R_RX_32. */ + RELOC_NUMBER (R_RX_DIR24S, 0x02) /* Was: R_RX_24. */ + RELOC_NUMBER (R_RX_DIR16, 0x03) + RELOC_NUMBER (R_RX_DIR16U, 0x04) /* Was: R_RX_16_UNS. */ + RELOC_NUMBER (R_RX_DIR16S, 0x05) /* Was: R_RX_16. */ + RELOC_NUMBER (R_RX_DIR8, 0x06) + RELOC_NUMBER (R_RX_DIR8U, 0x07) /* Was: R_RX_8_UNS. */ + RELOC_NUMBER (R_RX_DIR8S, 0x08) /* Was: R_RX_8. */ + + /* Signed pc-relative values. */ + RELOC_NUMBER (R_RX_DIR24S_PCREL, 0x09) /* Was: R_RX_24_PCREL. */ + RELOC_NUMBER (R_RX_DIR16S_PCREL, 0x0a) /* Was: R_RX_16_PCREL. */ + RELOC_NUMBER (R_RX_DIR8S_PCREL, 0x0b) /* Was: R_RX_8_PCREL. */ + + /* These are for fields in the instructions. */ + RELOC_NUMBER (R_RX_DIR16UL, 0x0c) + RELOC_NUMBER (R_RX_DIR16UW, 0x0d) + RELOC_NUMBER (R_RX_DIR8UL, 0x0e) + RELOC_NUMBER (R_RX_DIR8UW, 0x0f) + RELOC_NUMBER (R_RX_DIR32_REV, 0x10) + RELOC_NUMBER (R_RX_DIR16_REV, 0x11) + RELOC_NUMBER (R_RX_DIR3U_PCREL, 0x12) + + /* These are extensions added by Red Hat. */ + RELOC_NUMBER (R_RX_RH_3_PCREL, 0x20) /* Like R_RX_DIR8S_PCREL but only 3-bits. */ + RELOC_NUMBER (R_RX_RH_16_OP, 0x21) /* Like R_RX_DIR16 but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_24_OP, 0x22) /* Like R_RX_DIR24S but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_32_OP, 0x23) /* Like R_RX_DIR32 but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_24_UNS, 0x24) /* Like R_RX_DIR24S but for unsigned values. */ + RELOC_NUMBER (R_RX_RH_8_NEG, 0x25) /* Like R_RX_DIR8 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_16_NEG, 0x26) /* Like R_RX_DIR16 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_24_NEG, 0x27) /* Like R_RX_DIR24S but -x is stored. */ + RELOC_NUMBER (R_RX_RH_32_NEG, 0x28) /* Like R_RX_DIR32 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_DIFF, 0x29) /* Subtract from a previous relocation. */ + RELOC_NUMBER (R_RX_RH_GPRELB, 0x2a) /* Byte value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_GPRELW, 0x2b) /* Word value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_GPRELL, 0x2c) /* Long value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_RELAX, 0x2d) /* Marks opcodes suitable for linker relaxation. */ + + /* These are for complex relocs. */ + RELOC_NUMBER (R_RX_ABS32, 0x41) + RELOC_NUMBER (R_RX_ABS24S, 0x42) + RELOC_NUMBER (R_RX_ABS16, 0x43) + RELOC_NUMBER (R_RX_ABS16U, 0x44) + RELOC_NUMBER (R_RX_ABS16S, 0x45) + RELOC_NUMBER (R_RX_ABS8, 0x46) + RELOC_NUMBER (R_RX_ABS8U, 0x47) + RELOC_NUMBER (R_RX_ABS8S, 0x48) + RELOC_NUMBER (R_RX_ABS24S_PCREL, 0x49) + RELOC_NUMBER (R_RX_ABS16S_PCREL, 0x4a) + RELOC_NUMBER (R_RX_ABS8S_PCREL, 0x4b) + RELOC_NUMBER (R_RX_ABS16UL, 0x4c) + RELOC_NUMBER (R_RX_ABS16UW, 0x4d) + RELOC_NUMBER (R_RX_ABS8UL, 0x4e) + RELOC_NUMBER (R_RX_ABS8UW, 0x4f) + RELOC_NUMBER (R_RX_ABS32_REV, 0x50) + RELOC_NUMBER (R_RX_ABS16_REV, 0x51) + + RELOC_NUMBER (R_RX_SYM, 0x80) + RELOC_NUMBER (R_RX_OPneg, 0x81) + RELOC_NUMBER (R_RX_OPadd, 0x82) + RELOC_NUMBER (R_RX_OPsub, 0x83) + RELOC_NUMBER (R_RX_OPmul, 0x84) + RELOC_NUMBER (R_RX_OPdiv, 0x85) + RELOC_NUMBER (R_RX_OPshla, 0x86) + RELOC_NUMBER (R_RX_OPshra, 0x87) + RELOC_NUMBER (R_RX_OPsctsize, 0x88) + RELOC_NUMBER (R_RX_OPscttop, 0x8d) + RELOC_NUMBER (R_RX_OPand, 0x90) + RELOC_NUMBER (R_RX_OPor, 0x91) + RELOC_NUMBER (R_RX_OPxor, 0x92) + RELOC_NUMBER (R_RX_OPnot, 0x93) + RELOC_NUMBER (R_RX_OPmod, 0x94) + RELOC_NUMBER (R_RX_OPromtop, 0x95) + RELOC_NUMBER (R_RX_OPramtop, 0x96) + +END_RELOC_NUMBERS (R_RX_max) + +#define EF_RX_CPU_RX 0x00000079 /* FIXME: correct value? */ +#define EF_RX_CPU_MASK 0x0000007F /* specific cpu bits. */ +#define EF_RX_ALL_FLAGS (EF_RX_CPU_MASK) + +/* Values for the e_flags field in the ELF header. */ +#define E_FLAG_RX_64BIT_DOUBLES (1 << 0) +#define E_FLAG_RX_DSP (1 << 1) /* Defined in the RX CPU Object file specification, but not explained. */ + +/* These define the addend field of R_RX_RH_RELAX relocations. */ +#define RX_RELAXA_IMM6 0x00000010 /* Imm8/16/24/32 at bit offset 6. */ +#define RX_RELAXA_IMM12 0x00000020 /* Imm8/16/24/32 at bit offset 12. */ +#define RX_RELAXA_DSP4 0x00000040 /* Dsp0/8/16 at bit offset 4. */ +#define RX_RELAXA_DSP6 0x00000080 /* Dsp0/8/16 at bit offset 6. */ +#define RX_RELAXA_DSP14 0x00000100 /* Dsp0/8/16 at bit offset 14. */ +#define RX_RELAXA_BRA 0x00000200 /* Any type of branch (must be decoded). */ +#define RX_RELAXA_RNUM 0x0000000f /* Number of associated relocations. */ +/* These mark the place where alignment is requested, and the place where the filler bytes end. */ +#define RX_RELAXA_ALIGN 0x10000000 /* Start alignment; the remaining bits are the alignment value. */ +#define RX_RELAXA_ELIGN 0x20000000 /* End alignment; the remaining bits are the alignment value. */ +#define RX_RELAXA_ANUM 0x00ffffff /* Alignment amount, in bytes (i.e. .balign). */ + +#endif /* _ELF_RX_H */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 29f717bc40d..2fddcdfd449 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * rx.h: New file. + 2009-09-22 Peter Bergner <bergner@vnet.ibm.com> * ppc.h (ppc_cpu_t): Typedef to uint64_t. diff --git a/include/opcode/rx.h b/include/opcode/rx.h new file mode 100644 index 00000000000..7081ccce53e --- /dev/null +++ b/include/opcode/rx.h @@ -0,0 +1,218 @@ +/* Opcode decoder for the Renesas RX + Copyright 2008, 2009 + Free Software Foundation, Inc. + Written by DJ Delorie <dj@redhat.com> + + This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* The RX decoder in libopcodes is used by the simulator, gdb's + analyzer, and the disassembler. Given an opcode data source, + it decodes the next opcode into the following structures. */ + +typedef enum +{ + RX_AnySize = 0, + RX_Byte, /* undefined extension */ + RX_UByte, + RX_SByte, + RX_Word, /* undefined extension */ + RX_UWord, + RX_SWord, + RX_3Byte, + RX_Long, +} RX_Size; + +typedef enum +{ + RX_Operand_None, + RX_Operand_Immediate, /* #addend */ + RX_Operand_Register, /* Rn */ + RX_Operand_Indirect, /* [Rn + addend] */ + RX_Operand_Postinc, /* [Rn+] */ + RX_Operand_Predec, /* [-Rn] */ + RX_Operand_Condition, /* eq, gtu, etc */ + RX_Operand_Flag, /* [UIOSZC] */ +} RX_Operand_Type; + +typedef enum +{ + RXO_unknown, + RXO_mov, /* d = s (signed) */ + RXO_movbi, /* d = [s,s2] (signed) */ + RXO_movbir, /* [s,s2] = d (signed) */ + RXO_pushm, /* s..s2 */ + RXO_popm, /* s..s2 */ + RXO_pusha, /* &s */ + RXO_xchg, /* s <-> d */ + RXO_stcc, /* d = s if cond(s2) */ + RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */ + + /* These are all either d OP= s or, if s2 is set, d = s OP s2. Note + that d may be "None". */ + RXO_and, + RXO_or, + RXO_xor, + RXO_add, + RXO_sub, + RXO_mul, + RXO_div, + RXO_divu, + RXO_shll, + RXO_shar, + RXO_shlr, + + RXO_adc, /* d = d + s + carry */ + RXO_sbb, /* d = d - s - ~carry */ + RXO_abs, /* d = |s| */ + RXO_max, /* d = max(d,s) */ + RXO_min, /* d = min(d,s) */ + RXO_emul, /* d:64 = d:32 * s */ + RXO_emulu, /* d:64 = d:32 * s (unsigned) */ + RXO_ediv, /* d:64 / s; d = quot, d+1 = rem */ + RXO_edivu, /* d:64 / s; d = quot, d+1 = rem */ + + RXO_rolc, /* d <<= 1 through carry */ + RXO_rorc, /* d >>= 1 through carry*/ + RXO_rotl, /* d <<= #s without carry */ + RXO_rotr, /* d >>= #s without carry*/ + RXO_revw, /* d = revw(s) */ + RXO_revl, /* d = revl(s) */ + RXO_branch, /* pc = d if cond(s) */ + RXO_branchrel,/* pc += d if cond(s) */ + RXO_jsr, /* pc = d */ + RXO_jsrrel, /* pc += d */ + RXO_rts, + RXO_nop, + + RXO_scmpu, + RXO_smovu, + RXO_smovb, + RXO_suntil, + RXO_swhile, + RXO_smovf, + RXO_sstr, + + RXO_rmpa, + RXO_mulhi, + RXO_mullo, + RXO_machi, + RXO_maclo, + RXO_mvtachi, + RXO_mvtaclo, + RXO_mvfachi, + RXO_mvfacmi, + RXO_mvfaclo, + RXO_racw, + + RXO_sat, /* sat(d) */ + RXO_satr, + + RXO_fadd, /* d op= s */ + RXO_fcmp, + RXO_fsub, + RXO_ftoi, + RXO_fmul, + RXO_fdiv, + RXO_round, + RXO_itof, + + RXO_bset, /* d |= (1<<s) */ + RXO_bclr, /* d &= ~(1<<s) */ + RXO_btst, /* s & (1<<s2) */ + RXO_bnot, /* d ^= (1<<s) */ + RXO_bmcc, /* d<s> = cond(s2) */ + + RXO_clrpsw, /* flag index in d */ + RXO_setpsw, /* flag index in d */ + + RXO_mvtcp, /* cop# in s2, cop[d] = s */ + RXO_mvfcp, /* cop# in s2, d = cop[s] */ + RXO_opecp, /* cop# in s2, do cop[s] */ + + RXO_rtfi, + RXO_rte, + RXO_rtd, /* undocumented */ + RXO_brk, + RXO_dbt, /* undocumented */ + RXO_int, /* vector id in s */ + RXO_stop, + RXO_wait, + + RXO_sccnd, /* d = cond(s) ? 1 : 0 */ +} RX_Opcode_ID; + +/* Condition bitpatterns, as registers. */ +#define RXC_eq 0 +#define RXC_z 0 +#define RXC_ne 1 +#define RXC_nz 1 +#define RXC_c 2 +#define RXC_nc 3 +#define RXC_gtu 4 +#define RXC_leu 5 +#define RXC_pz 6 +#define RXC_n 7 +#define RXC_ge 8 +#define RXC_lt 9 +#define RXC_gt 10 +#define RXC_le 11 +#define RXC_o 12 +#define RXC_no 13 +#define RXC_always 14 +#define RXC_never 15 + +typedef struct +{ + RX_Operand_Type type; + int reg; + int addend; + RX_Size size; +} RX_Opcode_Operand; + +typedef struct +{ + RX_Opcode_ID id; + int n_bytes; + int prefix; + char * syntax; + RX_Size size; + /* By convention, these are destination, source1, source2. */ + RX_Opcode_Operand op[3]; + + /* The logic here is: + newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s) + Only the O, S, Z, and C flags are affected. */ + char flags_0; /* This also clears out flags-to-be-set. */ + char flags_1; + char flags_s; +} RX_Opcode_Decoded; + +/* Within the syntax, %c-style format specifiers are as follows: + + %% = '%' character + %0 = operand[0] (destination) + %1 = operand[1] (source) + %2 = operand[2] (2nd source) + %s = operation size (b/w/l) + %SN = operand size [N] (N=0,1,2) + %aN = op[N] as an address (N=0,1,2) + + Register numbers 0..15 are general registers. 16..31 are control + registers. 32..47 are condition codes. */ + +int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *); diff --git a/ld/ChangeLog b/ld/ChangeLog index 6658a7d70c5..a35039be94b 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,12 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * Makefile.am: Add rules to build RX emulation. + * configure.tgt: Likewise. + * NEWS: Mention support for RX architecture. + * Makefile.in: Regenerate. + * emulparams/elf32rx.sh: New file. + * emultempl/rxelf.em: New file. + 2009-09-29 Alan Modra <amodra@bigpond.net.au> * ldlang.c (lang_size_sections_1): Allow scripts to specify a diff --git a/ld/Makefile.am b/ld/Makefile.am index 7c4444b615d..5feebf3b199 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -209,6 +209,7 @@ ALL_EMULATIONS = \ eelf32ppcsim.o \ eelf32ppcwindiss.o \ eelf32ppcvxworks.o \ + eelf32rx.o \ eelf32vax.o \ eelf32xc16x.o \ eelf32xc16xl.o \ @@ -787,6 +788,10 @@ eelf32xstormy16.c: $(srcdir)/emulparams/elf32xstormy16.sh \ eelf32am33lin.c: $(srcdir)/emulparams/elf32am33lin.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32am33lin "$(tdir_mn10300)" +eelf32rx.c: $(srcdir)/emulparams/elf32rx.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32rx "$(tdir_elf32rx)" + @true end-sanitize-rx eelf32vax.c: $(srcdir)/emulparams/elf32vax.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32vax "$(tdir_elf32vax)" diff --git a/ld/Makefile.in b/ld/Makefile.in index 8aabafb3a5b..cba31ee7db7 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -495,6 +495,7 @@ ALL_EMULATIONS = \ eelf32ppcsim.o \ eelf32ppcwindiss.o \ eelf32ppcvxworks.o \ + eelf32rx.o \ eelf32vax.o \ eelf32xc16x.o \ eelf32xc16xl.o \ @@ -1007,6 +1008,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppcsim.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppcvxworks.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppcwindiss.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xl.Po@am__quote@ @@ -2128,6 +2130,10 @@ eelf32xstormy16.c: $(srcdir)/emulparams/elf32xstormy16.sh \ eelf32am33lin.c: $(srcdir)/emulparams/elf32am33lin.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32am33lin "$(tdir_mn10300)" +eelf32rx.c: $(srcdir)/emulparams/elf32rx.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32rx "$(tdir_elf32rx)" + @true end-sanitize-rx eelf32vax.c: $(srcdir)/emulparams/elf32vax.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32vax "$(tdir_elf32vax)" @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the Renesas RX processor. + Changes in 2.20: * GNU/Linux targets now support the STB_GNU_UNIQUE symbol binding. This is a diff --git a/ld/configure.tgt b/ld/configure.tgt index d6d86ab95c4..5cced83b4e3 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -503,6 +503,7 @@ powerpc-*-lynxos*) targ_emul=ppclynx ;; rs6000-*-aix[5-9]*) targ_emul=aix5rs6 ;; rs6000-*-aix*) targ_emul=aixrs6 ;; +rx-*-*) targ_emul=elf32rx ;; s390x-*-linux*) targ_emul=elf64_s390 targ_extra_emuls=elf_s390 targ_extra_libpath=$targ_extra_emuls diff --git a/ld/emulparams/elf32rx.sh b/ld/emulparams/elf32rx.sh new file mode 100644 index 00000000000..729b4b36697 --- /dev/null +++ b/ld/emulparams/elf32rx.sh @@ -0,0 +1,32 @@ +MACHINE= +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-rx-le" +# See also `include/elf/rx.h' +TEXT_START_ADDR=0x10000000 +ARCH=rx +ENTRY=_start +EMBEDDED=yes +TEMPLATE_NAME=elf32 +EXTRA_EM_FILE=rxelf +# EXTRA_EM_FILE=needrelax +ELFSIZE=32 +MAXPAGESIZE=256 +# This is like setting STACK_ADDR to 0xbffffffc, except that the setting can +# be overridden, e.g. --defsym _stack=0x0f00, and that we put an extra +# sentinal value at the bottom. +# N.B. We can't use PROVIDE to set the default value in a symbol because +# the address is needed to place the .stack section, which in turn is needed +# to hold the sentinel value(s). +test -z "$CREATE_SHLIB" && OTHER_SECTIONS=" .stack ${RELOCATING-0}${RELOCATING+(DEFINED(__stack) ? __stack : 0xbffffffc)} : + { + ${RELOCATING+__stack = .;} + *(.stack) + LONG(0xdeaddead) + }" +# We do not need .stack for shared library. +test -n "$CREATE_SHLIB" && OTHER_SECTIONS="" + +OTHER_TEXT_SECTIONS='*(P)' +OTHER_READONLY_SECTIONS='C_1 : { *(C_1) } C_2 : { *(C_2) } C : { *(C) }' +OTHER_READWRITE_SECTIONS='D_1 : { *(D_1) } D_2 : { *(D_2) } D : { *(D) }' +OTHER_BSS_SECTIONS='B_1 : { *(B_1) } B_2 : { *(B_2) } B : { *(B) }' diff --git a/ld/emultempl/rxelf.em b/ld/emultempl/rxelf.em new file mode 100644 index 00000000000..c4a2dacc3a8 --- /dev/null +++ b/ld/emultempl/rxelf.em @@ -0,0 +1,64 @@ +# This shell script emits a C file. -*- C -*- +# Copyright 2009 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +# This file is sourced from elf32.em, and defines extra rx-elf +# specific routines. +# +test -z "$TARGET2_TYPE" && TARGET2_TYPE="rel" +fragment <<EOF + +static bfd_boolean no_flag_mismatch_warnings = FALSE; + +/* This is a convenient point to tell BFD about target specific flags. + After the output has been created, but before inputs are read. */ +static void +rx_elf_create_output_section_statements (void) +{ + extern void bfd_elf32_rx_set_target_flags (bfd_boolean); + + bfd_elf32_rx_set_target_flags (no_flag_mismatch_warnings); +} + +EOF + +# Define some shell vars to insert bits of code into the standard elf +# parse_args and list_options functions. +# +PARSE_AND_LIST_PROLOGUE=' +#define OPTION_NO_FLAG_MISMATCH_WARNINGS 301 +' + +PARSE_AND_LIST_LONGOPTS=' + { "no-flag-mismatch-warnings", no_argument, NULL, OPTION_NO_FLAG_MISMATCH_WARNINGS}, +' + +PARSE_AND_LIST_OPTIONS=' + fprintf (file, _(" --no-flag-mismatch-warnings Don'\''t warn about objects with incompatible" + " endian or dsp settings\n")); +' + +PARSE_AND_LIST_ARGS_CASES=' + case OPTION_NO_FLAG_MISMATCH_WARNINGS: + no_flag_mismatch_warnings = TRUE; + break; +' + +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=rx_elf_create_output_section_statements diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5f26e01381e..a3363d8caeb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2009-09-29 DJ Delorie <dj@redhat.com> + + * Makefile.am: Add RX files. + * configure.in: Add support for RX target. + * disassemble.c: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * opc2c.c: New file. + * rx-decode.c: New file. + * rx-decode.opc: New file. + * rx-dis.c: New file. + 2009-09-29 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (powerpc_opcodes): Remove support for the the "lxsdux", diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 43db72a085a..735a7ab884d 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -188,6 +188,8 @@ TARGET_LIBOPCODES_CFILES = \ pj-opc.c \ ppc-dis.c \ ppc-opc.c \ + rx-decode.c \ + rx-dis.c \ s390-dis.c \ s390-opc.c \ score-dis.c \ @@ -435,6 +437,14 @@ stamp-iq2000: $(CGENDEPS) $(srcdir)/../cpu/iq2000.cpu \ archfile=$(srcdir)/../cpu/iq2000.cpu \ opcfile=$(srcdir)/../cpu/iq2000.opc extrafiles= +$(srcdir)/rx-decode.c : $(srcdir)/rx-decode.opc opc2c$(EXEEXT) + ./opc2c$(EXEEXT) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c + +rx-dis.lo : rx-dis.c sysdep.h config.h $(BFD_H) $(INCDIR)/opcode/rx.h + +opc2c$(EXEEXT) : $(srcdir)/opc2c.c + gcc $(srcdir)/opc2c.c -o opc2c$(EXEEXT) + $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 5b4721af85f..07c9495fa95 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -458,6 +458,8 @@ TARGET_LIBOPCODES_CFILES = \ pj-opc.c \ ppc-dis.c \ ppc-opc.c \ + rx-decode.c \ + rx-dis.c \ s390-dis.c \ s390-opc.c \ score-dis.c \ @@ -824,6 +826,8 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pj-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ppc-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ppc-opc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rx-decode.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rx-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/s390-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/s390-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/score-dis.Plo@am__quote@ @@ -1280,6 +1284,14 @@ stamp-iq2000: $(CGENDEPS) $(srcdir)/../cpu/iq2000.cpu \ archfile=$(srcdir)/../cpu/iq2000.cpu \ opcfile=$(srcdir)/../cpu/iq2000.opc extrafiles= +$(srcdir)/rx-decode.c : $(srcdir)/rx-decode.opc opc2c$(EXEEXT) + ./opc2c$(EXEEXT) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c + +rx-dis.lo : rx-dis.c sysdep.h config.h $(BFD_H) $(INCDIR)/opcode/rx.h + +opc2c$(EXEEXT) : $(srcdir)/opc2c.c + gcc $(srcdir)/opc2c.c -o opc2c$(EXEEXT) + $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc diff --git a/opcodes/configure b/opcodes/configure index 52da1c49436..83b973cf646 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12332,6 +12332,7 @@ if test x${all_targets} = xfalse ; then bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;; bfd_sh_arch) diff --git a/opcodes/configure.in b/opcodes/configure.in index 75414d799a6..dd9dabf100a 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -271,6 +271,7 @@ if test x${all_targets} = xfalse ; then bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;; bfd_sh_arch) diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 04d5d0c71f7..267fcf5b3c3 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -71,6 +71,7 @@ #define ARCH_pj #define ARCH_powerpc #define ARCH_rs6000 +#define ARCH_rx #define ARCH_s390 #define ARCH_score #define ARCH_sh @@ -352,6 +353,11 @@ disassembler (abfd) disassemble = print_insn_rs6000; break; #endif +#ifdef ARCH_rx + case bfd_arch_rx: + disassemble = print_insn_rx; + break; +#endif #ifdef ARCH_s390 case bfd_arch_s390: disassemble = print_insn_s390; diff --git a/opcodes/opc2c.c b/opcodes/opc2c.c new file mode 100644 index 00000000000..bec361f32cb --- /dev/null +++ b/opcodes/opc2c.c @@ -0,0 +1,810 @@ +/* opc2c.c --- generate C opcode decoder code from from .opc file + + Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc. + Contributed by Red Hat, Inc. + + This file is part of the GNU opcode library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + + +#include <stdio.h> +#include <string.h> +#include <ctype.h> +#include <stdlib.h> + +static char * line_buf = NULL; +static int line_buf_size = 0; + +#define LBUFINCR 100 + +char * +safe_fgets (FILE * f) +{ + char * line_ptr; + + if (line_buf == NULL) + { + line_buf = (char *) malloc (LBUFINCR); + line_buf_size = LBUFINCR; + } + + /* Points to last byte. */ + line_ptr = line_buf + line_buf_size - 1; + + /* So we can see if fgets put a 0 there. */ + *line_ptr = 1; + if (fgets (line_buf, line_buf_size, f) == 0) + return NULL; + + /* We filled the buffer? */ + while (line_ptr[0] == 0 && line_ptr[-1] != '\n') + { + /* Make the buffer bigger and read more of the line. */ + line_buf_size += LBUFINCR; + line_buf = (char *) realloc (line_buf, line_buf_size); + + /* Points to last byte again. */ + line_ptr = line_buf + line_buf_size - 1; + /* So we can see if fgets put a 0 there. */ + *line_ptr = 1; + + if (fgets (line_buf + line_buf_size - LBUFINCR - 1, LBUFINCR + 1, f) == 0) + return NULL; + } + + return line_buf; +} + + +static int errors = 0; + +#define MAX_BYTES 10 + +typedef struct +{ + int varyno:16; + int byte:8; + int shift:8; +} VaryRef; + +typedef struct +{ + char nbytes; + char dbytes; + char id[MAX_BYTES * 8 + 1]; + unsigned char var_start[MAX_BYTES * 8 + 1]; + struct + { + unsigned char decodable_mask; + unsigned char decodable_bits; + } b[MAX_BYTES]; + char * comment; + char * syntax; + int lineno; + int nlines; + char ** lines; + struct Indirect * last_ind; + int semantics_label; + int nvaries; + VaryRef * vary; +} opcode; + +int n_opcodes; +opcode ** opcodes; +opcode * op; + +typedef struct +{ + char * name; + int nlen; + unsigned char mask; + int n_patterns; + unsigned char * patterns; +} Vary; + +Vary ** vary = 0; +int n_varies = 0; + +unsigned char cur_bits[MAX_BYTES + 1]; + +char * orig_filename; + +FILE * sim_log = NULL; +#define lprintf if (sim_log) fprintf + +opcode prefix_text, suffix_text; + +typedef enum +{ + T_unused, + T_op, + T_indirect, + T_done +} OpType; + +typedef struct Indirect +{ + OpType type; + union + { + struct Indirect * ind; + opcode * op; + } u; +} Indirect; + +Indirect indirect[256]; + +static int +next_varybits (int bits, opcode * op, int byte) +{ + int mask = op->b[byte].decodable_mask; + int i; + + for (i = 0; i < 8; i++) + if (!(mask & (1 << i))) + { + if (bits & (1 << i)) + { + bits &= ~(1 << i); + } + else + { + bits |= (1 << i); + return bits; + } + } + return 0; +} + +static int +valid_varybits (int bits, opcode * op, int byte) +{ + if (op->nvaries) + { + int vn; + + for (vn = 0; vn < op->nvaries; vn++) + { + Vary * v; + int found = 0; + int i; + int ob; + + if (byte != op->vary[vn].byte) + continue; + v = vary[op->vary[vn].varyno]; + ob = (bits >> op->vary[vn].shift) & v->mask; + lprintf (sim_log, "varybits: vary %s ob %x\n", v->name, ob); + + for (i = 0; i < v->n_patterns; i++) + if (ob == v->patterns[i]) + { + lprintf (sim_log, " found at %d\n", i); + found = 1; + break; + } + if (!found) + return 0; + } + } + return 1; +} + +char * +prmb (int mask, int bits) +{ + static char buf[8][30]; + static int bn = 0; + char * bp; + + bn = (bn + 1) % 8; + bp = buf[bn]; + int i; + for (i = 0; i < 8; i++) + { + int bit = 0x80 >> i; + + if (!(mask & bit)) + *bp++ = '-'; + else if (bits & bit) + *bp++ = '1'; + else + *bp++ = '0'; + if (i % 4 == 3) + *bp++ = ' '; + } + *--bp = 0; + return buf[bn]; +} + +static int +op_cmp (const void *va, const void *vb) +{ + const opcode * a = *(const opcode **) va; + const opcode * b = *(const opcode **) vb; + + if (a->nbytes != b->nbytes) + return a->nbytes - b->nbytes; + + return strcmp (a->id, b->id); +} + +void +dump_lines (opcode * op, int level, Indirect * ind) +{ + char * varnames[40]; + int i, vn = 0; + + if (op->semantics_label) + { + printf ("%*sgoto op_semantics_%d;\n", level, "", op->semantics_label); + return; + } + + if (ind != op->last_ind) + { + static int labelno = 0; + labelno++; + printf ("%*sop_semantics_%d:\n", level, "", labelno); + op->semantics_label = labelno; + } + + if (op->comment) + { + level += 2; + printf ("%*s{\n", level, ""); + printf ("%*s %s\n", level, "", op->comment); + } + + for (i = 0; i < op->nbytes * 8;) + { + if (isalpha (op->id[i])) + { + int byte = i >> 3; + int mask = 0; + int shift = 0; + char name[33]; + char * np = name; + + while (op->id[i] && isalpha (op->id[i])) + { + mask = (mask << 1) | 1; + shift = 7 - (i & 7); + *np++ = op->id[i++]; + if (op->var_start[i]) + break; + } + *np = 0; + varnames[vn++] = strdup (name); + printf ("#line %d \"%s\"\n", op->lineno, orig_filename); + if (mask & ~0xff) + { + fprintf (stderr, "Error: variable %s spans bytes: %s\n", + name, op->comment); + errors++; + } + else if (shift && (mask != 0xff)) + printf ("%*s int %s AU = (op[%d] >> %d) & 0x%02x;\n", + level, "", name, byte, shift, mask); + else if (mask != 0xff) + printf ("%*s int %s AU = op[%d] & 0x%02x;\n", + level, "", name, byte, mask); + else + printf ("%*s int %s AU = op[%d];\n", level, "", name, byte); + } + else + i++; + } + + if (op->comment) + { + printf ("%*s if (trace)\n", level, ""); + printf ("%*s {\n", level, ""); + printf ("%*s printf (\"\\033[33m%%s\\033[0m ", level, ""); + for (i = 0; i < op->nbytes; i++) + printf (" %%02x"); + printf ("\\n\""); + printf (",\n%*s \"%s\"", level, "", op->comment); + for (i = 0; i < op->nbytes; i++) + { + if (i == 0) + printf (",\n%*s op[%d]", level, "", i); + else + printf (", op[%d]", i); + } + printf (");\n"); + for (i = 0; i < vn; i++) + printf ("%*s printf (\" %s = 0x%%x%s\", %s);\n", level, "", + varnames[i], (i < vn - 1) ? "," : "\\n", varnames[i]); + printf ("%*s }\n", level, ""); + } + + if (op->syntax) + printf ("%*s SYNTAX(\"%s\");\n", level, "", op->syntax); + + printf ("#line %d \"%s\"\n", op->lineno + 1, orig_filename); + + for (i = 0; i < op->nlines; i++) + printf ("%*s%s", level, "", op->lines[i]); + + if (op->comment) + printf ("%*s}\n", level, ""); +} + +void +store_opcode_bits (opcode * op, int byte, Indirect * ind) +{ + int bits = op->b[byte].decodable_bits; + + do + { + if (!valid_varybits (bits, op, byte)) + continue; + + switch (ind[bits].type) + { + case T_unused: + if (byte == op->dbytes - 1) + { + ind[bits].type = T_op; + ind[bits].u.op = op; + op->last_ind = ind; + break; + } + else + { + int i2; + + ind[bits].type = T_indirect; + ind[bits].u.ind = (Indirect *) malloc (256 * sizeof (Indirect)); + for (i2 = 0; i2 < 256; i2++) + ind[bits].u.ind[i2].type = T_unused; + store_opcode_bits (op, byte + 1, ind[bits].u.ind); + } + break; + + case T_indirect: + if (byte < op->dbytes - 1) + store_opcode_bits (op, byte + 1, ind[bits].u.ind); + break; + + case T_op: + break; + + case T_done: + break; + } + } + while ((bits = next_varybits (bits, op, byte)) != 0); +} + +void +emit_indirect (Indirect * ind, int byte) +{ + int unsup = 0; + int j, n, mask; + + mask = 0; + for (j = 0; j < 256; j++) + { + switch (ind[j].type) + { + case T_indirect: + mask = 0xff; + break; + case T_op: + mask |= ind[j].u.op->b[byte].decodable_mask; + break; + case T_done: + case T_unused: + break; + } + } + + printf ("%*s GETBYTE ();\n", byte * 6, ""); + printf ("%*s switch (op[%d] & 0x%02x)\n", byte * 6, "", byte, mask); + printf ("%*s {\n", byte * 6, ""); + + for (j = 0; j < 256; j++) + if ((j & ~mask) == 0) + { + switch (ind[j].type) + { + case T_done: + break; + case T_unused: + unsup = 1; + break; + case T_op: + for (n = j; n < 256; n++) + if ((n & ~mask) == 0 + && ind[n].type == T_op && ind[n].u.op == ind[j].u.op) + { + ind[n].type = T_done; + printf ("%*s case 0x%02x:\n", byte * 6, "", n); + } + for (n = byte; n < ind[j].u.op->nbytes - 1; n++) + printf ("%*s GETBYTE();\n", byte * 6, ""); + dump_lines (ind[j].u.op, byte * 6 + 6, ind); + printf ("%*s break;\n", byte * 6, ""); + break; + case T_indirect: + printf ("%*s case 0x%02x:\n", byte * 6, "", j); + emit_indirect (ind[j].u.ind, byte + 1); + printf ("%*s break;\n", byte * 6, ""); + break; + } + } + if (unsup) + printf ("%*s default: UNSUPPORTED(); break;\n", byte * 6, ""); + printf ("%*s }\n", byte * 6, ""); +} + +static char * +pv_dup (char * p, char * ep) +{ + int n = ep - p; + char *rv = (char *) malloc (n + 1); + + memcpy (rv, p, n); + rv[n] = 0; + return rv; +} + +static unsigned char +str2mask (char * str, char * ep) +{ + unsigned char rv = 0; + + while (str < ep) + { + rv *= 2; + if (*str == '1') + rv += 1; + str++; + } + return rv; +} + +static void +process_vary (char * line) +{ + char * cp; + char * ep; + Vary * v = (Vary *) malloc (sizeof (Vary)); + + n_varies++; + if (vary) + vary = (Vary **) realloc (vary, n_varies * sizeof (Vary *)); + else + vary = (Vary **) malloc (n_varies * sizeof (Vary *)); + vary[n_varies - 1] = v; + + cp = line; + + for (cp = line; isspace (*cp); cp++); + for (ep = cp; *ep && !isspace (*ep); ep++); + + v->name = pv_dup (cp, ep); + v->nlen = strlen (v->name); + v->mask = (1 << v->nlen) - 1; + + v->n_patterns = 0; + v->patterns = (unsigned char *) malloc (1); + while (1) + { + for (cp = ep; isspace (*cp); cp++); + if (!isdigit (*cp)) + break; + for (ep = cp; *ep && !isspace (*ep); ep++); + v->n_patterns++; + v->patterns = (unsigned char *) realloc (v->patterns, v->n_patterns); + v->patterns[v->n_patterns - 1] = str2mask (cp, ep); + } +} + +static int +fieldcmp (opcode * op, int bit, char *name) +{ + int n = strlen (name); + + if (memcmp (op->id + bit, name, n) == 0 + && (!isalpha (op->id[bit + n]) || op->var_start[bit + n])) + return 1; + return 0; +} + +static void +log_indirect (Indirect * ind, int byte) +{ + int i, j; + char * last_c = 0; + + for (i = 0; i < 256; i++) + { + + for (j = 0; j < byte; j++) + fprintf (sim_log, "%s ", prmb (255, cur_bits[j])); + fprintf (sim_log, "%s ", prmb (255, i)); + + switch (ind[i].type) + { + case T_op: + case T_done: + if (last_c && (ind[i].u.op->comment == last_c)) + fprintf (sim_log, "''\n"); + else + fprintf (sim_log, "%s\n", ind[i].u.op->comment); + last_c = ind[i].u.op->comment; + break; + case T_unused: + fprintf (sim_log, "unused\n"); + break; + case T_indirect: + fprintf (sim_log, "indirect\n"); + cur_bits[byte] = i; + log_indirect (ind[i].u.ind, byte + 1); + last_c = 0; + break; + } + } +} + +int +main (int argc, char ** argv) +{ + char * line; + FILE * in; + int lineno = 0; + int i; + VaryRef * vlist; + int skipping_section = 0; + + if (argc > 2 && strcmp (argv[1], "-l") == 0) + { + sim_log = fopen (argv[2], "w"); + fprintf (stderr, "sim_log: %s\n", argv[2]); + argc -= 2; + argv += 2; + } + + if (argc < 2) + { + fprintf (stderr, "usage: opc2c infile.opc > outfile.opc\n"); + exit (1); + } + + orig_filename = argv[1]; + in = fopen (argv[1], "r"); + if (!in) + { + fprintf (stderr, "Unable to open file %s for reading\n", argv[1]); + perror ("The error was"); + exit (1); + } + + n_opcodes = 0; + opcodes = (opcode **) malloc (sizeof (opcode *)); + op = &prefix_text; + op->lineno = 1; + while ((line = safe_fgets (in)) != 0) + { + lineno++; + if (strncmp (line, "/*?* ", 5) == 0) + { + skipping_section = 1; + continue; + } + if (strncmp (line, " /** ", 6) == 0 + && (isdigit (line[6]) || memcmp (line + 6, "VARY", 4) == 0)) + line += 2; + if (line[0] == '/' && line[1] == '*' && line[2] == '*') + { + skipping_section = 0; + if (strncmp (line, "/** */", 6) == 0) + { + op = &suffix_text; + op->lineno = lineno; + } + else if (strncmp (line, "/** VARY ", 9) == 0) + process_vary (line + 9); + else + { + char * lp; + int i, bit, byte; + int var_start = 1; + + n_opcodes++; + opcodes = + (opcode **) realloc (opcodes, n_opcodes * sizeof (opcode *)); + op = (opcode *) malloc (sizeof (opcode)); + opcodes[n_opcodes - 1] = op; + + op->nbytes = op->dbytes = 0; + memset (op->id, 0, sizeof (op->id)); + memset (op->var_start, 0, sizeof (op->var_start)); + for (i = 0; i < MAX_BYTES; i++) + { + op->b[i].decodable_mask = 0; + op->b[i].decodable_bits = 0; + } + op->comment = strdup (line); + op->comment[strlen (op->comment) - 1] = 0; + while (op->comment[0] && isspace (op->comment[0])) + op->comment++; + op->lineno = lineno; + op->nlines = 0; + op->lines = 0; + op->last_ind = 0; + op->semantics_label = 0; + op->nvaries = 0; + op->vary = 0; + + i = 0; + for (lp = line + 4; *lp; lp++) + { + bit = 7 - (i & 7); + byte = i >> 3; + + if (strncmp (lp, "*/", 2) == 0) + break; + else if ((lp[0] == ' ' && lp[1] == ' ') || (lp[0] == '\t')) + { + while (*lp == ' ' || *lp == '\t') + lp ++; + op->syntax = strdup (lp); + lp = strstr (op->syntax, "*/"); + if (lp) + { + *lp-- = 0; + while ((*lp == ' ' || *lp == '\t') + && lp > op->syntax) + *lp-- = 0; + } + break; + } + else if (*lp == ' ') + var_start = 1; + else + { + if (*lp == '0' || *lp == '1') + { + op->b[byte].decodable_mask |= 1 << bit; + var_start = 1; + if (op->dbytes < byte + 1) + op->dbytes = byte + 1; + } + else if (var_start) + { + op->var_start[i] = 1; + var_start = 0; + if (op->dbytes < byte + 1) + op->dbytes = byte + 1; + } + if (*lp == '1') + op->b[byte].decodable_bits |= 1 << bit; + + op->nbytes = byte + 1; + op->id[i++] = *lp; + } + } + } + } + else if (!skipping_section) + { + op->nlines++; + if (op->lines) + op->lines = + (char **) realloc (op->lines, op->nlines * sizeof (char *)); + else + op->lines = (char **) malloc (op->nlines * sizeof (char *)); + op->lines[op->nlines - 1] = strdup (line); + } + } + + { + int i, j; + for (i = 0; i < n_varies; i++) + { + Vary *v = vary[i]; + lprintf (sim_log, "V[%s] %d\n", v->name, v->nlen); + for (j = 0; j < v->n_patterns; j++) + lprintf (sim_log, " P %02x\n", v->patterns[j]); + } + } + + for (i = n_opcodes - 2; i >= 0; i--) + { + if (opcodes[i]->nlines == 0) + { + opcodes[i]->nlines = opcodes[i + 1]->nlines; + opcodes[i]->lines = opcodes[i + 1]->lines; + } + } + + for (i = 0; i < 256; i++) + indirect[i].type = T_unused; + + qsort (opcodes, n_opcodes, sizeof (opcodes[0]), op_cmp); + + vlist = (VaryRef *) malloc (n_varies * sizeof (VaryRef)); + + for (i = 0; i < n_opcodes; i++) + { + int j, b, v; + + for (j = 0; j < opcodes[i]->nbytes; j++) + lprintf (sim_log, "%s ", + prmb (opcodes[i]->b[j].decodable_mask, + opcodes[i]->b[j].decodable_bits)); + lprintf (sim_log, " %s\n", opcodes[i]->comment); + + for (j = 0; j < opcodes[i]->nbytes; j++) + { + for (b = 0; b < 8; b++) + if (isalpha (opcodes[i]->id[j * 8 + b])) + for (v = 0; v < n_varies; v++) + if (fieldcmp (opcodes[i], j * 8 + b, vary[v]->name)) + { + int nv = opcodes[i]->nvaries++; + if (nv) + opcodes[i]->vary = + (VaryRef *) realloc (opcodes[i]->vary, + (nv + 1) * sizeof (VaryRef)); + else + opcodes[i]->vary = + (VaryRef *) malloc ((nv + 1) * sizeof (VaryRef)); + + opcodes[i]->vary[nv].varyno = v; + opcodes[i]->vary[nv].byte = j; + opcodes[i]->vary[nv].shift = 8 - b - vary[v]->nlen; + lprintf (sim_log, "[vary %s shift %d]\n", + vary[v]->name, opcodes[i]->vary[nv].shift); + } + + } + } + + for (i = 0; i < n_opcodes; i++) + { + int i2; + int bytes = opcodes[i]->dbytes; + + lprintf (sim_log, "\nmask:"); + for (i2 = 0; i2 < opcodes[i]->nbytes; i2++) + lprintf (sim_log, " %02x", opcodes[i]->b[i2].decodable_mask); + lprintf (sim_log, "%*s%s\n", 13 - 3 * opcodes[i]->nbytes, "", + opcodes[i]->comment); + + lprintf (sim_log, "bits:"); + for (i2 = 0; i2 < opcodes[i]->nbytes; i2++) + lprintf (sim_log, " %02x", opcodes[i]->b[i2].decodable_bits); + lprintf (sim_log, "%*s(%s) %d byte%s\n", 13 - 3 * opcodes[i]->nbytes, + "", opcodes[i]->id, bytes, bytes == 1 ? "" : "s"); + + store_opcode_bits (opcodes[i], 0, indirect); + } + + dump_lines (&prefix_text, 0, 0); + + emit_indirect (indirect, 0); + + dump_lines (&suffix_text, 0, 0); + + if (sim_log) + log_indirect (indirect, 0); + + return errors; +} diff --git a/opcodes/rx-decode.c b/opcodes/rx-decode.c new file mode 100644 index 00000000000..3de4ba491db --- /dev/null +++ b/opcodes/rx-decode.c @@ -0,0 +1,14814 @@ +#line 2 "/work/sources/binutils/current/opcodes/rx-decode.opc" +/* -*- c -*- */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include "config.h" +#include "ansidecl.h" +#include "opcode/rx.h" + +#define RX_OPCODE_BIG_ENDIAN 0 + +typedef struct +{ + RX_Opcode_Decoded * rx; + int (* getbyte)(void *); + void * ptr; + unsigned char * op; +} LocalData; + +static int trace = 0; + +#define BSIZE 0 +#define WSIZE 1 +#define LSIZE 2 + +/* These are for when the upper bits are "don't care" or "undefined". */ +static int bwl[] = +{ + RX_Byte, + RX_Word, + RX_Long +}; + +static int sbwl[] = +{ + RX_SByte, + RX_SWord, + RX_Long +}; + +static int ubwl[] = +{ + RX_UByte, + RX_UWord, + RX_Long +}; + +static int memex[] = +{ + RX_SByte, + RX_SWord, + RX_Long, + RX_UWord +}; + +#define ID(x) rx->id = RXO_##x +#define OP(n,t,r,a) (rx->op[n].type = t, \ + rx->op[n].reg = r, \ + rx->op[n].addend = a ) +#define OPs(n,t,r,a,s) (OP (n,t,r,a), \ + rx->op[n].size = s ) + +/* This is for the BWL and BW bitfields. */ +static int SCALE[] = { 1, 2, 4 }; +/* This is for the prefix size enum. */ +static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 }; + +static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0, + 16, 17, 0, 0, 0, 0, 0, 0 }; + +static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 }; + +/* + *C a constant (immediate) c + *R A register + *I Register indirect, no offset + *Is Register indirect, with offset + *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code + *P standard displacement: type (r,[r]), reg, assumes UByte + *Pm memex displacement: type (r,[r]), reg, memex code + *cc condition code. */ + +#define DC(c) OP (0, RX_Operand_Immediate, 0, c) +#define DR(r) OP (0, RX_Operand_Register, r, 0) +#define DI(r,a) OP (0, RX_Operand_Indirect, r, a) +#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld); +#define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0) + +#define SC(i) OP (1, RX_Operand_Immediate, 0, i) +#define SR(r) OP (1, RX_Operand_Register, r, 0) +#define SI(r,a) OP (1, RX_Operand_Indirect, r, a) +#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld); +#define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1); +#define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m]; +#define Scc(cc) OP (1, RX_Operand_Condition, cc, 0) + +#define S2C(i) OP (2, RX_Operand_Immediate, 0, i) +#define S2R(r) OP (2, RX_Operand_Register, r, 0) +#define S2I(r,a) OP (2, RX_Operand_Indirect, r, a) +#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld); +#define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2); +#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m]; +#define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0) + +#define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz] +#define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz] +#define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz] +#define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long; + +#define F(f) store_flags(rx, f) + +#define AU ATTRIBUTE_UNUSED +#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr)) + +#define SYNTAX(x) rx->syntax = x + +#define UNSUPPORTED() \ + rx->syntax = "*unknown*" + +#define IMM(sf) immediate (sf, 0, ld) +#define IMMex(sf) immediate (sf, 1, ld) + +static int +immediate (int sfield, int ex, LocalData * ld) +{ + unsigned long i = 0, j; + + switch (sfield) + { +#define B ((unsigned long) GETBYTE()) + case 0: +#if RX_OPCODE_BIG_ENDIAN + i = B; + if (ex && (i & 0x80)) + i -= 0x100; + i <<= 24; + i |= B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; + j = B; + if (ex && (j & 0x80)) + j -= 0x100; + i |= j << 24; +#endif + break; + case 3: +#if RX_OPCODE_BIG_ENDIAN + i = B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; +#endif + if (ex && (i & 0x800000)) + i -= 0x1000000; + break; + case 2: +#if RX_OPCODE_BIG_ENDIAN + i |= B << 8; + i |= B; +#else + i |= B; + i |= B << 8; +#endif + if (ex && (i & 0x8000)) + i -= 0x10000; + break; + case 1: + i |= B; + if (ex && (i & 0x80)) + i -= 0x100; + break; + default: + abort(); + } + return i; +} + +static void +rx_disp (int n, int type, int reg, int size, LocalData * ld) +{ + int disp; + + ld->rx->op[n].reg = reg; + switch (type) + { + case 3: + ld->rx->op[n].type = RX_Operand_Register; + break; + case 0: + ld->rx->op[n].type = RX_Operand_Indirect; + ld->rx->op[n].addend = 0; + break; + case 1: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + case 2: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); +#if RX_OPCODE_BIG_ENDIAN + disp = disp * 256 + GETBYTE (); +#else + disp = disp + GETBYTE () * 256; +#endif + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + default: + abort (); + } +} + +/* The syntax is "OSZC" where each character is one of the following: + - = flag unchanged + 0 = flag cleared + 1 = flag set + ? = flag undefined + x = flag set (any letter will do, use it for hints :). */ + +static void +store_flags (RX_Opcode_Decoded * rx, char * str) +{ + int i, mask; + rx->flags_0 = 0; + rx->flags_1 = 0; + rx->flags_s = 0; + + for (i = 0; i < 4; i++) + { + mask = 8 >> i; + switch (str[i]) + { + case 0: + abort (); + case '-': + break; + case '0': + rx->flags_0 |= mask; + break; + case '1': + rx->flags_1 |= mask; + break; + case '?': + break; + default: + rx->flags_0 |= mask; + rx->flags_s |= mask; + break; + } + } +} + +int +rx_decode_opcode (unsigned long pc AU, + RX_Opcode_Decoded * rx, + int (* getbyte)(void *), + void * ptr) +{ + LocalData lds, * ld = &lds; + unsigned char op[20] = {0}; + + lds.rx = rx; + lds.getbyte = getbyte; + lds.ptr = ptr; + lds.op = op; + + memset (rx, 0, sizeof (*rx)); + BWL(LSIZE); + + +/*----------------------------------------------------------------------*/ +/* MOV */ + + GETBYTE (); + switch (op[0] & 0xff) + { + case 0x00: + { + /** 0000 0000 brk */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0000 brk */", + op[0]); + } + SYNTAX("brk"); +#line 957 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(brk); + + } + break; + case 0x01: + { + /** 0000 0001 dbt */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0001 dbt */", + op[0]); + } + SYNTAX("dbt"); +#line 960 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(dbt); + + } + break; + case 0x02: + { + /** 0000 0010 rts */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0010 rts */", + op[0]); + } + SYNTAX("rts"); +#line 740 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rts); + + /*----------------------------------------------------------------------*/ + /* NOP */ + + } + break; + case 0x03: + { + /** 0000 0011 nop */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0011 nop */", + op[0]); + } + SYNTAX("nop"); +#line 746 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(nop); + + /*----------------------------------------------------------------------*/ + /* STRING FUNCTIONS */ + + } + break; + case 0x04: + { + /** 0000 0100 bra.a %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0100 bra.a %a0 */", + op[0]); + } + SYNTAX("bra.a %a0"); +#line 718 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(RXC_always); DC(pc + IMMex(3)); + + } + break; + case 0x05: + { + /** 0000 0101 bsr.a %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0101 bsr.a %a0 */", + op[0]); + } + SYNTAX("bsr.a %a0"); +#line 734 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(jsr); DC(pc + IMMex(3)); + + } + break; + case 0x06: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_1: + { + /** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */ +#line 521 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 521 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 521 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 521 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sub %2%S2, %1"); +#line 522 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_2: + { + /** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */ +#line 509 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 509 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 509 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 509 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("cmp %2%S2, %1"); +#line 510 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F("OSZC"); + + /*----------------------------------------------------------------------*/ + /* SUB */ + + } + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_3: + { + /** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */ +#line 485 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 485 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 485 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 485 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add %1%S1, %0"); +#line 486 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(add); SPm(ss, rsrc, mx); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x0a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_4: + { + /** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */ +#line 582 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 582 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 582 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 582 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul %1%S1, %0"); +#line 583 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mul); SPm(ss, rsrc, mx); DR(rdst); F("O---"); + + } + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x0e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_5: + { + /** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */ +#line 398 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 398 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 398 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 398 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and %1%S1, %0"); +#line 399 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x12: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x13: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x14: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_6: + { + /** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */ +#line 416 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 416 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 416 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 416 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or %1%S1, %0"); +#line 417 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(or); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x15: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x16: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_7: + { + /** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */ +#line 534 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 534 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sp AU = op[1] & 0x03; +#line 534 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 534 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" sp = 0x%x,", sp); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sbb %1%S1, %0"); +#line 535 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F("OSZC"); + + /*----------------------------------------------------------------------*/ + /* ABS */ + + } + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_8: + { + /** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */ +#line 555 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 555 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 555 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 555 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("max %1%S1, %0"); +#line 556 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(max); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* MIN */ + + } + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_9: + { + /** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */ +#line 567 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 567 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 567 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 567 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("min %1%S1, %0"); +#line 568 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(min); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* MUL */ + + } + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_10: + { + /** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */ +#line 597 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 597 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 597 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 597 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emul %1%S1, %0"); +#line 598 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(emul); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* EMULU */ + + } + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_11: + { + /** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */ +#line 609 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 609 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 609 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 609 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emulu %1%S1, %0"); +#line 610 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(emulu); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* DIV */ + + } + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_12: + { + /** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */ +#line 621 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 621 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 621 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 621 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("div %1%S1, %0"); +#line 622 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(div); SPm(ss, rsrc, mx); DR(rdst); F("O---"); + + /*----------------------------------------------------------------------*/ + /* DIVU */ + + } + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_13: + { + /** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */ +#line 633 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 633 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 633 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 633 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("divu %1%S1, %0"); +#line 634 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(divu); SPm(ss, rsrc, mx); DR(rdst); F("O---"); + + /*----------------------------------------------------------------------*/ + /* SHIFT */ + + } + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_14: + { + /** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */ +#line 452 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 452 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 452 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 452 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("tst %1%S1, %2"); +#line 453 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); SPm(ss, rsrc, mx); S2R(rdst); F("-SZ-"); + + /*----------------------------------------------------------------------*/ + /* NEG */ + + } + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_15: + { + /** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */ +#line 431 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 431 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 431 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 431 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xor %1%S1, %0"); +#line 432 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(xor); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-"); + + /*----------------------------------------------------------------------*/ + /* NOT */ + + } + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_16: + { + /** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */ +#line 365 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 365 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 365 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 365 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xchg %1%S1, %0"); +#line 366 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(xchg); DR(rdst); SPm(ss, rsrc, mx); + + /*----------------------------------------------------------------------*/ + /* STZ/STNZ */ + + } + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_17: + { + /** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */ +#line 862 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 862 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 862 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 862 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("itof %1%S1, %0"); +#line 863 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(itof); DR (rdst); SPm(sd, rsrc, mx); F("-SZ-"); + + /*----------------------------------------------------------------------*/ + /* BIT OPS */ + + } + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x63: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x80: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xa0: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_18: + { + /** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */ +#line 473 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 473 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 473 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("adc %1%S1, %0"); +#line 474 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(adc); SPm(ss, rsrc, 2); DR(rdst); F("OSZC"); + + /*----------------------------------------------------------------------*/ + /* ADD */ + + } + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xa1: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_18; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xa2: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_18; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xa3: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_18; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + { + /** 0000 1dsp bra.s %a0 */ +#line 708 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dsp AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1dsp bra.s %a0 */", + op[0]); + printf (" dsp = 0x%x\n", dsp); + } + SYNTAX("bra.s %a0"); +#line 709 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(RXC_always); DC(pc + dsp3map[dsp]); + + } + break; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + { + /** 0001 n dsp b%1.s %a0 */ +#line 698 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int n AU = (op[0] >> 3) & 0x01; +#line 698 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dsp AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 n dsp b%1.s %a0 */", + op[0]); + printf (" n = 0x%x,", n); + printf (" dsp = 0x%x\n", dsp); + } + SYNTAX("b%1.s %a0"); +#line 699 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(n); DC(pc + dsp3map[dsp]); + + } + break; + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x26: + case 0x27: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + case 0x2c: + case 0x2d: + case 0x2f: + { + /** 0010 cond b%1.b %a0 */ +#line 701 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int cond AU = op[0] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 cond b%1.b %a0 */", + op[0]); + printf (" cond = 0x%x\n", cond); + } + SYNTAX("b%1.b %a0"); +#line 702 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(cond); DC(pc + IMMex (1)); + + } + break; + case 0x2e: + { + /** 0010 1110 bra.b %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1110 bra.b %a0 */", + op[0]); + } + SYNTAX("bra.b %a0"); +#line 712 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(RXC_always); DC(pc + IMMex(1)); + + } + break; + case 0x38: + { + /** 0011 1000 bra.w %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1000 bra.w %a0 */", + op[0]); + } + SYNTAX("bra.w %a0"); +#line 715 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(RXC_always); DC(pc + IMMex(2)); + + } + break; + case 0x39: + { + /** 0011 1001 bsr.w %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1001 bsr.w %a0 */", + op[0]); + } + SYNTAX("bsr.w %a0"); +#line 731 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(jsr); DC(pc + IMMex(2)); + + } + break; + case 0x3a: + case 0x3b: + { + /** 0011 101c b%1.w %a0 */ +#line 704 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int c AU = op[0] & 0x01; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 101c b%1.w %a0 */", + op[0]); + printf (" c = 0x%x\n", c); + } + SYNTAX("b%1.w %a0"); +#line 705 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(c); DC(pc + IMMex (2)); + + + } + break; + case 0x3c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_19: + { + /** 0011 11sz d dst sppp mov%s #%1, %0 */ +#line 294 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[0] & 0x03; +#line 294 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int d AU = (op[1] >> 7) & 0x01; +#line 294 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dst AU = (op[1] >> 4) & 0x07; +#line 294 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sppp AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 11sz d dst sppp mov%s #%1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" d = 0x%x,", d); + printf (" dst = 0x%x,", dst); + printf (" sppp = 0x%x\n", sppp); + } + SYNTAX("mov%s #%1, %0"); +#line 295 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F("----"); + + } + break; + } + break; + case 0x3d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_19; + break; + } + break; + case 0x3e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_19; + break; + } + break; + case 0x3f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0011 1111 rega regb rtsd #%1, %2-%0 */ +#line 383 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rega AU = (op[1] >> 4) & 0x0f; +#line 383 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int regb AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 1111 rega regb rtsd #%1, %2-%0 */", + op[0], op[1]); + printf (" rega = 0x%x,", rega); + printf (" regb = 0x%x\n", regb); + } + SYNTAX("rtsd #%1, %2-%0"); +#line 384 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb); + + /*----------------------------------------------------------------------*/ + /* AND */ + + } + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_20: + { + /** 0100 00ss rsrc rdst sub %2%S2, %1 */ +#line 518 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 518 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 518 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 00ss rsrc rdst sub %2%S2, %1 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sub %2%S2, %1"); +#line 519 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_20; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_20; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_20; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_21: + { + /** 0100 01ss rsrc rdst cmp %2%S2, %1 */ +#line 506 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 506 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 506 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 01ss rsrc rdst cmp %2%S2, %1 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("cmp %2%S2, %1"); +#line 507 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); S2P(ss, rsrc); SR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_21; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_21; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_21; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_22: + { + /** 0100 10ss rsrc rdst add %1%S1, %0 */ +#line 482 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 482 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 482 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 10ss rsrc rdst add %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add %1%S1, %0"); +#line 483 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(add); SP(ss, rsrc); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_22; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_22; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_22; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_23: + { + /** 0100 11ss rsrc rdst mul %1%S1, %0 */ +#line 579 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 579 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 579 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 11ss rsrc rdst mul %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul %1%S1, %0"); +#line 580 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mul); SP(ss, rsrc); DR(rdst); F("O---"); + + } + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_23; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_23; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_23; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_24: + { + /** 0101 00ss rsrc rdst and %1%S1, %0 */ +#line 395 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 395 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 395 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0101 00ss rsrc rdst and %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and %1%S1, %0"); +#line 396 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); SP(ss, rsrc); DR(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_24; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_24; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_24; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_25: + { + /** 0101 01ss rsrc rdst or %1%S1, %0 */ +#line 413 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 413 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 413 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0101 01ss rsrc rdst or %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or %1%S1, %0"); +#line 414 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(or); SP(ss, rsrc); DR(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_25; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_25; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_25; + break; + } + break; + case 0x58: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_26: + { + /** 0101 1 s ss rsrc rdst movu%s %1, %0 */ +#line 334 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int s AU = (op[0] >> 2) & 0x01; +#line 334 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 334 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 334 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0101 1 s ss rsrc rdst movu%s %1, %0 */", + op[0], op[1]); + printf (" s = 0x%x,", s); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("movu%s %1, %0"); +#line 335 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F("----"); + + } + break; + } + break; + case 0x59: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0000 immm rdst sub #%2, %0 */ +#line 515 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 515 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0000 immm rdst sub #%2, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sub #%2, %0"); +#line 516 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); S2C(immm); SR(rdst); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0001 immm rdst cmp #%2, %1 */ +#line 497 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 497 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 immm rdst cmp #%2, %1 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("cmp #%2, %1"); +#line 498 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); S2C(immm); SR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0010 immm rdst add #%1, %0 */ +#line 479 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 479 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0010 immm rdst add #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add #%1, %0"); +#line 480 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(add); SC(immm); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x63: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0011 immm rdst mul #%1, %0 */ +#line 573 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 573 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0011 immm rdst mul #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul #%1, %0"); +#line 574 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mul); DR(rdst); SC(immm); F("O---"); + + } + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0100 immm rdst and #%1, %0 */ +#line 389 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 389 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0100 immm rdst and #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and #%1, %0"); +#line 390 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); SC(immm); DR(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0101 immm rdst or #%1, %0 */ +#line 407 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 407 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0101 immm rdst or #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or #%1, %0"); +#line 408 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(or); SC(immm); DR(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0110 immm rdst mov%s #%1, %0 */ +#line 291 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 291 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0110 immm rdst mov%s #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s #%1, %0"); +#line 292 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); DR(rdst); SC(immm); F("----"); + + } + break; + } + break; + case 0x67: + { + /** 0110 0111 rtsd #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 0111 rtsd #%1 */", + op[0]); + } + SYNTAX("rtsd #%1"); +#line 381 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rtsd); SC(IMM(1) * 4); + + } + break; + case 0x68: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_27: + { + /** 0110 100i mmmm rdst shlr #%2, %0 */ +#line 659 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int i AU = op[0] & 0x01; +#line 659 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mmmm AU = (op[1] >> 4) & 0x0f; +#line 659 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 100i mmmm rdst shlr #%2, %0 */", + op[0], op[1]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shlr #%2, %0"); +#line 660 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("-SZC"); + + } + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_27; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_28: + { + /** 0110 101i mmmm rdst shar #%2, %0 */ +#line 649 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int i AU = op[0] & 0x01; +#line 649 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mmmm AU = (op[1] >> 4) & 0x0f; +#line 649 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 101i mmmm rdst shar #%2, %0 */", + op[0], op[1]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shar #%2, %0"); +#line 650 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("0SZC"); + + } + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_28; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_29: + { + /** 0110 110i mmmm rdst shll #%2, %0 */ +#line 639 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int i AU = op[0] & 0x01; +#line 639 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mmmm AU = (op[1] >> 4) & 0x0f; +#line 639 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 110i mmmm rdst shll #%2, %0 */", + op[0], op[1]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shll #%2, %0"); +#line 640 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_29; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 1110 dsta dstb pushm %1-%2 */ +#line 347 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dsta AU = (op[1] >> 4) & 0x0f; +#line 347 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dstb AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 1110 dsta dstb pushm %1-%2 */", + op[0], op[1]); + printf (" dsta = 0x%x,", dsta); + printf (" dstb = 0x%x\n", dstb); + } + SYNTAX("pushm %1-%2"); +#line 348 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(pushm); SR(dsta); S2R(dstb); F("----"); + + } + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 1111 dsta dstb popm %1-%2 */ +#line 344 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dsta AU = (op[1] >> 4) & 0x0f; +#line 344 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dstb AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 1111 dsta dstb popm %1-%2 */", + op[0], op[1]); + printf (" dsta = 0x%x,", dsta); + printf (" dstb = 0x%x\n", dstb); + } + SYNTAX("popm %1-%2"); +#line 345 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(popm); SR(dsta); S2R(dstb); F("----"); + + } + break; + } + break; + case 0x70: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_30: + { + /** 0111 00im rsrc rdst add #%1, %2, %0 */ +#line 488 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = op[0] & 0x03; +#line 488 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 488 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 00im rsrc rdst add #%1, %2, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add #%1, %2, %0"); +#line 489 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x71: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_30; + break; + } + break; + case 0x72: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_30; + break; + } + break; + case 0x73: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_30; + break; + } + break; + case 0x74: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + op_semantics_31: + { + /** 0111 01im 0000 rsrc cmp #%2, %1%S1 */ +#line 500 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = op[0] & 0x03; +#line 500 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0000 rsrc cmp #%2, %1%S1 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("cmp #%2, %1%S1"); +#line 501 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); SR(rsrc); S2C(IMMex(im)); F("OSZC"); + + } + break; + case 0x10: + op_semantics_32: + { + /** 0111 01im 0001rdst mul #%1, %0 */ +#line 576 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = op[0] & 0x03; +#line 576 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0001rdst mul #%1, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul #%1, %0"); +#line 577 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mul); DR(rdst); SC(IMMex(im)); F("O---"); + + } + break; + case 0x20: + op_semantics_33: + { + /** 0111 01im 0010 rdst and #%1, %0 */ +#line 392 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = op[0] & 0x03; +#line 392 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0010 rdst and #%1, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and #%1, %0"); +#line 393 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); SC(IMMex(im)); DR(rdst); F("-SZ-"); + + } + break; + case 0x30: + op_semantics_34: + { + /** 0111 01im 0011 rdst or #%1, %0 */ +#line 410 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = op[0] & 0x03; +#line 410 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0011 rdst or #%1, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or #%1, %0"); +#line 411 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(or); SC(IMMex(im)); DR(rdst); F("-SZ-"); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x75: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + goto op_semantics_31; + break; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + goto op_semantics_32; + break; + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x26: + case 0x27: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + goto op_semantics_33; + break; + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x34: + case 0x35: + case 0x36: + case 0x37: + case 0x38: + case 0x39: + case 0x3a: + case 0x3b: + case 0x3c: + case 0x3d: + case 0x3e: + case 0x3f: + goto op_semantics_34; + break; + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + { + /** 0111 0101 0100 rdst mov%s #%1, %0 */ +#line 285 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0101 0100 rdst mov%s #%1, %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s #%1, %0"); +#line 286 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); DR(rdst); SC(IMM (1)); F("----"); + + } + break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + { + /** 0111 0101 0101 rsrc cmp #%2, %1 */ +#line 503 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0101 0101 rsrc cmp #%2, %1 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("cmp #%2, %1"); +#line 504 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); SR(rsrc); S2C(IMM(1)); F("OSZC"); + + } + break; + case 0x60: + { + /** 0111 0101 0110 0000 int #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0101 0110 0000 int #%1 */", + op[0], op[1]); + } + SYNTAX("int #%1"); +#line 963 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(int); SC(IMM(1)); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x76: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + goto op_semantics_31; + break; + case 0x10: + goto op_semantics_32; + break; + case 0x20: + goto op_semantics_33; + break; + case 0x30: + goto op_semantics_34; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x77: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + goto op_semantics_31; + break; + case 0x10: + goto op_semantics_32; + break; + case 0x20: + goto op_semantics_33; + break; + case 0x30: + goto op_semantics_34; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x78: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_35: + { + /** 0111 100b ittt rdst bset #%1, %0 */ +#line 874 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int b AU = op[0] & 0x01; +#line 874 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ittt AU = (op[1] >> 4) & 0x0f; +#line 874 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 100b ittt rdst bset #%1, %0 */", + op[0], op[1]); + printf (" b = 0x%x,", b); + printf (" ittt = 0x%x,", ittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bset #%1, %0"); +#line 875 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F("----"); + + + } + break; + } + break; + case 0x79: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_35; + break; + } + break; + case 0x7a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_36: + { + /** 0111 101b ittt rdst bclr #%1, %0 */ +#line 884 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int b AU = op[0] & 0x01; +#line 884 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ittt AU = (op[1] >> 4) & 0x0f; +#line 884 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 101b ittt rdst bclr #%1, %0 */", + op[0], op[1]); + printf (" b = 0x%x,", b); + printf (" ittt = 0x%x,", ittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bclr #%1, %0"); +#line 885 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F("----"); + + + } + break; + } + break; + case 0x7b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_36; + break; + } + break; + case 0x7c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_37: + { + /** 0111 110b ittt rdst btst #%2, %1 */ +#line 894 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int b AU = op[0] & 0x01; +#line 894 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ittt AU = (op[1] >> 4) & 0x0f; +#line 894 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 110b ittt rdst btst #%2, %1 */", + op[0], op[1]); + printf (" b = 0x%x,", b); + printf (" ittt = 0x%x,", ittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("btst #%2, %1"); +#line 895 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F("--ZC"); + + + } + break; + } + break; + case 0x7d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_37; + break; + } + break; + case 0x7e: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + { + /** 0111 1110 0000 rdst not %0 */ +#line 437 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0000 rdst not %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("not %0"); +#line 438 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(xor); DR(rdst); SR(rdst); S2C(~0); F("-SZ-"); + + } + break; + case 0x10: + { + /** 0111 1110 0001 rdst neg %0 */ +#line 458 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0001 rdst neg %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("neg %0"); +#line 459 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); DR(rdst); SC(0); S2R(rdst); F("OSZC"); + + } + break; + case 0x20: + { + /** 0111 1110 0010 rdst abs %0 */ +#line 540 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0010 rdst abs %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("abs %0"); +#line 541 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(abs); DR(rdst); SR(rdst); F("OSZ-"); + + } + break; + case 0x30: + { + /** 0111 1110 0011 rdst sat %0 */ +#line 814 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0011 rdst sat %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sat %0"); +#line 815 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sat); DR (rdst); + + } + break; + case 0x40: + { + /** 0111 1110 0100 rdst rorc %0 */ +#line 674 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0100 rdst rorc %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rorc %0"); +#line 675 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rorc); DR(rdst); F("-SZC"); + + } + break; + case 0x50: + { + /** 0111 1110 0101 rdst rolc %0 */ +#line 671 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0101 rdst rolc %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rolc %0"); +#line 672 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rolc); DR(rdst); F("-SZC"); + + } + break; + case 0x80: + case 0x90: + case 0xa0: + { + /** 0111 1110 10sz rsrc push%s %1 */ +#line 353 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 353 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 10sz rsrc push%s %1 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("push%s %1"); +#line 354 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F("----"); + + } + break; + case 0xb0: + { + /** 0111 1110 1011 rdst pop %0 */ +#line 350 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 1011 rdst pop %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("pop %0"); +#line 351 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F("----"); + + } + break; + case 0xc0: + case 0xd0: + { + /** 0111 1110 110 crsrc pushc %1 */ +#line 926 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int crsrc AU = op[1] & 0x1f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 110 crsrc pushc %1 */", + op[0], op[1]); + printf (" crsrc = 0x%x\n", crsrc); + } + SYNTAX("pushc %1"); +#line 927 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16); + + } + break; + case 0xe0: + case 0xf0: + { + /** 0111 1110 111 crdst popc %0 */ +#line 923 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int crdst AU = op[1] & 0x1f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 111 crdst popc %0 */", + op[0], op[1]); + printf (" crdst = 0x%x\n", crdst); + } + SYNTAX("popc %0"); +#line 924 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7f: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + { + /** 0111 1111 0000 rsrc jmp %0 */ +#line 724 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0000 rsrc jmp %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("jmp %0"); +#line 725 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branch); Scc(RXC_always); DR(rsrc); + + } + break; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + { + /** 0111 1111 0001 rsrc jsr %0 */ +#line 727 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0001 rsrc jsr %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("jsr %0"); +#line 728 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(jsr); DR(rsrc); + + } + break; + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + { + /** 0111 1111 0100 rsrc bra.l %0 */ +#line 720 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0100 rsrc bra.l %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bra.l %0"); +#line 721 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(branchrel); Scc(RXC_always); DR(rsrc); + + + } + break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + { + /** 0111 1111 0101 rsrc bsr.l %0 */ +#line 736 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0101 rsrc bsr.l %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bsr.l %0"); +#line 737 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(jsrrel); DR(rsrc); + + } + break; + case 0x80: + case 0x81: + case 0x82: + { + /** 0111 1111 1000 00sz suntil%s */ +#line 760 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 00sz suntil%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("suntil%s"); +#line 761 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(suntil); BWL(sz); F("OSZC"); + + } + break; + case 0x83: + { + /** 0111 1111 1000 0011 scmpu */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 0011 scmpu */", + op[0], op[1]); + } + SYNTAX("scmpu"); +#line 752 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(scmpu); F("--ZC"); + + } + break; + case 0x84: + case 0x85: + case 0x86: + { + /** 0111 1111 1000 01sz swhile%s */ +#line 763 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 01sz swhile%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("swhile%s"); +#line 764 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(swhile); BWL(sz); F("OSZC"); + + } + break; + case 0x87: + { + /** 0111 1111 1000 0111 smovu */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 0111 smovu */", + op[0], op[1]); + } + SYNTAX("smovu"); +#line 755 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(smovu); + + } + break; + case 0x88: + case 0x89: + case 0x8a: + { + /** 0111 1111 1000 10sz sstr%s */ +#line 769 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 10sz sstr%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("sstr%s"); +#line 770 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sstr); BWL(sz); + + /*----------------------------------------------------------------------*/ + /* RMPA */ + + } + break; + case 0x8b: + { + /** 0111 1111 1000 1011 smovb */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 1011 smovb */", + op[0], op[1]); + } + SYNTAX("smovb"); +#line 758 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(smovb); + + } + break; + case 0x8c: + case 0x8d: + case 0x8e: + { + /** 0111 1111 1000 11sz rmpa%s */ +#line 775 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 11sz rmpa%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("rmpa%s"); +#line 776 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rmpa); BWL(sz); F("OS--"); + + /*----------------------------------------------------------------------*/ + /* HI/LO stuff */ + + } + break; + case 0x8f: + { + /** 0111 1111 1000 1111 smovf */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 1111 smovf */", + op[0], op[1]); + } + SYNTAX("smovf"); +#line 767 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(smovf); + + } + break; + case 0x93: + { + /** 0111 1111 1001 0011 satr */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0011 satr */", + op[0], op[1]); + } + SYNTAX("satr"); +#line 818 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(satr); + + /*----------------------------------------------------------------------*/ + /* FLOAT */ + + } + break; + case 0x94: + { + /** 0111 1111 1001 0100 rtfi */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0100 rtfi */", + op[0], op[1]); + } + SYNTAX("rtfi"); +#line 951 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rtfi); + + } + break; + case 0x95: + { + /** 0111 1111 1001 0101 rte */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0101 rte */", + op[0], op[1]); + } + SYNTAX("rte"); +#line 954 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rte); + + } + break; + case 0x96: + { + /** 0111 1111 1001 0110 wait */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0110 wait */", + op[0], op[1]); + } + SYNTAX("wait"); +#line 966 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(wait); + + /*----------------------------------------------------------------------*/ + /* SCcnd */ + + } + break; + case 0xa0: + case 0xa1: + case 0xa2: + case 0xa3: + case 0xa4: + case 0xa5: + case 0xa6: + case 0xa7: + case 0xa8: + case 0xa9: + case 0xaa: + case 0xab: + case 0xac: + case 0xad: + case 0xae: + case 0xaf: + { + /** 0111 1111 1010 rdst setpsw %0 */ +#line 920 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1010 rdst setpsw %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("setpsw %0"); +#line 921 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(setpsw); DF(rdst); + + } + break; + case 0xb0: + case 0xb1: + case 0xb2: + case 0xb3: + case 0xb4: + case 0xb5: + case 0xb6: + case 0xb7: + case 0xb8: + case 0xb9: + case 0xba: + case 0xbb: + case 0xbc: + case 0xbd: + case 0xbe: + case 0xbf: + { + /** 0111 1111 1011 rdst clrpsw %0 */ +#line 917 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1011 rdst clrpsw %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("clrpsw %0"); +#line 918 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(clrpsw); DF(rdst); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x80: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_38: + { + /** 10sz 0dsp a dst b src mov%s %1, %0 */ +#line 311 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[0] >> 4) & 0x03; +#line 311 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dsp AU = op[0] & 0x07; +#line 311 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int a AU = (op[1] >> 7) & 0x01; +#line 311 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dst AU = (op[1] >> 4) & 0x07; +#line 311 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int b AU = (op[1] >> 3) & 0x01; +#line 311 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int src AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 10sz 0dsp a dst b src mov%s %1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" dsp = 0x%x,", dsp); + printf (" a = 0x%x,", a); + printf (" dst = 0x%x,", dst); + printf (" b = 0x%x,", b); + printf (" src = 0x%x\n", src); + } + SYNTAX("mov%s %1, %0"); +#line 312 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F("----"); + + } + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_39: + { + /** 10sz 1dsp a src b dst mov%s %1, %0 */ +#line 308 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[0] >> 4) & 0x03; +#line 308 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dsp AU = op[0] & 0x07; +#line 308 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int a AU = (op[1] >> 7) & 0x01; +#line 308 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int src AU = (op[1] >> 4) & 0x07; +#line 308 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int b AU = (op[1] >> 3) & 0x01; +#line 308 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dst AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 10sz 1dsp a src b dst mov%s %1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" dsp = 0x%x,", dsp); + printf (" a = 0x%x,", a); + printf (" src = 0x%x,", src); + printf (" b = 0x%x,", b); + printf (" dst = 0x%x\n", dst); + } + SYNTAX("mov%s %1, %0"); +#line 309 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F("----"); + + } + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x98: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x99: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xa0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xa9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xaa: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xab: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xac: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xad: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xae: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xaf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xb0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_40: + { + /** 1011 w dsp a src b dst movu%s %1, %0 */ +#line 331 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int w AU = (op[0] >> 3) & 0x01; +#line 331 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dsp AU = op[0] & 0x07; +#line 331 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int a AU = (op[1] >> 7) & 0x01; +#line 331 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int src AU = (op[1] >> 4) & 0x07; +#line 331 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int b AU = (op[1] >> 3) & 0x01; +#line 331 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int dst AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1011 w dsp a src b dst movu%s %1, %0 */", + op[0], op[1]); + printf (" w = 0x%x,", w); + printf (" dsp = 0x%x,", dsp); + printf (" a = 0x%x,", a); + printf (" src = 0x%x,", src); + printf (" b = 0x%x,", b); + printf (" dst = 0x%x\n", dst); + } + SYNTAX("movu%s %1, %0"); +#line 332 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F("----"); + + } + break; + } + break; + case 0xb1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xba: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbc: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbd: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbe: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_41: + { + /** 11sz sd ss rsrc rdst mov%s %1, %0 */ +#line 297 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[0] >> 4) & 0x03; +#line 297 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = (op[0] >> 2) & 0x03; +#line 297 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 297 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 297 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 11sz sd ss rsrc rdst mov%s %1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" sd = 0x%x,", sd); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s %1, %0"); +#line 298 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); sBWL(sz); F("----"); + if ((ss == 3) && (sd != 3)) + { + SD(ss, rdst, sz); DD(sd, rsrc, sz); + } + else + { + SD(ss, rsrc, sz); DD(sd, rdst, sz); + } + + } + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdc: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdd: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xde: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xf0: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + op_semantics_42: + { + /** 1111 00sd rdst 0bit bset #%1, %0%S0 */ +#line 868 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 868 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 868 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bit AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 00sd rdst 0bit bset #%1, %0%S0 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bset #%1, %0%S0"); +#line 869 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F("----"); + + } + break; + case 0x08: + op_semantics_43: + { + /** 1111 00sd rdst 1bit bclr #%1, %0%S0 */ +#line 878 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 878 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 878 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bit AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 00sd rdst 1bit bclr #%1, %0%S0 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bclr #%1, %0%S0"); +#line 879 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F("----"); + + } + break; + } + break; + case 0xf1: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + goto op_semantics_42; + break; + case 0x08: + goto op_semantics_43; + break; + } + break; + case 0xf2: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + goto op_semantics_42; + break; + case 0x08: + goto op_semantics_43; + break; + } + break; + case 0xf3: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + goto op_semantics_42; + break; + case 0x08: + goto op_semantics_43; + break; + } + break; + case 0xf4: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + op_semantics_44: + { + /** 1111 01sd rdst 0bit btst #%2, %1%S1 */ +#line 888 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 888 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 888 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bit AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 01sd rdst 0bit btst #%2, %1%S1 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("btst #%2, %1%S1"); +#line 889 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F("--ZC"); + + } + break; + case 0x08: + op_semantics_45: + { + /** 1111 01ss rsrc 10sz push%s %1 */ +#line 356 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 356 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 356 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 01ss rsrc 10sz push%s %1 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("push%s %1"); +#line 357 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F("----"); + + /*----------------------------------------------------------------------*/ + /* XCHG */ + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf5: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + goto op_semantics_44; + break; + case 0x08: + goto op_semantics_45; + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf6: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + goto op_semantics_44; + break; + case 0x08: + goto op_semantics_45; + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf7: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + goto op_semantics_44; + break; + case 0x08: + goto op_semantics_45; + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_46: + { + /** 1111 10sd rdst im sz mov%s #%1, %0 */ +#line 288 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 288 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 288 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 288 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 10sd rdst im sz mov%s #%1, %0 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" im = 0x%x,", im); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("mov%s #%1, %0"); +#line 289 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); sBWL (sz); DD(sd, rdst, sz); SC(IMMex(im)); F("----"); + + } + break; + } + break; + case 0xf9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_46; + break; + } + break; + case 0xfa: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_46; + break; + } + break; + case 0xfb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_46; + break; + } + break; + case 0xfc: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */ +#line 530 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 530 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sbb %1, %0"); +#line 531 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sbb); SR (rsrc); DR(rdst); F("OSZC"); + + /* FIXME: only supports .L */ + } + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */ +#line 461 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 461 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("neg %2, %0"); +#line 462 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); DR(rdst); SC(0); S2R(rsrc); F("OSZC"); + + /*----------------------------------------------------------------------*/ + /* ADC */ + + } + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */ +#line 470 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 470 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("adc %1, %0"); +#line 471 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(adc); SR(rsrc); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */ +#line 543 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 543 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("abs %1, %0"); +#line 544 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(abs); DR(rdst); SR(rsrc); F("OSZ-"); + + /*----------------------------------------------------------------------*/ + /* MAX */ + + } + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_47: + { + /** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */ +#line 552 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 552 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 552 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("max %1%S1, %0"); +#line 553 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(max); SP(ss, rsrc); DR(rdst); + + } + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_47; + break; + } + break; + case 0x12: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_47; + break; + } + break; + case 0x13: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_47; + break; + } + break; + case 0x14: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_48: + { + /** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */ +#line 564 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 564 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 564 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("min %1%S1, %0"); +#line 565 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(min); SP(ss, rsrc); DR(rdst); + + } + break; + } + break; + case 0x15: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_48; + break; + } + break; + case 0x16: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_48; + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_48; + break; + } + break; + case 0x18: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_49: + { + /** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */ +#line 594 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 594 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 594 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emul %1%S1, %0"); +#line 595 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(emul); SP(ss, rsrc); DR(rdst); + + } + break; + } + break; + case 0x19: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_49; + break; + } + break; + case 0x1a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_49; + break; + } + break; + case 0x1b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_49; + break; + } + break; + case 0x1c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_50: + { + /** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */ +#line 606 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 606 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 606 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emulu %1%S1, %0"); +#line 607 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(emulu); SP(ss, rsrc); DR(rdst); + + } + break; + } + break; + case 0x1d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_50; + break; + } + break; + case 0x1e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_50; + break; + } + break; + case 0x1f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_50; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_51: + { + /** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */ +#line 618 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 618 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 618 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("div %1%S1, %0"); +#line 619 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(div); SP(ss, rsrc); DR(rdst); F("O---"); + + } + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_51; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_51; + break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_51; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_52: + { + /** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */ +#line 630 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 630 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 630 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("divu %1%S1, %0"); +#line 631 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(divu); SP(ss, rsrc); DR(rdst); F("O---"); + + } + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_52; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_52; + break; + } + break; + case 0x27: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_52; + break; + } + break; + case 0x30: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_53: + { + /** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */ +#line 449 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 449 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 449 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("tst %1%S1, %2"); +#line 450 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); SP(ss, rsrc); S2R(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x31: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_53; + break; + } + break; + case 0x32: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_53; + break; + } + break; + case 0x33: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_53; + break; + } + break; + case 0x34: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_54: + { + /** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */ +#line 428 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 428 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 428 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xor %1%S1, %0"); +#line 429 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(xor); SP(ss, rsrc); DR(rdst); F("-SZ-"); + + } + break; + } + break; + case 0x35: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_54; + break; + } + break; + case 0x36: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_54; + break; + } + break; + case 0x37: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_54; + break; + } + break; + case 0x3b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0011 1011 rsrc rdst not %1, %0 */ +#line 440 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 440 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0011 1011 rsrc rdst not %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("not %1, %0"); +#line 441 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(xor); DR(rdst); SR(rsrc); S2C(~0); F("-SZ-"); + + /*----------------------------------------------------------------------*/ + /* TST */ + + } + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_55: + { + /** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */ +#line 362 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 362 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 362 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xchg %1%S1, %0"); +#line 363 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(xchg); DR(rdst); SP(ss, rsrc); + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_55; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_55; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_55; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_56: + { + /** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */ +#line 859 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 859 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 859 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("itof %1%S1, %0"); +#line 860 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(itof); DR (rdst); SP(sd, rsrc); F("-SZ-"); + + } + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_56; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_56; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_56; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_57: + { + /** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */ +#line 871 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 871 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 871 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bset %1, %0%S0"); +#line 872 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F("----"); + + } + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_57; + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_57; + break; + } + break; + case 0x63: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_57; + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_58: + { + /** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */ +#line 881 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 881 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 881 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bclr %1, %0%S0"); +#line 882 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F("----"); + + } + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_58; + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_58; + break; + } + break; + case 0x67: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_58; + break; + } + break; + case 0x68: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_59: + { + /** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */ +#line 891 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 891 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 891 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("btst %2, %1%S1"); +#line 892 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F("--ZC"); + + } + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_59; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_59; + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_59; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_60: + { + /** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */ +#line 901 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 901 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 901 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bnot %1, %0%S0"); +#line 902 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); + + } + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_60; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_60; + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_60; + break; + } + break; + case 0x80: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_61: + { + /** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */ +#line 838 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 838 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 838 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fsub %1%S1, %0"); +#line 839 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + + } + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_61; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_61; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_61; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_62: + { + /** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */ +#line 832 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 832 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 832 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fcmp %1%S1, %0"); +#line 833 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F("OSZ-"); + + } + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_62; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_62; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_62; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_63: + { + /** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */ +#line 826 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 826 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 826 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fadd %1%S1, %0"); +#line 827 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + + } + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_63; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_63; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_63; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_64: + { + /** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */ +#line 847 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 847 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 847 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fmul %1%S1, %0"); +#line 848 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + + } + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_64; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_64; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_64; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_65: + { + /** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */ +#line 853 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 853 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 853 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fdiv %1%S1, %0"); +#line 854 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + + } + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_65; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_65; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_65; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_66: + { + /** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */ +#line 841 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 841 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 841 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("ftoi %1%S1, %0"); +#line 842 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + + } + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_66; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_66; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_66; + break; + } + break; + case 0x98: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_67: + { + /** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */ +#line 856 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 856 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 856 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("round %1%S1, %0"); +#line 857 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + + } + break; + } + break; + case 0x99: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_67; + break; + } + break; + case 0x9a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_67; + break; + } + break; + case 0x9b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_67; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_68: + { + /** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */ +#line 971 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[1] >> 2) & 0x03; +#line 971 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 971 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 971 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int cond AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" cond = 0x%x\n", cond); + } + SYNTAX("sc%1%s %0"); +#line 972 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond); + + } + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + op_semantics_69: + { + /** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */ +#line 908 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bit AU = (op[1] >> 2) & 0x07; +#line 908 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 908 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 908 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int cond AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */", + op[0], op[1], op[2]); + printf (" bit = 0x%x,", bit); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" cond = 0x%x\n", cond); + } + SYNTAX("bm%2 #%1, %0%S0"); +#line 909 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE); + + } + break; + case 0x0f: + op_semantics_70: + { + /** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */ +#line 898 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bit AU = (op[1] >> 2) & 0x07; +#line 898 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 898 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */", + op[0], op[1], op[2]); + printf (" bit = 0x%x,", bit); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bnot #%1, %0%S0"); +#line 899 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); + + } + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf0: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf1: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf2: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf3: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf4: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf5: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf6: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf7: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf8: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf9: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfa: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfb: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfc: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfd: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfe: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xff: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xfd: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */ +#line 781 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 781 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("mulhi %1, %2"); +#line 782 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mulhi); SR(srca); S2R(srcb); F("----"); + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0001 srca srcb mullo %1, %2 */ +#line 784 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 784 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("mullo %1, %2"); +#line 785 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mullo); SR(srca); S2R(srcb); F("----"); + + } + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0100 srca srcb machi %1, %2 */ +#line 787 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 787 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0100 srca srcb machi %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("machi %1, %2"); +#line 788 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(machi); SR(srca); S2R(srcb); F("----"); + + } + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0101 srca srcb maclo %1, %2 */ +#line 790 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 790 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("maclo %1, %2"); +#line 791 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(maclo); SR(srca); S2R(srcb); F("----"); + + } + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + { + /** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */ +#line 793 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("mvtachi %1"); +#line 794 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mvtachi); SR(rsrc); F("----"); + + } + break; + case 0x10: + { + /** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */ +#line 796 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("mvtaclo %1"); +#line 797 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mvtaclo); SR(rsrc); F("----"); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x18: + GETBYTE (); + switch (op[2] & 0xef) + { + case 0x00: + { + /** 1111 1101 0001 1000 000i 0000 racw #%1 */ +#line 808 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int i AU = (op[2] >> 4) & 0x01; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1000 000i 0000 racw #%1 */", + op[0], op[1], op[2]); + printf (" i = 0x%x\n", i); + } + SYNTAX("racw #%1"); +#line 809 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(racw); SC(i+1); F("----"); + + /*----------------------------------------------------------------------*/ + /* SAT */ + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x1f: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + { + /** 1111 1101 0001 1111 0000 rdst mvfachi %0 */ +#line 799 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfachi %0"); +#line 800 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mvfachi); DR(rdst); F("----"); + + } + break; + case 0x10: + { + /** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */ +#line 805 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfaclo %0"); +#line 806 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mvfaclo); DR(rdst); F("----"); + + } + break; + case 0x20: + { + /** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */ +#line 802 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfacmi %0"); +#line 803 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mvfacmi); DR(rdst); F("----"); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_71: + { + /** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */ +#line 323 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int p AU = (op[1] >> 2) & 0x01; +#line 323 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; +#line 323 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 323 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */", + op[0], op[1], op[2]); + printf (" p = 0x%x,", p); + printf (" sz = 0x%x,", sz); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("mov%s %1, %0"); +#line 324 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); sBWL (sz); SR(rsrc); F("----"); + OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0); + + } + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x28: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_72: + { + /** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */ +#line 327 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int p AU = (op[1] >> 2) & 0x01; +#line 327 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; +#line 327 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 327 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */", + op[0], op[1], op[2]); + printf (" p = 0x%x,", p); + printf (" sz = 0x%x,", sz); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s %1, %0"); +#line 328 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); sBWL (sz); DR(rdst); F("----"); + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + + } + break; + } + break; + case 0x29: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x38: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_73: + { + /** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */ +#line 337 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int p AU = (op[1] >> 2) & 0x01; +#line 337 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = op[1] & 0x03; +#line 337 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 337 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */", + op[0], op[1], op[2]); + printf (" p = 0x%x,", p); + printf (" sz = 0x%x,", sz); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("movu%s %1, %0"); +#line 338 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); uBWL (sz); DR(rdst); F("----"); + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + + /*----------------------------------------------------------------------*/ + /* PUSH/POP */ + + } + break; + } + break; + case 0x39: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */ +#line 662 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 662 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shlr %2, %0"); +#line 663 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F("-SZC"); + + } + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */ +#line 652 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 652 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shar %2, %0"); +#line 653 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F("0SZC"); + + } + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */ +#line 642 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 642 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shll %2, %0"); +#line 643 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F("OSZC"); + + } + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */ +#line 686 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 686 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotr %1, %0"); +#line 687 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rotr); SR(rsrc); DR(rdst); F("-SZC"); + + } + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */ +#line 689 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 689 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("revw %1, %0"); +#line 690 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(revw); SR(rsrc); DR(rdst); + + } + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */ +#line 680 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 680 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotl %1, %0"); +#line 681 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rotl); SR(rsrc); DR(rdst); F("-SZC"); + + } + break; + } + break; + case 0x67: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */ +#line 692 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 692 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("revl %1, %0"); +#line 693 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(revl); SR(rsrc); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* BRANCH */ + + } + break; + } + break; + case 0x68: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_74: + { + /** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */ +#line 932 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int c AU = op[1] & 0x01; +#line 932 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 932 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */", + op[0], op[1], op[2]); + printf (" c = 0x%x,", c); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvtc %1, %0"); +#line 933 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); SR(rsrc); DR(c*16+rdst + 16); + + } + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_74; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_75: + { + /** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */ +#line 935 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int s AU = op[1] & 0x01; +#line 935 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 935 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */", + op[0], op[1], op[2]); + printf (" s = 0x%x,", s); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfc %1, %0"); +#line 936 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); SR((s*16+rsrc) + 16); DR(rdst); + + } + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_75; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_76: + { + /** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */ +#line 683 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int i AU = op[1] & 0x01; +#line 683 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mmmm AU = (op[2] >> 4) & 0x0f; +#line 683 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */", + op[0], op[1], op[2]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotr #%1, %0"); +#line 684 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rotr); SC(i*16+mmmm); DR(rdst); F("-SZC"); + + } + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_76; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_77: + { + /** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */ +#line 677 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int i AU = op[1] & 0x01; +#line 677 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int mmmm AU = (op[2] >> 4) & 0x0f; +#line 677 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */", + op[0], op[1], op[2]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotl #%1, %0"); +#line 678 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(rotl); SC(i*16+mmmm); DR(rdst); F("-SZC"); + + } + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_77; + break; + } + break; + case 0x70: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + op_semantics_78: + { + /** 1111 1101 0111 im00 0010rdst adc #%1, %0 */ +#line 467 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 467 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0010rdst adc #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("adc #%1, %0"); +#line 468 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(adc); SC(IMMex(im)); DR(rdst); F("OSZC"); + + } + break; + case 0x40: + op_semantics_79: + { + /** 1111 1101 0111 im00 0100rdst max #%1, %0 */ +#line 549 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 549 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0100rdst max #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("max #%1, %0"); +#line 550 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(max); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x50: + op_semantics_80: + { + /** 1111 1101 0111 im00 0101rdst min #%1, %0 */ +#line 561 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 561 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0101rdst min #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("min #%1, %0"); +#line 562 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(min); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x60: + op_semantics_81: + { + /** 1111 1101 0111 im00 0110rdst emul #%1, %0 */ +#line 591 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 591 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0110rdst emul #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emul #%1, %0"); +#line 592 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(emul); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x70: + op_semantics_82: + { + /** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */ +#line 603 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 603 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emulu #%1, %0"); +#line 604 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(emulu); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x80: + op_semantics_83: + { + /** 1111 1101 0111 im00 1000rdst div #%1, %0 */ +#line 615 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 615 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1000rdst div #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("div #%1, %0"); +#line 616 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(div); DR(rdst); SC(IMMex(im)); F("O---"); + + } + break; + case 0x90: + op_semantics_84: + { + /** 1111 1101 0111 im00 1001rdst divu #%1, %0 */ +#line 627 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 627 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1001rdst divu #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("divu #%1, %0"); +#line 628 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(divu); DR(rdst); SC(IMMex(im)); F("O---"); + + } + break; + case 0xc0: + op_semantics_85: + { + /** 1111 1101 0111 im00 1100rdst tst #%1, %2 */ +#line 446 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 446 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1100rdst tst #%1, %2 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("tst #%1, %2"); +#line 447 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); SC(IMMex(im)); S2R(rdst); F("-SZ-"); + + } + break; + case 0xd0: + op_semantics_86: + { + /** 1111 1101 0111 im00 1101rdst xor #%1, %0 */ +#line 425 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 425 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1101rdst xor #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xor #%1, %0"); +#line 426 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(xor); SC(IMMex(im)); DR(rdst); F("-SZ-"); + + } + break; + case 0xe0: + op_semantics_87: + { + /** 1111 1101 0111 im00 1110rdst stz #%1, %0 */ +#line 371 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 371 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1110rdst stz #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("stz #%1, %0"); +#line 372 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z); + + } + break; + case 0xf0: + op_semantics_88: + { + /** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */ +#line 374 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 374 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("stnz #%1, %0"); +#line 375 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz); + + /*----------------------------------------------------------------------*/ + /* RTSD */ + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x72: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + { + /** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */ +#line 835 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fsub #%1, %0"); +#line 836 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fsub); DR(rdst); SC(IMM(0)); F("-SZ-"); + + } + break; + case 0x10: + { + /** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */ +#line 829 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fcmp #%1, %0"); +#line 830 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fcmp); DR(rdst); SC(IMM(0)); F("OSZ-"); + + } + break; + case 0x20: + { + /** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */ +#line 823 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fadd #%1, %0"); +#line 824 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fadd); DR(rdst); SC(IMM(0)); F("-SZ-"); + + } + break; + case 0x30: + { + /** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */ +#line 844 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fmul #%1, %0"); +#line 845 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fmul); DR(rdst); SC(IMM(0)); F("-SZ-"); + + } + break; + case 0x40: + { + /** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */ +#line 850 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fdiv #%1, %0"); +#line 851 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(fdiv); DR(rdst); SC(IMM(0)); F("-SZ-"); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x73: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + op_semantics_89: + { + /** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */ +#line 929 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 929 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int crdst AU = op[2] & 0x1f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" crdst = 0x%x\n", crdst); + } + SYNTAX("mvtc #%1, %0"); +#line 930 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mov); SC(IMMex(im)); DR(crdst + 16); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x74: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + goto op_semantics_78; + break; + case 0x40: + goto op_semantics_79; + break; + case 0x50: + goto op_semantics_80; + break; + case 0x60: + goto op_semantics_81; + break; + case 0x70: + goto op_semantics_82; + break; + case 0x80: + goto op_semantics_83; + break; + case 0x90: + goto op_semantics_84; + break; + case 0xc0: + goto op_semantics_85; + break; + case 0xd0: + goto op_semantics_86; + break; + case 0xe0: + goto op_semantics_87; + break; + case 0xf0: + goto op_semantics_88; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x77: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + goto op_semantics_89; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x78: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + goto op_semantics_78; + break; + case 0x40: + goto op_semantics_79; + break; + case 0x50: + goto op_semantics_80; + break; + case 0x60: + goto op_semantics_81; + break; + case 0x70: + goto op_semantics_82; + break; + case 0x80: + goto op_semantics_83; + break; + case 0x90: + goto op_semantics_84; + break; + case 0xc0: + goto op_semantics_85; + break; + case 0xd0: + goto op_semantics_86; + break; + case 0xe0: + goto op_semantics_87; + break; + case 0xf0: + goto op_semantics_88; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7b: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + goto op_semantics_89; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7c: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + goto op_semantics_78; + break; + case 0x40: + goto op_semantics_79; + break; + case 0x50: + goto op_semantics_80; + break; + case 0x60: + goto op_semantics_81; + break; + case 0x70: + goto op_semantics_82; + break; + case 0x80: + goto op_semantics_83; + break; + case 0x90: + goto op_semantics_84; + break; + case 0xc0: + goto op_semantics_85; + break; + case 0xd0: + goto op_semantics_86; + break; + case 0xe0: + goto op_semantics_87; + break; + case 0xf0: + goto op_semantics_88; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7f: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + goto op_semantics_89; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x80: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_90: + { + /** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */ +#line 665 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immmm AU = op[1] & 0x1f; +#line 665 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 665 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */", + op[0], op[1], op[2]); + printf (" immmm = 0x%x,", immmm); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shlr #%2, %1, %0"); +#line 666 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F("-SZC"); + + /*----------------------------------------------------------------------*/ + /* ROTATE */ + + } + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x98: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x99: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0xa0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_91: + { + /** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */ +#line 655 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immmm AU = op[1] & 0x1f; +#line 655 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 655 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */", + op[0], op[1], op[2]); + printf (" immmm = 0x%x,", immmm); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shar #%2, %1, %0"); +#line 656 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F("0SZC"); + + + } + break; + } + break; + case 0xa1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xaa: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xab: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xac: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xad: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xae: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xaf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xba: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbe: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_92: + { + /** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */ +#line 645 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int immmm AU = op[1] & 0x1f; +#line 645 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 645 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */", + op[0], op[1], op[2]); + printf (" immmm = 0x%x,", immmm); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shll #%2, %1, %0"); +#line 646 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F("OSZC"); + + + } + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xde: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + op_semantics_93: + { + /** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */ +#line 911 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bittt AU = op[1] & 0x1f; +#line 911 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int cond AU = (op[2] >> 4) & 0x0f; +#line 911 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */", + op[0], op[1], op[2]); + printf (" bittt = 0x%x,", bittt); + printf (" cond = 0x%x,", cond); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bm%2 #%1, %0%S0"); +#line 912 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* CONTROL REGISTERS */ + + } + break; + case 0xf0: + op_semantics_94: + { + /** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */ +#line 904 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bittt AU = op[1] & 0x1f; +#line 904 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */", + op[0], op[1], op[2]); + printf (" bittt = 0x%x,", bittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bnot #%1, %0"); +#line 905 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst); + + + } + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf0: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf1: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf2: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf3: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf4: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf5: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf6: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf7: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf8: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf9: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfa: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfb: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfc: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfd: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfe: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xff: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xfe: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_95: + { + /** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */ +#line 317 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 317 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int isrc AU = op[1] & 0x0f; +#line 317 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bsrc AU = (op[2] >> 4) & 0x0f; +#line 317 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" isrc = 0x%x,", isrc); + printf (" bsrc = 0x%x,", bsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s %0, [%1, %2]"); +#line 318 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(movbir); sBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----"); + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x12: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x13: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x14: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x15: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x16: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x18: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x19: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x27: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x28: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x29: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_96: + { + /** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */ +#line 314 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 314 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int isrc AU = op[1] & 0x0f; +#line 314 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bsrc AU = (op[2] >> 4) & 0x0f; +#line 314 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" isrc = 0x%x,", isrc); + printf (" bsrc = 0x%x,", bsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s [%1, %2], %0"); +#line 315 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(movbi); sBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----"); + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x58: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x59: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x63: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x67: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x68: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_97: + { + /** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */ +#line 320 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 320 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int isrc AU = op[1] & 0x0f; +#line 320 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int bsrc AU = (op[2] >> 4) & 0x0f; +#line 320 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" isrc = 0x%x,", isrc); + printf (" bsrc = 0x%x,", bsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("movu%s [%1, %2], %0"); +#line 321 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(movbi); uBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----"); + + } + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xde: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xff: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_98: + { + /** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */ +#line 524 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 524 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 524 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("sub %2, %1, %0"); +#line 525 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(sub); DR(rdst); SR(srcb); S2R(srca); F("OSZC"); + + /*----------------------------------------------------------------------*/ + /* SBB */ + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_99: + { + /** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */ +#line 491 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 491 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 491 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("add %2, %1, %0"); +#line 492 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(add); DR(rdst); SR(srcb); S2R(srca); F("OSZC"); + + /*----------------------------------------------------------------------*/ + /* CMP */ + + } + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x27: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x28: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x29: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x30: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_100: + { + /** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */ +#line 585 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 585 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 585 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("mul %2, %1, %0"); +#line 586 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(mul); DR(rdst); SR(srcb); S2R(srca); F("O---"); + + /*----------------------------------------------------------------------*/ + /* EMUL */ + + } + break; + } + break; + case 0x31: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x32: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x33: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x34: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x35: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x36: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x37: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x38: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x39: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_101: + { + /** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */ +#line 401 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 401 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 401 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("and %2, %1, %0"); +#line 402 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(and); DR(rdst); SR(srcb); S2R(srca); F("-SZ-"); + + /*----------------------------------------------------------------------*/ + /* OR */ + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_102: + { + /** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */ +#line 419 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 419 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 419 "/work/sources/binutils/current/opcodes/rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("or %2, %1, %0"); +#line 420 "/work/sources/binutils/current/opcodes/rx-decode.opc" + ID(or); DR(rdst); SR(srcb); S2R(srca); F("-SZ-"); + + /*----------------------------------------------------------------------*/ + /* XOR */ + + } + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x58: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x59: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + default: UNSUPPORTED(); break; + } +#line 975 "/work/sources/binutils/current/opcodes/rx-decode.opc" + + return rx->n_bytes; +} diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc new file mode 100644 index 00000000000..bddf12bfee4 --- /dev/null +++ b/opcodes/rx-decode.opc @@ -0,0 +1,977 @@ +/* -*- c -*- */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include "config.h" +#include "ansidecl.h" +#include "opcode/rx.h" + +#define RX_OPCODE_BIG_ENDIAN 0 + +typedef struct +{ + RX_Opcode_Decoded * rx; + int (* getbyte)(void *); + void * ptr; + unsigned char * op; +} LocalData; + +static int trace = 0; + +#define BSIZE 0 +#define WSIZE 1 +#define LSIZE 2 + +/* These are for when the upper bits are "don't care" or "undefined". */ +static int bwl[] = +{ + RX_Byte, + RX_Word, + RX_Long +}; + +static int sbwl[] = +{ + RX_SByte, + RX_SWord, + RX_Long +}; + +static int ubwl[] = +{ + RX_UByte, + RX_UWord, + RX_Long +}; + +static int memex[] = +{ + RX_SByte, + RX_SWord, + RX_Long, + RX_UWord +}; + +#define ID(x) rx->id = RXO_##x +#define OP(n,t,r,a) (rx->op[n].type = t, \ + rx->op[n].reg = r, \ + rx->op[n].addend = a ) +#define OPs(n,t,r,a,s) (OP (n,t,r,a), \ + rx->op[n].size = s ) + +/* This is for the BWL and BW bitfields. */ +static int SCALE[] = { 1, 2, 4 }; +/* This is for the prefix size enum. */ +static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 }; + +static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0, + 16, 17, 0, 0, 0, 0, 0, 0 }; + +static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 }; + +/* + *C a constant (immediate) c + *R A register + *I Register indirect, no offset + *Is Register indirect, with offset + *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code + *P standard displacement: type (r,[r]), reg, assumes UByte + *Pm memex displacement: type (r,[r]), reg, memex code + *cc condition code. */ + +#define DC(c) OP (0, RX_Operand_Immediate, 0, c) +#define DR(r) OP (0, RX_Operand_Register, r, 0) +#define DI(r,a) OP (0, RX_Operand_Indirect, r, a) +#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld); +#define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0) + +#define SC(i) OP (1, RX_Operand_Immediate, 0, i) +#define SR(r) OP (1, RX_Operand_Register, r, 0) +#define SI(r,a) OP (1, RX_Operand_Indirect, r, a) +#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld); +#define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1); +#define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m]; +#define Scc(cc) OP (1, RX_Operand_Condition, cc, 0) + +#define S2C(i) OP (2, RX_Operand_Immediate, 0, i) +#define S2R(r) OP (2, RX_Operand_Register, r, 0) +#define S2I(r,a) OP (2, RX_Operand_Indirect, r, a) +#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld); +#define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2); +#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m]; +#define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0) + +#define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz] +#define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz] +#define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz] +#define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long; + +#define F(f) store_flags(rx, f) + +#define AU ATTRIBUTE_UNUSED +#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr)) + +#define SYNTAX(x) rx->syntax = x + +#define UNSUPPORTED() \ + rx->syntax = "*unknown*" + +#define IMM(sf) immediate (sf, 0, ld) +#define IMMex(sf) immediate (sf, 1, ld) + +static int +immediate (int sfield, int ex, LocalData * ld) +{ + unsigned long i = 0, j; + + switch (sfield) + { +#define B ((unsigned long) GETBYTE()) + case 0: +#if RX_OPCODE_BIG_ENDIAN + i = B; + if (ex && (i & 0x80)) + i -= 0x100; + i <<= 24; + i |= B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; + j = B; + if (ex && (j & 0x80)) + j -= 0x100; + i |= j << 24; +#endif + break; + case 3: +#if RX_OPCODE_BIG_ENDIAN + i = B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; +#endif + if (ex && (i & 0x800000)) + i -= 0x1000000; + break; + case 2: +#if RX_OPCODE_BIG_ENDIAN + i |= B << 8; + i |= B; +#else + i |= B; + i |= B << 8; +#endif + if (ex && (i & 0x8000)) + i -= 0x10000; + break; + case 1: + i |= B; + if (ex && (i & 0x80)) + i -= 0x100; + break; + default: + abort(); + } + return i; +} + +static void +rx_disp (int n, int type, int reg, int size, LocalData * ld) +{ + int disp; + + ld->rx->op[n].reg = reg; + switch (type) + { + case 3: + ld->rx->op[n].type = RX_Operand_Register; + break; + case 0: + ld->rx->op[n].type = RX_Operand_Indirect; + ld->rx->op[n].addend = 0; + break; + case 1: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + case 2: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); +#if RX_OPCODE_BIG_ENDIAN + disp = disp * 256 + GETBYTE (); +#else + disp = disp + GETBYTE () * 256; +#endif + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + default: + abort (); + } +} + +/* The syntax is "OSZC" where each character is one of the following: + - = flag unchanged + 0 = flag cleared + 1 = flag set + ? = flag undefined + x = flag set (any letter will do, use it for hints :). */ + +static void +store_flags (RX_Opcode_Decoded * rx, char * str) +{ + int i, mask; + rx->flags_0 = 0; + rx->flags_1 = 0; + rx->flags_s = 0; + + for (i = 0; i < 4; i++) + { + mask = 8 >> i; + switch (str[i]) + { + case 0: + abort (); + case '-': + break; + case '0': + rx->flags_0 |= mask; + break; + case '1': + rx->flags_1 |= mask; + break; + case '?': + break; + default: + rx->flags_0 |= mask; + rx->flags_s |= mask; + break; + } + } +} + +int +rx_decode_opcode (unsigned long pc AU, + RX_Opcode_Decoded * rx, + int (* getbyte)(void *), + void * ptr) +{ + LocalData lds, * ld = &lds; + unsigned char op[20] = {0}; + + lds.rx = rx; + lds.getbyte = getbyte; + lds.ptr = ptr; + lds.op = op; + + memset (rx, 0, sizeof (*rx)); + BWL(LSIZE); + +/** VARY sz 00 01 10 */ + +/*----------------------------------------------------------------------*/ +/* MOV */ + +/** 0111 0101 0100 rdst mov%s #%1, %0 */ + ID(mov); DR(rdst); SC(IMM (1)); F("----"); + +/** 1111 10sd rdst im sz mov%s #%1, %0 */ + ID(mov); sBWL (sz); DD(sd, rdst, sz); SC(IMMex(im)); F("----"); + +/** 0110 0110 immm rdst mov%s #%1, %0 */ + ID(mov); DR(rdst); SC(immm); F("----"); + +/** 0011 11sz d dst sppp mov%s #%1, %0 */ + ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F("----"); + +/** 11sz sd ss rsrc rdst mov%s %1, %0 */ + ID(mov); sBWL(sz); F("----"); + if ((ss == 3) && (sd != 3)) + { + SD(ss, rdst, sz); DD(sd, rsrc, sz); + } + else + { + SD(ss, rsrc, sz); DD(sd, rdst, sz); + } + +/** 10sz 1dsp a src b dst mov%s %1, %0 */ + ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F("----"); + +/** 10sz 0dsp a dst b src mov%s %1, %0 */ + ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F("----"); + +/** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */ + ID(movbi); sBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----"); + +/** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */ + ID(movbir); sBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----"); + +/** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */ + ID(movbi); uBWL(sz); DR(rdst); SR(isrc); S2R(bsrc); F("----"); + +/** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */ + ID(mov); sBWL (sz); SR(rsrc); F("----"); + OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0); + +/** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */ + ID(mov); sBWL (sz); DR(rdst); F("----"); + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + +/** 1011 w dsp a src b dst movu%s %1, %0 */ + ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F("----"); + +/** 0101 1 s ss rsrc rdst movu%s %1, %0 */ + ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F("----"); + +/** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */ + ID(mov); uBWL (sz); DR(rdst); F("----"); + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + +/*----------------------------------------------------------------------*/ +/* PUSH/POP */ + +/** 0110 1111 dsta dstb popm %1-%2 */ + ID(popm); SR(dsta); S2R(dstb); F("----"); + +/** 0110 1110 dsta dstb pushm %1-%2 */ + ID(pushm); SR(dsta); S2R(dstb); F("----"); + +/** 0111 1110 1011 rdst pop %0 */ + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F("----"); + +/** 0111 1110 10sz rsrc push%s %1 */ + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F("----"); + +/** 1111 01ss rsrc 10sz push%s %1 */ + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F("----"); + +/*----------------------------------------------------------------------*/ +/* XCHG */ + +/** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */ + ID(xchg); DR(rdst); SP(ss, rsrc); + +/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */ + ID(xchg); DR(rdst); SPm(ss, rsrc, mx); + +/*----------------------------------------------------------------------*/ +/* STZ/STNZ */ + +/** 1111 1101 0111 im00 1110rdst stz #%1, %0 */ + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z); + +/** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */ + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz); + +/*----------------------------------------------------------------------*/ +/* RTSD */ + +/** 0110 0111 rtsd #%1 */ + ID(rtsd); SC(IMM(1) * 4); + +/** 0011 1111 rega regb rtsd #%1, %2-%0 */ + ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb); + +/*----------------------------------------------------------------------*/ +/* AND */ + +/** 0110 0100 immm rdst and #%1, %0 */ + ID(and); SC(immm); DR(rdst); F("-SZ-"); + +/** 0111 01im 0010 rdst and #%1, %0 */ + ID(and); SC(IMMex(im)); DR(rdst); F("-SZ-"); + +/** 0101 00ss rsrc rdst and %1%S1, %0 */ + ID(and); SP(ss, rsrc); DR(rdst); F("-SZ-"); + +/** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */ + ID(and); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-"); + +/** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */ + ID(and); DR(rdst); SR(srcb); S2R(srca); F("-SZ-"); + +/*----------------------------------------------------------------------*/ +/* OR */ + +/** 0110 0101 immm rdst or #%1, %0 */ + ID(or); SC(immm); DR(rdst); F("-SZ-"); + +/** 0111 01im 0011 rdst or #%1, %0 */ + ID(or); SC(IMMex(im)); DR(rdst); F("-SZ-"); + +/** 0101 01ss rsrc rdst or %1%S1, %0 */ + ID(or); SP(ss, rsrc); DR(rdst); F("-SZ-"); + +/** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */ + ID(or); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-"); + +/** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */ + ID(or); DR(rdst); SR(srcb); S2R(srca); F("-SZ-"); + +/*----------------------------------------------------------------------*/ +/* XOR */ + +/** 1111 1101 0111 im00 1101rdst xor #%1, %0 */ + ID(xor); SC(IMMex(im)); DR(rdst); F("-SZ-"); + +/** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */ + ID(xor); SP(ss, rsrc); DR(rdst); F("-SZ-"); + +/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */ + ID(xor); SPm(ss, rsrc, mx); DR(rdst); F("-SZ-"); + +/*----------------------------------------------------------------------*/ +/* NOT */ + +/** 0111 1110 0000 rdst not %0 */ + ID(xor); DR(rdst); SR(rdst); S2C(~0); F("-SZ-"); + +/** 1111 1100 0011 1011 rsrc rdst not %1, %0 */ + ID(xor); DR(rdst); SR(rsrc); S2C(~0); F("-SZ-"); + +/*----------------------------------------------------------------------*/ +/* TST */ + +/** 1111 1101 0111 im00 1100rdst tst #%1, %2 */ + ID(and); SC(IMMex(im)); S2R(rdst); F("-SZ-"); + +/** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */ + ID(and); SP(ss, rsrc); S2R(rdst); F("-SZ-"); + +/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */ + ID(and); SPm(ss, rsrc, mx); S2R(rdst); F("-SZ-"); + +/*----------------------------------------------------------------------*/ +/* NEG */ + +/** 0111 1110 0001 rdst neg %0 */ + ID(sub); DR(rdst); SC(0); S2R(rdst); F("OSZC"); + +/** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */ + ID(sub); DR(rdst); SC(0); S2R(rsrc); F("OSZC"); + +/*----------------------------------------------------------------------*/ +/* ADC */ + +/** 1111 1101 0111 im00 0010rdst adc #%1, %0 */ + ID(adc); SC(IMMex(im)); DR(rdst); F("OSZC"); + +/** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */ + ID(adc); SR(rsrc); DR(rdst); F("OSZC"); + +/** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */ + ID(adc); SPm(ss, rsrc, 2); DR(rdst); F("OSZC"); + +/*----------------------------------------------------------------------*/ +/* ADD */ + +/** 0110 0010 immm rdst add #%1, %0 */ + ID(add); SC(immm); DR(rdst); F("OSZC"); + +/** 0100 10ss rsrc rdst add %1%S1, %0 */ + ID(add); SP(ss, rsrc); DR(rdst); F("OSZC"); + +/** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */ + ID(add); SPm(ss, rsrc, mx); DR(rdst); F("OSZC"); + +/** 0111 00im rsrc rdst add #%1, %2, %0 */ + ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F("OSZC"); + +/** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */ + ID(add); DR(rdst); SR(srcb); S2R(srca); F("OSZC"); + +/*----------------------------------------------------------------------*/ +/* CMP */ + +/** 0110 0001 immm rdst cmp #%2, %1 */ + ID(sub); S2C(immm); SR(rdst); F("OSZC"); + +/** 0111 01im 0000 rsrc cmp #%2, %1%S1 */ + ID(sub); SR(rsrc); S2C(IMMex(im)); F("OSZC"); + +/** 0111 0101 0101 rsrc cmp #%2, %1 */ + ID(sub); SR(rsrc); S2C(IMM(1)); F("OSZC"); + +/** 0100 01ss rsrc rdst cmp %2%S2, %1 */ + ID(sub); S2P(ss, rsrc); SR(rdst); F("OSZC"); + +/** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */ + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F("OSZC"); + +/*----------------------------------------------------------------------*/ +/* SUB */ + +/** 0110 0000 immm rdst sub #%2, %0 */ + ID(sub); S2C(immm); SR(rdst); DR(rdst); F("OSZC"); + +/** 0100 00ss rsrc rdst sub %2%S2, %1 */ + ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F("OSZC"); + +/** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */ + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F("OSZC"); + +/** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */ + ID(sub); DR(rdst); SR(srcb); S2R(srca); F("OSZC"); + +/*----------------------------------------------------------------------*/ +/* SBB */ + +/** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */ + ID(sbb); SR (rsrc); DR(rdst); F("OSZC"); + + /* FIXME: only supports .L */ +/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */ + ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F("OSZC"); + +/*----------------------------------------------------------------------*/ +/* ABS */ + +/** 0111 1110 0010 rdst abs %0 */ + ID(abs); DR(rdst); SR(rdst); F("OSZ-"); + +/** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */ + ID(abs); DR(rdst); SR(rsrc); F("OSZ-"); + +/*----------------------------------------------------------------------*/ +/* MAX */ + +/** 1111 1101 0111 im00 0100rdst max #%1, %0 */ + ID(max); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */ + ID(max); SP(ss, rsrc); DR(rdst); + +/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */ + ID(max); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* MIN */ + +/** 1111 1101 0111 im00 0101rdst min #%1, %0 */ + ID(min); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */ + ID(min); SP(ss, rsrc); DR(rdst); + +/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */ + ID(min); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* MUL */ + +/** 0110 0011 immm rdst mul #%1, %0 */ + ID(mul); DR(rdst); SC(immm); F("O---"); + +/** 0111 01im 0001rdst mul #%1, %0 */ + ID(mul); DR(rdst); SC(IMMex(im)); F("O---"); + +/** 0100 11ss rsrc rdst mul %1%S1, %0 */ + ID(mul); SP(ss, rsrc); DR(rdst); F("O---"); + +/** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */ + ID(mul); SPm(ss, rsrc, mx); DR(rdst); F("O---"); + +/** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */ + ID(mul); DR(rdst); SR(srcb); S2R(srca); F("O---"); + +/*----------------------------------------------------------------------*/ +/* EMUL */ + +/** 1111 1101 0111 im00 0110rdst emul #%1, %0 */ + ID(emul); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */ + ID(emul); SP(ss, rsrc); DR(rdst); + +/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */ + ID(emul); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* EMULU */ + +/** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */ + ID(emulu); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */ + ID(emulu); SP(ss, rsrc); DR(rdst); + +/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */ + ID(emulu); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* DIV */ + +/** 1111 1101 0111 im00 1000rdst div #%1, %0 */ + ID(div); DR(rdst); SC(IMMex(im)); F("O---"); + +/** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */ + ID(div); SP(ss, rsrc); DR(rdst); F("O---"); + +/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */ + ID(div); SPm(ss, rsrc, mx); DR(rdst); F("O---"); + +/*----------------------------------------------------------------------*/ +/* DIVU */ + +/** 1111 1101 0111 im00 1001rdst divu #%1, %0 */ + ID(divu); DR(rdst); SC(IMMex(im)); F("O---"); + +/** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */ + ID(divu); SP(ss, rsrc); DR(rdst); F("O---"); + +/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */ + ID(divu); SPm(ss, rsrc, mx); DR(rdst); F("O---"); + +/*----------------------------------------------------------------------*/ +/* SHIFT */ + +/** 0110 110i mmmm rdst shll #%2, %0 */ + ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("OSZC"); + +/** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */ + ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F("OSZC"); + +/** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */ + ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F("OSZC"); + + +/** 0110 101i mmmm rdst shar #%2, %0 */ + ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("0SZC"); + +/** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */ + ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F("0SZC"); + +/** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */ + ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F("0SZC"); + + +/** 0110 100i mmmm rdst shlr #%2, %0 */ + ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F("-SZC"); + +/** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */ + ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F("-SZC"); + +/** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */ + ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F("-SZC"); + +/*----------------------------------------------------------------------*/ +/* ROTATE */ + +/** 0111 1110 0101 rdst rolc %0 */ + ID(rolc); DR(rdst); F("-SZC"); + +/** 0111 1110 0100 rdst rorc %0 */ + ID(rorc); DR(rdst); F("-SZC"); + +/** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */ + ID(rotl); SC(i*16+mmmm); DR(rdst); F("-SZC"); + +/** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */ + ID(rotl); SR(rsrc); DR(rdst); F("-SZC"); + +/** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */ + ID(rotr); SC(i*16+mmmm); DR(rdst); F("-SZC"); + +/** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */ + ID(rotr); SR(rsrc); DR(rdst); F("-SZC"); + +/** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */ + ID(revw); SR(rsrc); DR(rdst); + +/** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */ + ID(revl); SR(rsrc); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* BRANCH */ + +/** 0001 n dsp b%1.s %a0 */ + ID(branch); Scc(n); DC(pc + dsp3map[dsp]); + +/** 0010 cond b%1.b %a0 */ + ID(branch); Scc(cond); DC(pc + IMMex (1)); + +/** 0011 101c b%1.w %a0 */ + ID(branch); Scc(c); DC(pc + IMMex (2)); + + +/** 0000 1dsp bra.s %a0 */ + ID(branch); Scc(RXC_always); DC(pc + dsp3map[dsp]); + +/** 0010 1110 bra.b %a0 */ + ID(branch); Scc(RXC_always); DC(pc + IMMex(1)); + +/** 0011 1000 bra.w %a0 */ + ID(branch); Scc(RXC_always); DC(pc + IMMex(2)); + +/** 0000 0100 bra.a %a0 */ + ID(branch); Scc(RXC_always); DC(pc + IMMex(3)); + +/** 0111 1111 0100 rsrc bra.l %0 */ + ID(branchrel); Scc(RXC_always); DR(rsrc); + + +/** 0111 1111 0000 rsrc jmp %0 */ + ID(branch); Scc(RXC_always); DR(rsrc); + +/** 0111 1111 0001 rsrc jsr %0 */ + ID(jsr); DR(rsrc); + +/** 0011 1001 bsr.w %a0 */ + ID(jsr); DC(pc + IMMex(2)); + +/** 0000 0101 bsr.a %a0 */ + ID(jsr); DC(pc + IMMex(3)); + +/** 0111 1111 0101 rsrc bsr.l %0 */ + ID(jsrrel); DR(rsrc); + +/** 0000 0010 rts */ + ID(rts); + +/*----------------------------------------------------------------------*/ +/* NOP */ + +/** 0000 0011 nop */ + ID(nop); + +/*----------------------------------------------------------------------*/ +/* STRING FUNCTIONS */ + +/** 0111 1111 1000 0011 scmpu */ + ID(scmpu); F("--ZC"); + +/** 0111 1111 1000 0111 smovu */ + ID(smovu); + +/** 0111 1111 1000 1011 smovb */ + ID(smovb); + +/** 0111 1111 1000 00sz suntil%s */ + ID(suntil); BWL(sz); F("OSZC"); + +/** 0111 1111 1000 01sz swhile%s */ + ID(swhile); BWL(sz); F("OSZC"); + +/** 0111 1111 1000 1111 smovf */ + ID(smovf); + +/** 0111 1111 1000 10sz sstr%s */ + ID(sstr); BWL(sz); + +/*----------------------------------------------------------------------*/ +/* RMPA */ + +/** 0111 1111 1000 11sz rmpa%s */ + ID(rmpa); BWL(sz); F("OS--"); + +/*----------------------------------------------------------------------*/ +/* HI/LO stuff */ + +/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */ + ID(mulhi); SR(srca); S2R(srcb); F("----"); + +/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */ + ID(mullo); SR(srca); S2R(srcb); F("----"); + +/** 1111 1101 0000 0100 srca srcb machi %1, %2 */ + ID(machi); SR(srca); S2R(srcb); F("----"); + +/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */ + ID(maclo); SR(srca); S2R(srcb); F("----"); + +/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */ + ID(mvtachi); SR(rsrc); F("----"); + +/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */ + ID(mvtaclo); SR(rsrc); F("----"); + +/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */ + ID(mvfachi); DR(rdst); F("----"); + +/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */ + ID(mvfacmi); DR(rdst); F("----"); + +/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */ + ID(mvfaclo); DR(rdst); F("----"); + +/** 1111 1101 0001 1000 000i 0000 racw #%1 */ + ID(racw); SC(i+1); F("----"); + +/*----------------------------------------------------------------------*/ +/* SAT */ + +/** 0111 1110 0011 rdst sat %0 */ + ID(sat); DR (rdst); + +/** 0111 1111 1001 0011 satr */ + ID(satr); + +/*----------------------------------------------------------------------*/ +/* FLOAT */ + +/** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */ + ID(fadd); DR(rdst); SC(IMM(0)); F("-SZ-"); + +/** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */ + ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + +/** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */ + ID(fcmp); DR(rdst); SC(IMM(0)); F("OSZ-"); + +/** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */ + ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F("OSZ-"); + +/** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */ + ID(fsub); DR(rdst); SC(IMM(0)); F("-SZ-"); + +/** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */ + ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + +/** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */ + ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + +/** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */ + ID(fmul); DR(rdst); SC(IMM(0)); F("-SZ-"); + +/** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */ + ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + +/** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */ + ID(fdiv); DR(rdst); SC(IMM(0)); F("-SZ-"); + +/** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */ + ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + +/** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */ + ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F("-SZ-"); + +/** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */ + ID(itof); DR (rdst); SP(sd, rsrc); F("-SZ-"); + +/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */ + ID(itof); DR (rdst); SPm(sd, rsrc, mx); F("-SZ-"); + +/*----------------------------------------------------------------------*/ +/* BIT OPS */ + +/** 1111 00sd rdst 0bit bset #%1, %0%S0 */ + ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F("----"); + +/** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */ + ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F("----"); + +/** 0111 100b ittt rdst bset #%1, %0 */ + ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F("----"); + + +/** 1111 00sd rdst 1bit bclr #%1, %0%S0 */ + ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F("----"); + +/** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */ + ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F("----"); + +/** 0111 101b ittt rdst bclr #%1, %0 */ + ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F("----"); + + +/** 1111 01sd rdst 0bit btst #%2, %1%S1 */ + ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F("--ZC"); + +/** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */ + ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F("--ZC"); + +/** 0111 110b ittt rdst btst #%2, %1 */ + ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F("--ZC"); + + +/** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */ + ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); + +/** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */ + ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); + +/** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */ + ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst); + + +/** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */ + ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE); + +/** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */ + ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* CONTROL REGISTERS */ + +/** 0111 1111 1011 rdst clrpsw %0 */ + ID(clrpsw); DF(rdst); + +/** 0111 1111 1010 rdst setpsw %0 */ + ID(setpsw); DF(rdst); + +/** 0111 1110 111 crdst popc %0 */ + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16); + +/** 0111 1110 110 crsrc pushc %1 */ + ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16); + +/** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */ + ID(mov); SC(IMMex(im)); DR(crdst + 16); + +/** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */ + ID(mov); SR(rsrc); DR(c*16+rdst + 16); + +/** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */ + ID(mov); SR((s*16+rsrc) + 16); DR(rdst); + +/*?* 1111 1101 1111 1010 01cp rsrc mvtcp #%2, %1, #%0 */ + ID(mvtcp); S2C(cp); SR(rsrc); DC (IMM (WSIZE)); + +/*?* 1111 1101 1111 1011 01cp rdst mvfcp #%2, %0, #%1 */ + ID(mvfcp); S2C(cp); DR(rdst); SC (IMM (WSIZE)); + +/*?* 1111 1101 1111 1001 01cp 0000 opecp #%2, #%1 */ + ID(opecp); S2C(cp); SC (IMM (WSIZE)); + +/*----------------------------------------------------------------------*/ +/* INTERRUPTS */ + +/** 0111 1111 1001 0100 rtfi */ + ID(rtfi); + +/** 0111 1111 1001 0101 rte */ + ID(rte); + +/** 0000 0000 brk */ + ID(brk); + +/** 0000 0001 dbt */ + ID(dbt); + +/** 0111 0101 0110 0000 int #%1 */ + ID(int); SC(IMM(1)); + +/** 0111 1111 1001 0110 wait */ + ID(wait); + +/*----------------------------------------------------------------------*/ +/* SCcnd */ + +/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */ + ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond); + +/** */ + + return rx->n_bytes; +} diff --git a/opcodes/rx-dis.c b/opcodes/rx-dis.c new file mode 100644 index 00000000000..3413b1d8ec9 --- /dev/null +++ b/opcodes/rx-dis.c @@ -0,0 +1,199 @@ +/* Disassembler code for Renesas RX. + Copyright 2008, 2009 Free Software Foundation, Inc. + Contributed by Red Hat. + Written by DJ Delorie. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include <stdio.h> + +#include "bfd.h" +#include "dis-asm.h" +#include "opcode/rx.h" + +typedef struct +{ + bfd_vma pc; + disassemble_info * dis; +} RX_Data; + +static int +rx_get_byte (void * vdata) +{ + bfd_byte buf[1]; + RX_Data *rx_data = (RX_Data *) vdata; + + rx_data->dis->read_memory_func (rx_data->pc, + buf, + 1, + rx_data->dis); + + rx_data->pc ++; + return buf[0]; +} + +static char const * size_names[] = +{ + "", ".b", ".ub", ".b", ".w", ".uw", ".w", ".a", ".l" +}; + +static char const * opsize_names[] = +{ + "", ".b", ".b", ".b", ".w", ".w", ".w", ".a", ".l" +}; + +static char const * register_names[] = +{ + /* general registers */ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + /* control register */ + "psw", "pc", "usp", "fpsw", "cpen", "", "", "wr", + "bpsw", "bpc", "isp", "fintv", "intb", "", "", "", + "pbp", "pben", "", "", "", "", "", "", + "bbpsw", "bbpc", "", "", "", "", "", "" +}; + +static char const * condition_names[] = +{ + /* condition codes */ + "eq", "ne", "c", "nc", "gtu", "leu", "pz", "n", + "ge", "lt", "gt", "le", "o", "no", "always", "never" +}; + +static const char * flag_names[] = +{ + "c", "z", "s", "o", "", "", "", "", + "", "", "", "", "", "", "", "", + "i", "u", "", "", "", "", "", "" + "", "", "", "", "", "", "", "", +}; + +int +print_insn_rx (bfd_vma addr, disassemble_info * dis) +{ + int rv; + RX_Data rx_data; + RX_Opcode_Decoded opcode; + const char * s; + + rx_data.pc = addr; + rx_data.dis = dis; + + rv = rx_decode_opcode (addr, &opcode, rx_get_byte, &rx_data); + + dis->bytes_per_line = 10; + +#define PR (dis->fprintf_func) +#define PS (dis->stream) +#define PC(c) PR (PS, "%c", c) + + for (s = opcode.syntax; *s; s++) + { + if (*s != '%') + { + PC (*s); + } + else + { + RX_Opcode_Operand * oper; + int do_size = 0; + int do_hex = 0; + int do_addr = 0; + + s ++; + + if (*s == 'S') + { + do_size = 1; + s++; + } + if (*s == 'x') + { + do_hex = 1; + s++; + } + if (*s == 'a') + { + do_addr = 1; + s++; + } + + switch (*s) + { + case '%': + PC ('%'); + break; + + case 's': + PR (PS, "%s", opsize_names[opcode.size]); + break; + + case '0': + case '1': + case '2': + oper = opcode.op + *s - '0'; + if (do_size) + { + if (oper->type == RX_Operand_Indirect) + PR (PS, "%s", size_names[oper->size]); + } + else + switch (oper->type) + { + case RX_Operand_Immediate: + if (do_addr) + dis->print_address_func (oper->addend, dis); + else if (do_hex + || oper->addend > 999 + || oper->addend < -999) + PR (PS, "%#x", oper->addend); + else + PR (PS, "%d", oper->addend); + break; + case RX_Operand_Register: + PR (PS, "%s", register_names[oper->reg]); + break; + case RX_Operand_Indirect: + if (oper->addend) + PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]); + else + PR (PS, "[%s]", register_names[oper->reg]); + break; + case RX_Operand_Postinc: + PR (PS, "[%s+]", register_names[oper->reg]); + break; + case RX_Operand_Predec: + PR (PS, "[-%s]", register_names[oper->reg]); + break; + case RX_Operand_Condition: + PR (PS, "%s", condition_names[oper->reg]); + break; + case RX_Operand_Flag: + PR (PS, "%s", flag_names[oper->reg]); + break; + default: + PR (PS, "[???]"); + break; + } + } + } + } + + return rv; +} |