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| author |   Michał Górny <mgorny@gentoo.org> | 2019-08-12 14:31:43 +0200 |
|---|---|---|
| committer | Michał Górny <mgorny@gentoo.org> | 2019-08-12 15:20:45 +0200 |
| commit | a120f14b4606aacc3f2e65f764ee48e14bfa6138 (patch) | |
| tree | ed3fd2f80d989d0edc884bdd4b686df00ea88009 | |
| parent | sys-devel/llvm: RISCV is no longer exp. in 9.0+ (diff) | |
| download | gentoo-a120f14b4606aacc3f2e65f764ee48e14bfa6138.tar.gz gentoo-a120f14b4606aacc3f2e65f764ee48e14bfa6138.tar.bz2 gentoo-a120f14b4606aacc3f2e65f764ee48e14bfa6138.zip | |
dev-ml/llvm-ocaml: RISCV is no longer exp. in 9.0+
Closes: https://bugs.gentoo.org/691816
Signed-off-by: Michał Górny <mgorny@gentoo.org>
| -rw-r--r-- | dev-ml/llvm-ocaml/llvm-ocaml-10.0.0.9999.ebuild | 4 | ||||
| -rw-r--r-- | dev-ml/llvm-ocaml/llvm-ocaml-9.0.0.9999.ebuild | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/dev-ml/llvm-ocaml/llvm-ocaml-10.0.0.9999.ebuild b/dev-ml/llvm-ocaml/llvm-ocaml-10.0.0.9999.ebuild index e354e4765340..9b4fa23f1388 100644 --- a/dev-ml/llvm-ocaml/llvm-ocaml-10.0.0.9999.ebuild +++ b/dev-ml/llvm-ocaml/llvm-ocaml-10.0.0.9999.ebuild @@ -17,9 +17,9 @@ EGIT_REPO_URI="https://git.llvm.org/git/llvm.git https://github.com/llvm-mirror/llvm.git" # Keep in sync with sys-devel/llvm -ALL_LLVM_EXPERIMENTAL_TARGETS=( AVR Nios2 RISCV ) +ALL_LLVM_EXPERIMENTAL_TARGETS=( AVR Nios2 ) ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 - NVPTX PowerPC Sparc SystemZ WebAssembly X86 XCore + NVPTX PowerPC RISCV Sparc SystemZ WebAssembly X86 XCore "${ALL_LLVM_EXPERIMENTAL_TARGETS[@]}" ) ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?} diff --git a/dev-ml/llvm-ocaml/llvm-ocaml-9.0.0.9999.ebuild b/dev-ml/llvm-ocaml/llvm-ocaml-9.0.0.9999.ebuild index 28e3cb65696c..973c0c74dc5c 100644 --- a/dev-ml/llvm-ocaml/llvm-ocaml-9.0.0.9999.ebuild +++ b/dev-ml/llvm-ocaml/llvm-ocaml-9.0.0.9999.ebuild @@ -19,7 +19,7 @@ EGIT_BRANCH="release_90" # Keep in sync with sys-devel/llvm ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 - NVPTX PowerPC Sparc SystemZ WebAssembly X86 XCore ) + NVPTX PowerPC RISCV Sparc SystemZ WebAssembly X86 XCore ) ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?} |