new version, again

2 files changed, 161 insertions, 0 deletions

diff --git a/app-emulation/qemu/files/digest-qemu-0.5.4 b/app-emulation/qemu/files/digest-qemu-0.5.4
new file mode 100644
index 000000000000..2fd872f8bd91
--- /dev/null
+++ b/app-emulation/qemu/files/digest-qemu-0.5.4
@@ -0,0 +1 @@
+MD5 4880e253de75ebaf0673428388232797 qemu-0.5.4.tar.gz 748094
diff --git a/app-emulation/qemu/files/qemu-0.5.4-jocelyn-mayer-ppc.patch b/app-emulation/qemu/files/qemu-0.5.4-jocelyn-mayer-ppc.patch
new file mode 100644
index 000000000000..9f72fb1b9efb
--- /dev/null
+++ b/app-emulation/qemu/files/qemu-0.5.4-jocelyn-mayer-ppc.patch
@@ -0,0 +1,160 @@
+Index: hw/vga.c
+===================================================================
+RCS file: /cvsroot/qemu/qemu/hw/vga.c,v
+retrieving revision 1.23
+diff -u -d -w -B -b -d -p -r1.23 vga.c
+--- hw/vga.c	26 Apr 2004 19:44:02 -0000	1.23
++++ hw/vga.c	28 Apr 2004 00:03:16 -0000
+@@ -33,6 +33,16 @@
+ /* S3 VGA is deprecated - another graphic card will be emulated */
+ //#define CONFIG_S3VGA
+ 
++/* XXX: should go in target definition */
++#if defined (TARGET_I386)
++#define ISA_MEM_BASE (target_phys_addr_t)(0x00000000)
++#elif defined (TARGET_PPC)
++/* Note: this true only for PREP platform */
++#define ISA_MEM_BASE (target_phys_addr_t)(0xc0000000)
++#else
++#error "Please define IO memory base for the emulated target"
++#endif
++
+ #define MSR_COLOR_EMULATION 0x01
+ #define MSR_PAGE_SELECT     0x20
+ 
+@@ -92,7 +102,7 @@ typedef struct VGAState {
+     uint8_t dac_write_index;
+     uint8_t dac_cache[3]; /* used when writing */
+     uint8_t palette[768];
+-    int32_t bank_offset;
++    target_phys_addr_t bank_offset;
+ #ifdef CONFIG_BOCHS_VBE
+     uint16_t vbe_index;
+     uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
+@@ -549,7 +559,8 @@ static void vbe_ioport_write(void *opaqu
+         case VBE_DISPI_INDEX_BANK:
+             val &= s->vbe_bank_mask;
+             s->vbe_regs[s->vbe_index] = val;
+-            s->bank_offset = (val << 16) - 0xa0000;
++
++            s->bank_offset = -(val << 16) - (0xa0000 + ISA_MEM_BASE);
+             break;
+         case VBE_DISPI_INDEX_ENABLE:
+             if (val & VBE_DISPI_ENABLED) {
+@@ -603,7 +614,7 @@ static void vbe_ioport_write(void *opaqu
+                 s->vbe_regs[s->vbe_index] = val;
+             } else {
+                 /* XXX: the bios should do that */
+-                s->bank_offset = -0xa0000;
++                s->bank_offset = -(0xa0000 + ISA_MEM_BASE);
+             }
+             break;
+         case VBE_DISPI_INDEX_VIRT_WIDTH:
+@@ -658,22 +669,22 @@ static uint32_t vga_mem_readb(target_phy
+     memory_map_mode = (s->gr[6] >> 2) & 3;
+     switch(memory_map_mode) {
+     case 0:
+-        addr -= 0xa0000;
++        addr -= 0xa0000 + ISA_MEM_BASE;
+         break;
+     case 1:
+-        if (addr >= 0xb0000)
++        if (addr >= 0xb0000 + ISA_MEM_BASE)
+             return 0xff;
+         addr += s->bank_offset;
+         break;
+     case 2:
+-        addr -= 0xb0000;
+-        if (addr >= 0x8000)
++        addr -= 0xb0000 + ISA_MEM_BASE;
++        if (addr >= 0x8000 + ISA_MEM_BASE)
+             return 0xff;
+         break;
+     default:
+     case 3:
+-        addr -= 0xb8000;
+-        if (addr >= 0x8000)
++        addr -= 0xb8000 + ISA_MEM_BASE;
++        if (addr >= 0x8000 + ISA_MEM_BASE)
+             return 0xff;
+         break;
+     }
+@@ -736,22 +747,22 @@ static void vga_mem_writeb(target_phys_a
+     memory_map_mode = (s->gr[6] >> 2) & 3;
+     switch(memory_map_mode) {
+     case 0:
+-        addr -= 0xa0000;
++        addr -= 0xa0000 + ISA_MEM_BASE;
+         break;
+     case 1:
+-        if (addr >= 0xb0000)
++        if (addr >= 0xb0000 + ISA_MEM_BASE)
+             return;
+         addr += s->bank_offset;
+         break;
+     case 2:
+-        addr -= 0xb0000;
+-        if (addr >= 0x8000)
++        addr -= 0xb0000 + ISA_MEM_BASE;
++        if (addr >= 0x8000 + ISA_MEM_BASE)
+             return;
+         break;
+     default:
+     case 3:
+-        addr -= 0xb8000;
+-        if (addr >= 0x8000)
++        addr -= 0xb8000 + ISA_MEM_BASE;
++        if (addr >= 0x8000 + ISA_MEM_BASE)
+             return;
+         break;
+     }
+@@ -1642,7 +1653,11 @@ static void vga_save(QEMUFile *f, void *
+     qemu_put_buffer(f, s->dac_cache, 3);
+     qemu_put_buffer(f, s->palette, 768);
+ 
++#if TARGET_PHYS_ADDR_BITS == 32
+     qemu_put_be32s(f, &s->bank_offset);
++#elif TARGET_PHYS_ADDR_BITS == 64
++    qemu_put_be64s(f, &s->bank_offset);
++#endif
+ #ifdef CONFIG_BOCHS_VBE
+     qemu_put_byte(f, 1);
+     qemu_put_be16s(f, &s->vbe_index);
+@@ -1686,7 +1701,11 @@ static int vga_load(QEMUFile *f, void *o
+     qemu_get_buffer(f, s->dac_cache, 3);
+     qemu_get_buffer(f, s->palette, 768);
+ 
++#if TARGET_PHYS_ADDR_BITS == 32
+     qemu_get_be32s(f, &s->bank_offset);
++#elif TARGET_PHYS_ADDR_BITS == 64
++    qemu_get_be64s(f, &s->bank_offset);
++#endif
+     is_vbe = qemu_get_byte(f);
+ #ifdef CONFIG_BOCHS_VBE
+     if (!is_vbe)
+@@ -1758,7 +1777,7 @@ int vga_initialize(DisplayState *ds, uin
+     register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
+     register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
+     register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
+-    s->bank_offset = -0xa0000;
++    s->bank_offset = -(0xa0000 + ISA_MEM_BASE);
+ 
+ #ifdef CONFIG_BOCHS_VBE
+     s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
+@@ -1771,15 +1790,13 @@ int vga_initialize(DisplayState *ds, uin
+ #endif
+ 
+     vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
++    cpu_register_physical_memory(0x000a0000 + ISA_MEM_BASE, 0x20000, vga_io_memory);
+ #if defined (TARGET_I386)
+-    cpu_register_physical_memory(0x000a0000, 0x20000, vga_io_memory);
+ #ifdef CONFIG_BOCHS_VBE
+     /* XXX: use optimized standard vga accesses */
+     cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS, 
+                                  vga_ram_size, vga_ram_offset);
+ #endif
+-#elif defined (TARGET_PPC)
+-    cpu_register_physical_memory(0xf00a0000, 0x20000, vga_io_memory);
+ #endif
+     return 0;
+ }